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Open Youngjaekim-Dissertation.Pdf The Pennsylvania State University The Graduate School DESIGN CHALLENGES ON ENTERPRISE-SCALE STORAGE SYSTEMS EMPLOYING HARD DRIVES AND NAND FLASH BASED SOLID-STATE DRIVES A Dissertation in Computer Science and Engineering by Youngjae Kim c 2009 Youngjae Kim Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy December 2009 The dissertation of Youngjae Kim was reviewed and approved∗ by the following: Anand Sivasubramaniam Professor of Computer Science and Engineering Dissertation Co-Advisor, Co-Chair of Committee Bhuvan Urgaonkar Assistant Professor of Computer Science and Engineering Dissertation Co-Advisor, Co-Chair of Committee Prasenjit Mitra Assistant Professor of Computer Science and Engineering Qian Wang Associate Professor of Mechanical and Nuclear Engineering Raj Acharya Professor of Computer Science and Engineering Head of the Department of Computer Science and Engineering ∗Signatures are on file in the Graduate School. Abstract Flash memory overcomes some key shortcomings of hard disk drives (HDDs), in- cluding faster access to non-sequential data and lower power consumption. Eco- nomic forces, driven by the desire to introduce flash into the enterprise market without changing existing software based, have resulted in the emergence of solid- state drives (SSDs), flash packaged in HDD from factors and capable of working with device drivers and I/O buses designed for HDDs. Unlike the use of DRAM for caching or buffering, however, certain idiosyncrasies of SSDs make their inte- gration into HDD-based systems non-trivial. Flash memory suffers from limits on its reliability, in an order of magnitude more expensive than the disk, and can be sometimes even slower than the HDD (due to excessive GC induced by high intensity of random writes). Given the complementary properties of HDDs and SDDs in terms of cost, performance, and lifetime, the current consensus among several storage experts is to view SSDs not as a replacement for HDD but rather as a complementary device within the storage hierarchy. In my dissertation, I designed and evaluated such a hybrid system called Hy- bridStore to provide (a) improved capacity planning techniques to administra- tors with the overall goal of operating within cost-budgets and (b) improved per- formance/lifetime guarantees during episodes of deviations from expected work- loads through several novel mechanisms such as fragmentation busting and write- regulation. As an illustrative example of HybridStore’s efficacy, a combination of 1 SSD and 6 low-speed, cheaper and higher capacity HDDs is recommended the most cost-effective storage configuration in HybridStore for a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution. Also, HybridStore employing HDD with small SSD is able to reduce the average response time for Financial trace by about 71% as compared to a HDD-based system. In addition to HybridStore project, I developed a novel design technique of iii the Flash Translation Layer (FTL) in the SSD. It provides improved performance, reduced garbage collection overhead, and better overloaded behavior compared to state-of- the art FTL schemes. For example, the Financial trace shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared to a state-of-the-art FTL scheme. Finally, I also developed and validated flash simulation framework call FlashSim. While a number of well-regarded simulation environments exist for HDDs, the same is not yet true for SSDs. This is due to SSDs having been in the storage market for relatively less time as well as the lack of information (hardware configuration and software methods) about state-of-the-art SSDs that is publicly available. FlashSim aimed at filling this void in performance evaluation of emerging storage systems that employ SSDs. iv Table of Contents List of Figures vi List of Tables vii Acknowledgments viii Chapter 1 Introduction 1 1.1 Read-map ................................ 4 Chapter 2 Background and Related Work 5 2.1 BasicsofFlashMemoryTechnology. 5 2.2 Characteristics of Flash Memory Operations . ... 7 2.3 Flash Memory based Solid State Disk Drive . 8 2.3.1 NANDFlashbasedSSDs. 8 2.3.2 DetailsofFlashTranslationLayer. 9 2.3.3 GarbageCollectioninHybridFTLs . 12 2.4 RelatedWork .............................. 14 Chapter 3 Improvements in Solid-state Disk Drive 18 3.1 Introduction............................... 18 3.2 Motivation................................ 19 3.3 Design of DFTL: Our Demand-based Page-mapped FTL . 20 3.3.1 DFTLArchitecture . 21 3.3.2 Logical to Physical Address Translation . 22 3.3.3 Read/Write Operation and Garbage Collection . 25 v 3.3.4 Dealing with Power Failure . 28 3.3.5 Comparison of State-of-the-art FTLs with DFTL . 29 3.4 FlashSim: A Simulator for NAND Flash-based Solid-State Drives . 31 3.4.1 MotivationforASimulatorFramework . 31 3.4.2 SSDSimulatorDesign . 32 3.4.2.1 Object-Oriented Component Design . 33 3.4.2.2 Bus Channel Interleaving . 37 3.4.2.3 EventFlow ...................... 38 3.4.3 ValidationofSSDSimulator . 41 3.4.4 SummaryandFutureWork . 43 3.5 Experimental Results Using FlashSim . 44 3.5.1 Garbage Collection and Address Translation Overheads... 46 3.5.2 PerformanceAnalysis. 49 3.5.3 Exploring a Wider Range of Workload Characteristics . ... 52 3.5.4 MicroscopicAnalysis . 53 3.5.5 Impact of SRAM size for Mapping Entries . 54 3.5.6 Analysis of Energy Consumption . 55 3.5.7 ImpactofSSDCache. 57 3.6 ConcludingRemarks .......................... 58 Chapter 4 Capacity Planning in HybridStore 60 4.1 Introduction............................... 60 4.2 MotivationforHybridStore . 63 4.3 OverviewofHybridStore . 66 4.4 Capacity Planning: MixPlan . 66 4.4.1 ProblemFormulation . 68 4.4.2 Finding optimal solution by MixPlan . 71 4.5 EvaluationforMixPlan. 74 4.5.1 Experimental Setup and Workloads . 74 4.5.2 Hierarchical Data Classification . 76 4.5.3 BandwidthofDevices . 76 4.5.4 EconomicalStorageConfiguration. 77 4.5.4.1 CanSSDsreplaceHDDs? . 77 4.5.4.2 Efficiency of Hybrid System . 79 4.5.5 Impactofvariablefactors . 80 4.5.5.1 What if price fluctuation of device? . 80 4.5.5.2 What if not considering recurring cost? . 80 4.6 ConcludingRemarks .......................... 81 vi Chapter 5 Dynamic Management in HybridStore 83 5.1 Introduction............................... 83 5.2 Modeling Performance and Lifetime of Flash Memory . ... 84 5.2.1 Regression Based Modeling . 85 5.2.2 Validation ............................ 86 5.2.3 Why MixPlan Alone Doesn’t Suffice . 88 5.3 DynamicController:MixDyn . 89 5.3.1 Short-Term Performance Prediction Model for SSD . 89 5.3.2 Evaluation with Dynamism-Aware Performance Predictor. 90 5.3.3 FragmentationBusting . 91 5.3.4 Handling Uncertainties in Enterprise-scale Workloads............................ 94 5.3.4.1 WriteRegulation . 94 5.3.4.2 Adaptive Wear-Leveling . 94 5.4 Evaluation................................ 95 5.4.1 Experimental Setup and Workloads . 95 5.4.2 EvaluationofMixPlan . 97 5.4.2.1 Lifetime Budget Constraint . 97 5.4.2.2 Performance Budget Constraint . 98 5.4.3 MixDyn Acting in Concert with MixPlan . 100 5.4.3.1 Dynamism-Aware Performance Prediction . 100 5.4.3.2 FragmentationBusting. 102 5.4.3.3 WriteRegulation . 103 5.4.3.4 Adaptive Wear-Leveling . 104 5.5 ConcludingRemarks . 105 Chapter 6 Conclusion and Future Work 106 6.1 Summary ................................106 6.2 FutureWork...............................107 Bibliography 109 vii List of Figures 2.1 A Block Diagram of Flash based Solid State Disk Drive. ........ 9 2.2 Page-level FTL scheme. LPN: Logical Page Number, PPN: Physical Page Number, LBN: Logical Block Number, PBN: Physical Block Num- ber. ................................... 11 2.3 Block-level FTL scheme. LPN: Logical Page Number, PPN: Physical Page Number, LBN: Logical Block Number, PBN: Physical Block Num- ber. ................................... 11 2.4 Hybrid FTL Scheme, combining a block-based FTL for data blocks with a page-based FTL for log blocks. LPN: Logical Page Number, PPN: Physical Page Number, LBN: Logical Block Number, PBN: Physical Block Number. ............................. 12 2.5 Various Merge operations (Switch, Partial, and Full) in log-buffer based FTL schemes. V: Valid, I: Invalid, and F: Free/Erased and LPN is Logical Page Number. .......................... 13 2.6 Expensive Full Merge. .......................... 14 3.1 Schematic Design of DFTL. DLP N : Logical Data Page Number, DP P N : Physical Data Page Number, MV P N : Virtual Translation Page Number, MP P N : Physical Translation Page Number. 21 3.2 (1) Request to DLP N 1280 incurs a miss in Cached Mapping Ta- ble (CMT), (2) Victim entry DLP N 1 is selected, its corresponding translation page MP P N 21 is located using Global Translation Di- rectory (GTD), (3)-(4) MP P N 21 is read, updated (DP P N 130 → DP P N 260) and written to a free translation page (MP P N 23), (5)- (6) GTD is updated (MP P N 21 → MP P N 23) and DLP N 1 entry is erased from CMT. (7)-(11) The original request’s (DLP N 1280) translation page is located on flash (MP P N 15). The mapping en- try is loaded into CMT and the request is serviced. Note that each GTD entry maps 512 logically consecutive mappings. 24 viii 3.3 Example: (1) Translation Block (MP BN B1) is selected as Victim for Garbage Collection. (2) Valid pages MP P N 12 & MP P N 13 are copied to the Current Translation Block (MP BN B2) at free pages MP P N 22 & MP P N 23. (3) Global Translation Directory entries corresponding to MV P N 0 & MV P N 2 are updated (MP P N 12 → MP P N 22, MP P N 13 → MP P N 23. .................. 26 3.4 Example: (1) Data Block (DP BN B3) is selected as Victim for Garbage Collection. (2) Valid pages DP P N 110 & DP P N 111 are copied to the Current Data Block (DP BN B4) at free pages DP P N 202 & DP P N 203.
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