Recent Researches in Circuits, Systems, Control and Signals

A Buck Converter for DVS Compatible Processors in Mobile Computing Applications Using Fuzzy Logic Implemented in a RISC based Microcontroller

Monaf S. Tapou , Hamed S. AlRaweshidy, Maysam Abbod, Manal J. AlKindi

Abstract—The design of voltage regulators for mobile power converter must provide these output changes while computing applications is complicated by several factors that lead maintaining high efficiency over the whole operating range. to making tradeoffs between efficiency, voltage ripple and dynamic That makes the power converter a very important part in response. Careful choices must be made in selecting the passive any system that requires voltage scaling. Mobile computing and active components order to accommodate for the performance figures required to achieve compatibility for DVS ready devices like Netbooks, Tablets, and PDAs are supplied with processors. power packs that consist of several Lithiumion / polymer A suitable control scheme must be selected that can suffice the cells connected in series with nominal voltages of 11.1 Volts stability and dynamic response required. This paper describes the or more. This voltage is then reduced using mode design of Buck converter that has a fuzzy controller implemented regulators in buck topology to provide for the variety of using Atmel Atmega189 RISC Based microcontroller with a choice voltages required to operate the various circuitries inside the of hardware components that will ensure better efficiency while mobile device. delivering good stability and dynamic response. System simulation was carried out using MATLAB/SIMULINK. Simulation results showed that the fuzzy controller has the capability of providing II. RELATED WORKS response characteristics that makes it comparable with PID DVS compatible power supply designs are always under controllers and more suitable for implementation using continuous development with variety of ideas, systems microcontrollers. configurations and Control algorithms. Keywords— Fuzzy Logic Control, Buck Converter, Zhang et. al. proposed a digital PWM/PFM controller Microcontrollers, PID, RISC, DVS. with automatic mode switching [15]. While the propose design comprises good efficiency distribution over wide I. INTRODUCTION operating ranges but the hardware complexity and power educing power consumption in mobile computing consumption makes the design successful for high powered R systems has an important role in achieving longer processors like those implemented in laptop computers with running time on a single charge of the equipment battery efficiency figure between 86 % and 82%. along with reducing power dissipation resulting in the Dhar et.al. describes a switching regulator that has the possibility of reducing equipment size. The dynamic voltage capability to change supply voltage as required by and frequency scaling (DVS) is a technique that is being application using a modified Watkins Johnson converter increasingly applied in modern microprocessor designs. It [16] implementing a simple Bang Bang controller to obtain enables tailoring power in accordance with the fast transient response along with AVS (Automatic Voltage application requirements, and since different application Scaling ) controller implemented on a single chip using required different computational power in order to execute a standard CMOS process. The end system has all given task, it becomes possible to reduce processor components including and implemented performance when not needed. This is accomplished by using CMOS technology which means the converter will reducing processor clock frequency along with core voltage. work at several MHz frequency. The resulting efficiency varies between 80% to 90 when operated at 20MHz to The equation below shows that dynamic power consumed 30MHZ. by processor circuitries which are implemented in CMOS Gupta et.al. proposed a Fuzzy controller for DCDC technology [1]: converter using 87C752 microcontroller form Intel [17]. 2 Dynamicα ⋅ fCVP ⋅ clkeffdd They have demonstrated that stable responses can be (1) obtained from any converter topology (Buck or Boost) without any change in control program. where Vdd is supply voltage, Ceff is the total capacitance of the nodes weighted with its activity factor, and f is the clk III. DESIGNING A DVS COMPATIBLE POWER clock frequency. CONVERTER It can be observed that reducing the clock frequency alone would not affect the power consumption greatly as a given DVS compatible power converters have special task will require the same number of clock cycles to finish requirements as they work on a variable load that needs to but the great power reduction comes from reducing the change its operating voltage in accordance with the supply voltage which comes possible when operating requirements of the running software. Along with this comes additional requirements, these include the need for faster CMOS circuitry at lower frequency. This action proves to transition times during load changes [3]. The DVS contribute to a great reduction in power consumed by the compatible converter works in two main modes. processor which consumes about 58% of the total power • Regulation mode where the converter tries to keep needed by any computer system [2]. the voltage supplied to the load constant. The main component in the system that can provide for • Tracking mode where the regulator starts these reductions in power is the power converter of the changing the output voltage as requested by the system. The DVS compatible processor requires a special DVS scheduler. converter design that can provide variable output voltages according to DVS system requirement. Along with that the

ISBN: 978-1-61804-035-0 135 Recent Researches in Circuits, Systems, Control and Signals

To start designing the buck converter required, one must )( ⋅− VVV first choose the target processor, as an example, a processor L = IN OUT OUT is selected from Intel XScale family of DVS compatible ⋅⋅ IfV LswIN processor namely the PXA270. The power requirements for (2) this processor has been investigated [4][5] and it requires where L is in Henries, IL is the peak current ripple five separate converters one of which must be DVS in Amperes and is usually chosen between 20% to 40% compatible in order to utilize the power reduction from the maximum load current [8][9]. This equation results capabilities of this processor. This converter supplies the in L values ranging from 115.7H to 231.5H. Larger core of the processor which works on a voltage ranging values give lower output voltage ripple but reduce the from 0.85Volts at low workloads to 1.55 Volts at peak dynamic response of the system [3][9]. workloads with maximum core power figure of 925mW. IL,max is the maximum current flowing through the inductor Other system parameters are also being put into and is calculated for the following equation [9]: consideration while calculating component values for the I L max, Buck converter design. I L max, I OUT max, += Before starting the calculation, the choice of the 2 microcontroller is to be made and that has been done (3) comparing features of microcontroller families from several An inductor with ISAT large than IL,max (0.908A) must be manufacturers while keeping in mind the power selected to avoid saturating the magnetic core material consumption figure for the microcontroller in addition to which will result in poor regulation and larger inductor integrated peripherals and instruction set. DSPs were not losses. included in the search because of their relatively high power As the DVS compatible converter requires fast response, L consumption figures that render them inadequate for mobile is selected to be close to the minimum value. applications. The maximum allowable overshoot in supply voltage is The PIC16FXX from Microchips, and AVR ATmegaxx taken from the data sheet [4] to be 10% of the output from Atmel. The choice has fallen on the RISC based voltage. This value will be used to calculate the Atmega169 for having very low power consumption figure (C) as follows [9]: and a host of analogue peripherals and its instruction set 2 ⋅ IL L max, )( provides better flexibility than that of the PIC16FXX family C = 22 [6][7]. ( OUT + VV OUT ,overshoot ) −VOUT The pulse width modulator frequency that is to be (4) implemented using the Atmel mega169 microcontroller is From the above equation a capacitor value of about 180 selected to be 40 KHz. This figure will make it possible to F is found. The choice of capacitors must be made while implement the digitally controlled buck converter while considering another factor called the effective series maintaining low power operation of the microcontroller in resistance of the capacitor (ESR). This figure can be use. calculated from the equation given below [9]: The careful selection of design components will ensure VOUT ,overshoot higher efficiency, in case of switching elements, the ESR = MOSFET , these will be selected according to I L max, their figure of merit (FOM) which is based on channel ON (5) resistance (RDSon) and gate charge (QG) these two figures The calculated ESR value is 170m, the capacitor reflects the conduction losses of the device and its drive selected should have it ESR figure below that but if power charge requirements. Selecting having the efficiency is of prime importance the capacitor selected lowest possible figures for FOM with the required voltage must be of low ESR type like Polymer Cathode Tantalum, and current ratings will result in a better converter design. Solid Aluminum Polymer Electrolyte or Ceramic thin film The TI CSD17312Q5 MOSFET for switch and the TI capacitors. Figure 1 shows the block diagram of the CSD16312Q5 MOSFET for synchronous [11] were proposed buck converter. chosen for having a very low FOM in addition to a 1.1Volts L gate threshold voltage which simplifies driving CSD173 12Q5 11 6 micro H requirements. 22 micro F. 11 .1 Volts As the topology chosen for the buck converter is the one BATTERY Cin + C that uses synchronous rectifier, the TI UCC27222 Gate 18 0 micro F. UCC2 72 22 CSD163 12Q5 Sy nchronou s Buck PXA 270 Driving IC [12] is selected to simplify MOSFET gating and Procssor Core has a predictive gate timing function the helps eliminating PWM and Control cross currents and actively boost efficiency. Voltage Feedback Sign al ATmel ATmega169 to ADC input To calculate the values of the passive components and at Microcontroller the same time adhering with common design methodologies followed in buck converters for DVS applications [3][8] the choice of the components will be made as follows: Fig. 1 buck converter proposed design for PXA270 core supply After setting input and output voltages, maximum load current, and converter frequency, the value of the inductor is calculated from the following equation [9]: The designed converter losses were calculated [8][13] for the selected components according to the operating conditions given in the design. The design yielded a 92.02% efficiency figure sustainable over wide operating conditions

ISBN: 978-1-61804-035-0 136 Recent Researches in Circuits, Systems, Control and Signals for the specific load. Table I shows the power loss and the to change mimicking a battery operating from a fully efficiency figures expected for the designed buck converter. charged state until becoming flat. Figure 3 shows the TABLE I SIMULINK model built for the buck converter along with POWER LOSSES AND EFFICIENCY OF THE DESIGNED BUCK the testing block. CONVERTER VIN=11.1 Volts, VOUT=1.55 Volts, P LOAD=925mWatts, FConverter=40KHz Component Power loss MOSFET Switch CSD17312Q5 1.308mWatts MOSFET Sync. RECT. CSD16312q5 2.071mWatts Inductor L (ESR=10.02m) 3.352mWatts Capacitor C (ESR=30m) 2.488mWatts Gate Driver UCC27222 48.84mWatts RISC Microcontroller ATmega169 15.51mWatts Total Loss 73.569mWatts Efficiency 92.63%

Fig. 3 the SIMULINK model for the buck converter with the line IV. SELECTING CONTROLLER AND PERFORMING and load testing elements. CIRCUIT SIMULATION While general purpose DCDC converters are commonly The Fuzzy controller being selected for the buck designed implementing a linear controller of some sort for converter design due to the fact that this type of controllers example linear proportional – integral (PI) or proportional can deliver performance figures and operational flexibility integral –derivative (PID) controllers. In these cases an required with out demanding exact mathematical models or accurate model for the converter becomes essential to obtain the need for complex computational power to a given performance standard. Linear control strategies perform[17][21]. Thus, Fuzzy based controller design would usually attempt to linearize the dynamics behavior for a be very applicable when RISC based micropower certain operating region depending on the mathematical microcontrollers are considered. model of the system. The resulting controller will be useful Fuzzy logic control provides a formal methodology for for limited operating range and this is not the case with the representing, manipulating and implementing a human’s DCDC converters designed to be DVS compatible thus the heuristic knowledge about how to control a system. requirement for a control system that can cope with these Basically it is an artificial decisionmaker that operates in a variations becomes necessary. These include non linear PID closed loop system in real time. It gathers plant output data, controller, Fuzzy controllers and Neural Network controllers compares it to reference input and then decides what the along with other variations. With the exception of the Fuzzy plant input should be to ensure that the performance controller, other controllers implementation requires larger objective will be met. software overhead which renders them in applicable to The Design of a fuzzy logic controller consists of four simple microcontrollers, and their implementation requires components: Fuzzification, Fuzzy Rule Base, Fuzzy using DSP processors or FPGA devices [14 ]. Inference Engine, and Defuzzification [21]. The MATLAB/SIMULINK is used to design a model for a fuzzification process converts the real input (usually error buck converter [22]. The model was built observing the and change of error) to fuzzy universe of discourse to basic Buck Converter Circuit show in figure 2. produce corresponding fuzzy inputs. These inputs are fed into the fuzzy inference engine, where certain fuzzy rules coming from the fuzzy rule base are triggered according to the fuzzy input variables. These triggered rules produce the output variable which in turn is defuzzified by the defuzzification engine to the real world universe of discourse and the o/p is used as the plant input [21]. Figure 4 shows the design components for a fuzzy controller. Fig. 2 basic buck converter circuit where S1 is the MOS Switch and S2 is the MOS synchronous rectifier, VS is the source voltage, VO is the output voltage, Lm is the converter Main Inductance, Cm is the main capacitor and RL id the load resistance. The analysis method of this converter has followed the literature of references [18][19][20]. The constructed SIMULINK model included the additional details of circuit components Fig. 4 the design components of a fuzzy controller like the RDSon of the switch and synchronous rectifier MOS transistors, ECR of the Inductor and Capacitor. In addition The implemented fuzzy logic controller consists of one to that the model has included elements for conducting line, fuzzy algorithm in which the error and change of error are load regulation, and transient response analysis where the fed to the controller and interpreted into linguistic terms load resistance was change and the effect on the controller using the fuzzyfire. Throughout the conducted tests, it was behavior was observed. The Source voltage has been made noticed that using the Gaussian distribution membership

ISBN: 978-1-61804-035-0 137 Recent Researches in Circuits, Systems, Control and Signals

function resulted in smoother control action. This function is where N is the number of the used interval, i is the degree described by [21]: of membership of every output variable corresponding to 2 each error, change of error, and sum of error group. U is the (x) exp 1 (( −−= xm )/. σ ) ( 2 ) crisp o/p of the controller. (6) where m is the center of the membership function (mean), σ is the width of the membership function (standard deviation) and x is the input variable. The number of fuzzy sets that were used in the simulation is seven, as smaller set did not give the desired smoothness while larger fuzzy set required larger tables and algorithms. They were distributed normally along the universe of discourse for error, change of error and the control action, as shown in figure 5.

Fig. 5 the membership function distribution along the universe of discourse for the error, change of error and the output (U). Fig. 6 control surface of table II rules

The designed fuzzy controller performance has been tested against a tuned PID controlled buck converter to get the load regulation characteristics. In both cases the From this figure, it can be observed that there are seven controller was subjected to load change from light load linguistic fuzzy sets which are: NB for negative big, NM for (CPU core idle ILoad=167mA) to Heavy load (CPU core full negative medium, NS for negative small, Z for zero, PS for activity ILoad=597mA). The resulting transient response has positive small, PM for positive medium and PB for positive been recorded and shown in figure 7. big, CE for change of error and E is the error signal= output (measured) input (desired). 1.625 The fuzzy rules were derived by experience and through PID Controller 1.6 the observation of the control action along with the transient Fuzzy Controller and steady state response and were checked against several 1.575

design cases of Fuzzy controlled buck converters in order to 1.55 improve the rule table. This rule table is shown in table II. 1.525 Table II FUZZY RULE SET IMPLEMENTED IN THE CONTROLLER DESIGN 1.5 Output Voltage Output E 1.475 NB NM NS Z PS PM PB CE 1.45 NB NB NB NB NM NM NS Z 1.425 NM NB NB NM NM NS Z PS 5 10 15 20 25 Sampling Time 1mSec NS NB NM NM NS Z PS PM

Fig. 7 load change transient response of the buck Z NM NM NS Z PS PM PM converter when operated with a PID controller (solid

PS NM NS Z PS PM PM PB line) and a fuzzy controller (dashed line).

PM NS Z PS PM PM PB PB The following differences were observed: the PID controller was tuned to have response characteristics that PB Z PS PM PM PB PB PB makes the end response fast with an overshoot that would be lower than target load limit set by the manufacturer, This This table will give the control surface shown in figure 6. PID controller had an overshoot that was about 6.5% form the output and that was within the allowable limits set by the For the defuzzification process, the center of gravity target load electrical specifications, steady state was reached method is used and is given by [21]: after 4.6milliSeconds and there was no measurable error in N the steady state output. The fuzzy controller had a Lower ∑ ().uu ii overshoot that was 4.8% of the output and reached steady i=0 state after about 4.75 milliseconds and had a steady state U = N ()u error figure of less than 0.3%. From these results, it can be ∑ i concluded that: i=0 (7)

ISBN: 978-1-61804-035-0 138 Recent Researches in Circuits, Systems, Control and Signals

• The Fuzzy controller had a little slower response [11] Texas Instruments, NexFET Power MOSFETs Quick Reference than the PID controller. Guide. 2010 Texas Instruments Incorporated. Data Sheet. [12] Texas Instruments, UCC27222 High Efficiency Synchronous Buck • The Fuzzy controller had smaller overshoot than Gate Drivers. 2003 SLUS486b Texas Instruments Incorporated. Data the PID controller. Sheet. • The Fuzzy controller had a small steady state error [13] Jauregui D.; Wang B.; Chen R.; Power Loss Calculation with Common Source Inductance consideration for Synchronous Buck while the PID controller showed no steady state Converters. SLPA00920011 Texas Instruments Application Report. error. [14] Guo L.; Hung J.Y.; Nelms R.M.; Evaluation of DSPBased PID and The designed fuzzy controller provided more flexible Fuzzy Controllers for DC_DC Converters. IEEE Transactions on operating performance suitable for a DVS ready system as Industrial Electronics Vol. 56 No.6 June 2009/ [15] Zahng Z.; Maksimovic D.; Digital PWM/PFM Controller with Input changing the output voltage of the converter didn’t require Voltage FeedForward for Synchronous Buck Converters. APEC changing the fuzzy set rules while the PID Controller 2008. 23rd Annual IEEE. required retuning of its parameters in order to yield the same [16] Dhar S.; Maksimovic D.; Switching Regulator With Dynamically th response characteristics. Adjustable Supply Voltage for Low Power VLSI. IECON’01. 27 Annual Conference of the IEEE industrial Electronics Society. [17] Gupta T.; Boudreaux R.R.; Implementation of a Fuzzy Controller for V. CONCLUSION DCDC Converter Using an Inexpensive 8b Microcontroller. IEEE Transactions on Industrial Electronics. Vol. 44, No. 5, October 1997. In this paper a design for a buck converter suitable to [18] Hart D.W.; Introduction to Power Electronics, Prentice Hall Inc. supply the core of a DVS ready processor (PXA270) was 1997. proposed. Careful selection of components was made in an [19] Mohan N.; Underland T.M.; Robbins W.P.; Power Electronics: attempt to efficiency. Low ESR capacitor Converters Applications and Design, John Wiley and Sons 1995. [20] Su J.H.; Chen J.J.; Learning Feedback Controller Design of Switching and low leakage inductors in addition to selecting MOS Converters Via MATLAB/SIMULINK. IEEE Transaction on devices with very low FOM were chosen to minimize power Education Vol.45 No.4 November 2002. loss and enhance performance. Further more, the MOS gate [21] REZNIK L.; Fuzzy Controllers . Newnes, 1997.ISBN 0 7506 3429 4. driver device chosen has a unique feature of dynamically [22] Jain S.; Azad M.; Modeling and Simulation Using MATLAB SIMULINK. 2011 WileyIndia ISBN 9788126530052. selecting dead zone between gating the MOS switch and the MOS synchronous rectifier thus resulting in better cross current prevention yielding higher efficiency. The proposed microcontroller (ATmega169) has a very low operating Monaf Sabri Tapou is a Lecturer in the Control and System Engineering power in addition to a powerful RISC designed instruction Department – University of Technology Baghdad. He was born in 1959. He set that permits performing good control function which is earned his BSc. degree in Electronics Engineering from the Electrical being implemented using a fuzzy controller. This Engineering Department – University of Technology Baghdad in 1981, microcontroller has been incorporated with several serial M.Sc. degree in Computer Engineering from the Control and System Engineering department – University of Technology Baghdad in 1988. He buses, this feature can ease the transaction between the main is currently conducting a PhD. Research in the School of engineering and processor and the power management microcontroller in Design, Brunel Univeersity. His research interest is in investigating in low implementing DVS functions. The proposed fuzzy controller power techniques in modern computer systems. performance was compared against a tuned PID controller. He can be contacted at this email: [email protected].

The results promote using the fuzzy based controller with Hamed Al-Raweshidy is a research professor and the head of the Wireless much better flexibility and lower software overhead than the Networks & Communications Research Group in the School of Engineering case when controller structure of another type would be and Design at Brunel University. His research interests include network suggested. The overall system efficiency is expected to be optimization, mesh and ad hoc networks, radio over fiber, PAN and PN, and IP mobility. He received his PhD for work in spread spectrum higher than 92% that can be maintained over wide operating multiplexing for communication networks. He holds a number of projects conditions by Adapting variable frequency PWM when with EPSRC and EU. He’s a senior member of the IEEE, an IEE fellow, operating at different output voltages and switching to PFM and a member of New York Academy of Sciences. Contact him at the for low power loads. Wireless Networks & Communications Group, School of Eng. and Design, Brunel Univ., Uxbridge, Middlesex UB8 3PH, UK; Hamed.Al [email protected]. REFERENCES [1] Soto A,; Alou,p.; Cobos,J.A.; Uceda,J.; The Future DCDC Converter Maysam Abbod was born in 1966. He has finished his BSc degree in as an Enabler of Low Energy Consumption System with Dynamic electronics from the University of Technology, Baghdad in 1987 and PhD Voltage Scaling. IECON 02 , IEEE 2002 28th. degree in Control Engineering for the University of Sheffield in 1992. His [2] Pering T.; Burd T.; Brodersen R.; Dynamic Voltage Scaling and the research work is of a multidisciplinary nature ranging from biomedical Design of a Low –Power Microprocessor System. ISCA 1998. applications to industrial applications. He has been a Research Fellow [3] Soto A,; Alou,p.; Cobos,J.A.; Design Methodology for Dynamic working for the Institute for Microstructural and Mechanical Process Voltage Scaling in the Buck Converter. APEC 2005, 20th Annual Engineering, The University of Sheffield (IMMPETUS) on modeling of IEEE. material properties using hybrid modeling techniques. His research interests [4] Intel, PXA270 Processor, Electrical, Mechanical, and Thermal include intelligent systems for modeling and optimization. Currently he is a Specifications. Data Sheet. lecturer in Intelligent Systems in the School of Engineering and Design, [5] Intel, PXA27x Processor Family Power Requirements. Application Brunel University. Note. Dr Abbod is a member of the IET and Chartered Engineer. His email [6] ATmel, ATmega169 8bit AVR microcontroller with 16K Byte in address: [email protected] system Programmable Flash. Data Sheet. [7] Microchip, PIC16F87XA Enhanced Flash Microcontroller. 2003 Dr. ManalJ. ALKindi is an Assitant Lecturer currently working at the Microchip Technology Incorporated. Data Sheet. Department of Electrical and Electronic Engineering AlNahrain [8] Wu K.C.; Pulse Width Modulated DCDC Converters. 1997 by University Baghdad. He had his BSc. Engineering from The Electerical Chapman & Hall ISBN 0412105411. Engineering Department – University of Technology Baghdad. He obtained [9] Microchip, Buck Converter Design Example. 2006 Microchip his PhD. From University of Strathclyde Glasgow – UK. He can be Technology Incorporated. Application Note. contacted thorugh this email address: Manal [email protected] [10] Freescale, Selecting L and C Components in Power Stage of Switching Regulators. 2010 Freescale Semiconductors Incorporated. Application Note.

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