Recent Researches in Circuits, Systems, Control and Signals A Buck Converter for DVS Compatible Processors in Mobile Computing Applications Using Fuzzy Logic Implemented in a RISC based Microcontroller Monaf S. Tapou , Hamed S. Al-Raweshidy, Maysam Abbod, Manal J. Al-Kindi Abstract—The design of voltage regulators for mobile power converter must provide these output changes while computing applications is complicated by several factors that lead maintaining high efficiency over the whole operating range. to making tradeoffs between efficiency, voltage ripple and dynamic That makes the power converter a very important part in response. Careful choices must be made in selecting the passive any system that requires voltage scaling. Mobile computing and active components order to accommodate for the performance figures required to achieve compatibility for DVS ready devices like Netbooks, Tablets, and PDAs are supplied with processors. power packs that consist of several Lithium-ion / polymer A suitable control scheme must be selected that can suffice the cells connected in series with nominal voltages of 11.1 Volts stability and dynamic response required. This paper describes the or more. This voltage is then reduced using switch mode design of Buck converter that has a fuzzy controller implemented regulators in buck topology to provide for the variety of using Atmel Atmega189 RISC Based microcontroller with a choice voltages required to operate the various circuitries inside the of hardware components that will ensure better efficiency while mobile device. delivering good stability and dynamic response. System simulation was carried out using MATLAB/SIMULINK. Simulation results showed that the fuzzy controller has the capability of providing II. RELATED WORKS response characteristics that makes it comparable with PID DVS compatible power supply designs are always under controllers and more suitable for implementation using continuous development with variety of ideas, systems microcontrollers. configurations and Control algorithms. Keywords— Fuzzy Logic Control, Buck Converter, Zhang et. al. proposed a digital PWM/PFM controller Microcontrollers, PID, RISC, DVS. with automatic mode switching [15]. While the propose design comprises good efficiency distribution over wide I. INTRODUCTION operating ranges but the hardware complexity and power educing power consumption in mobile computing consumption makes the design successful for high powered R systems has an important role in achieving longer processors like those implemented in laptop computers with running time on a single charge of the equipment battery efficiency figure between 86 % and 82%. along with reducing power dissipation resulting in the Dhar et.al. describes a switching regulator that has the possibility of reducing equipment size. The dynamic voltage capability to change supply voltage as required by and frequency scaling (DVS) is a technique that is being application using a modified Watkins Johnson converter increasingly applied in modern microprocessor designs. It [16] implementing a simple Bang Bang controller to obtain enables tailoring processor power in accordance with the fast transient response along with AVS (Automatic Voltage application requirements, and since different application Scaling ) controller implemented on a single chip using required different computational power in order to execute a standard CMOS process. The end system has all given task, it becomes possible to reduce processor components including inductors and capacitors implemented performance when not needed. This is accomplished by using CMOS technology which means the converter will reducing processor clock frequency along with core voltage. work at several MHz frequency. The resulting efficiency varies between 80% to 90 when operated at 20MHz to The equation below shows that dynamic power consumed 30MHZ. by processor circuitries which are implemented in CMOS Gupta et.al. proposed a Fuzzy controller for DC-DC technology [1]: converter using 87C752 microcontroller form Intel [17]. 2 Dynamicα ⋅ fCVP ⋅ clkeffdd They have demonstrated that stable responses can be (1) obtained from any converter topology (Buck or Boost) without any change in control program. where Vdd is supply voltage, Ceff is the total capacitance of the nodes weighted with its activity factor, and f is the clk III. DESIGNING A DVS COMPATIBLE POWER clock frequency. CONVERTER It can be observed that reducing the clock frequency alone would not affect the power consumption greatly as a given DVS compatible power converters have special task will require the same number of clock cycles to finish requirements as they work on a variable load that needs to but the great power reduction comes from reducing the change its operating voltage in accordance with the supply voltage which comes possible when operating requirements of the running software. Along with this comes additional requirements, these include the need for faster CMOS circuitry at lower frequency. This action proves to transition times during load changes [3]. The DVS contribute to a great reduction in power consumed by the compatible converter works in two main modes. processor which consumes about 58% of the total power • Regulation mode where the converter tries to keep needed by any computer system [2]. the voltage supplied to the load constant. The main component in the system that can provide for • Tracking mode where the regulator starts these reductions in power is the power converter of the changing the output voltage as requested by the system. The DVS compatible processor requires a special DVS scheduler. converter design that can provide variable output voltages according to DVS system requirement. Along with that the ISBN: 978-1-61804-035-0 135 Recent Researches in Circuits, Systems, Control and Signals To start designing the buck converter required, one must ()VVV− ⋅ first choose the target processor, as an example, a processor L = IN OUT OUT is selected from Intel XScale family of DVS compatible VIN⋅ f sw ⋅ ∆ I L processor namely the PXA270. The power requirements for (2) this processor has been investigated [4][5] and it requires where L is in Henries, ∆IL is the peak inductor current ripple five separate converters one of which must be DVS in Amperes and is usually chosen between 20% to 40% compatible in order to utilize the power reduction from the maximum load current [8][9]. This equation results capabilities of this processor. This converter supplies the in L values ranging from 115.7µH to 231.5µH. Larger core of the processor which works on a voltage ranging values give lower output voltage ripple but reduce the from 0.85Volts at low workloads to 1.55 Volts at peak dynamic response of the system [3][9]. workloads with maximum core power figure of 925mW. IL,max is the maximum current flowing through the inductor Other system parameters are also being put into and is calculated for the following equation [9]: consideration while calculating component values for the ∆I L,max Buck converter design. I L,max =I OUT ,max + Before starting the calculation, the choice of the 2 microcontroller is to be made and that has been done (3) comparing features of microcontroller families from several An inductor with ISAT large than IL,max (0.908A) must be manufacturers while keeping in mind the power selected to avoid saturating the magnetic core material consumption figure for the microcontroller in addition to which will result in poor regulation and larger inductor integrated peripherals and instruction set. DSPs were not losses. included in the search because of their relatively high power As the DVS compatible converter requires fast response, L consumption figures that render them inadequate for mobile is selected to be close to the minimum value. applications. The maximum allowable overshoot in supply voltage is The PIC16FXX from Microchips, and AVR ATmegaxx taken from the data sheet [4] to be 10% of the output from Atmel. The choice has fallen on the RISC based voltage. This value will be used to calculate the capacitor Atmega169 for having very low power consumption figure (C) as follows [9]: and a host of analogue peripherals and its instruction set 2 LI⋅ ()L,max provides better flexibility than that of the PIC16FXX family C = 2 2 [6][7]. (VVOUT + ∆ OUT ,overshoot ) −VOUT The pulse width modulator frequency that is to be (4) implemented using the Atmel mega169 microcontroller is From the above equation a capacitor value of about 180 selected to be 40 KHz. This figure will make it possible to µF is found. The choice of capacitors must be made while implement the digitally controlled buck converter while considering another factor called the effective series maintaining low power operation of the microcontroller in resistance of the capacitor (ESR). This figure can be use. calculated from the equation given below [9]: The careful selection of design components will ensure ∆VOUT ,overshoot higher efficiency, in case of switching elements, the ESR = MOSFET transistors, these will be selected according to I L,max their figure of merit (FOM) which is based on channel ON (5) resistance (RDSon) and gate charge (QG) these two figures The calculated ESR value is 170mΩ, the capacitor reflects the conduction losses of the device and its drive selected should have it ESR figure below that but if power charge requirements. Selecting MOSFETS having the efficiency is of prime importance the capacitor selected lowest possible figures for FOM with the required voltage must be of low ESR type like Polymer Cathode Tantalum, and current ratings will result in a better converter design. Solid Aluminum Polymer Electrolyte or Ceramic thin film The TI CSD17312Q5 MOSFET for switch and the TI capacitors. Figure 1 shows the block diagram of the CSD16312Q5 MOSFET for synchronous rectifier [11] were proposed buck converter. chosen for having a very low FOM in addition to a 1.1Volts L gate threshold voltage which simplifies driving CSD173 12Q5 11 6 micro H FUSE requirements. 22 micro F. 11 .1 Volts As the topology chosen for the buck converter is the one BATTERY Cin + C that uses synchronous rectifier, the TI UCC27222 Gate 18 0 micro F.