Algorithms and Data Structures for External Memory Algorithms and Data Structures 2:4 for External Memory Jeffrey Scott Vitter
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United States Patent (10) Patent N0.: US 7,290,102 B2 Lubbers Et A]
US007290102B2 (12) United States Patent (10) Patent N0.: US 7,290,102 B2 Lubbers et a]. (45) Date of Patent: Oct. 30, 2007 (54) POINT IN TIME STORAGE COPY 5,184,281 A 2/1993 Samarov et al. 5,513,314 A 4/1996 Kandasamy et al. (75) Inventors: Clark E. Lubbers, Colorado Springs, 5,815,371 A 9/ 1998 Jeiffies et a1~ CO (US); James M. Reiser, Colorado 5,815,649 A 9/1998 Utter et al' Springs’ CO (Us); Anuja Korgaonkars 5,822,777 A 10/1998 Les-hem et al. Colorado Springs CO Randy L 5,832,222 A 11/1998 DZladosZ et al. Roberson New £30m Richeg/ FL (US)_' 5,835,700 A 11/1998 Carbonneau et al. ’ ’ ’ 5,923,876 A 7/1999 Teague Robert G- Bean, Monument, CO (Us) 5,987,622 A 11/1999 L0 Verso et al. 5,996,089 A 11/1999 Mann et a1. (73) Assignee: Hewlett-Packard Development 6,033,639 A 3/2000 Schmidt et a1, Company, LP, Houston, TX (US) (Continued) ( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 OTHER PUBLICATIONS U-S-C- 154(1)) by 360 days- Smart Storage Inc., “SmartStor In?NetTM; Virtual Storage for Today’s E-economy,” Sep. 2000. (21) Appl. N0.: 11/081,061 _ (Contlnued) (22) Filed: Mar‘ 15’ 2005 Primary ExaminerAiary Portka (65) Prior Publication Data (57) ABSTRACT US 2005/0160243 A1 Jul. 21, 2005 A storage system permits Virtual storage of user data by Related US. Application Data implementing a logical disk mapping structure that provides (63) Continuation of application NO‘ 10/080 961 ?led on access to user data stored on physical storage media and Oct 22 2001 HOW Pat NO 6 915 392 Winch is a methods for generating point-in-time copies, or snapshots, con?nue’ltion_il’l_ an of 2'‘ li'cat’ion ’NO ’09/872 597 of logical disks. -
Cortex-A9 Single Core Microarchitecture
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 18-600 Foundations of Computer Systems Lecture 10: “The Memory Hierarchy” John P. Shen & Gregory Kesden October 2, 2017 ➢ Required Reading Assignment: • Chapter 6 of CS:APP (3rd edition) by Randy Bryant & Dave O’Hallaron ➢ Recommended Reference: • Sec. 1 & Sec. 3: Bruce Jacob, “The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It,” Synthesis Lectures on Computer Architecture 2009. 10/02/2017 (© John Shen) 18-600 Lecture #10 1 18-600 Foundations of Computer Systems Lecture 10: “The Memory Hierarchy” A. Memory Technologies B. Main Memory Implementation a. DRAM Organization b. DRAM Operation c. Memory Controller C. Disk Storage Technologies 10/02/2017 (© John Shen) 18-600 Lecture #10 2 From Lec #9 … Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Three Flow Paths of Superscalar Processors ➢ Wide Instruction Fetching ➢ Dynamic Branch Prediction I-cache Branch Instruction FETCH Flow Predictor Instruction ➢ Register Renaming Buffer ➢ Dynamic Scheduling DECODE ➢ Load Bypassing & Forwarding ➢ Speculative Memory Disamb. DISPATCH Integer Floating-point Media Memory Reservation Stations Memory Data EXECUTE Flow Reorder Buffer Register (ROB) Data COMMIT Flow Store D-cache Queue 10/02/2017 (© John Shen) 18-600 Lecture #10 3 From Lec #9 … Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Integrating Map Table with the ARF 9/27/2017 (©J.P. Shen) 18-600 Lecture #9 4 From Lec #9 … Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Reservation Station Implementation + info for executing instruction (opcode, ROB entry, RRF entry…) • Reservation Stations: distributed vs. -
The Influence of Caches on the Performance of Sorting
The Influence of Caches on the Performance of Sorting Anthony LaMarca* & Richard E. Ladner Department of Computer Science and Engineering University of Washington Seattle, WA 98195 lamarcaQparc.xerox.com [email protected] Abstract quicksort [12], and radix sort*. Heapsort, mergesort, We investigate the effect that caches have on the per- and quicksort are all comparison based sorting algo- formance of sorting algorithms both experimentally and rithms while radix sort is not. analytically. To address the performance problems that For each of the four sorting algorithms we choose an high cache miss penalties introduce we restructure heap- implementation variant with potential for good overall sort, mergesort and quicksort in order to improve their performance and then heavily optimize this variant us- cache locality. For all three algorithms the improvement ing traditional techniques to minimize the number of in cache performance leads to a reduction in total ex- instructions executed. These heavily optimized algo- ecution time. We also investigate the performance of rithms form the baseline for comparison. For each of radix sort. Despite the extremely low instruction count the comparison sort baseline algorithms we develop and incurred by this linear sorting algorithm, its relatively apply memory optimizations in order to improve cache poor cache performance results in worse overall perfor- performance and, hopefully, overall performance. For mance than the efficient comparison based sorting algo- radix sort we optimize cache performance by varying rithms. the radix. In the process we develop some simple an- alytic techniques which enable us to predict the mem- 1 Introduction. ory performance of these algorithms in terms of cache misses. -
17. Chapter 11
11 EXTERNALSORTING Good order is the foundation of all things. —Edmund Burke Sorting a collection of records on some (search) key is a very useful operation. The key can be a single attribute or an ordered list of attributes, of course. Sorting is required in a variety of situations, including the following important ones: Users may want answers in some order; for example, by increasing age (Section 5.2). Sorting records is the first step in bulk loading a tree index (Section 9.8.2). Sorting is useful for eliminating duplicate copies in a collection of records (Chapter 12). A widely used algorithm for performing a very important relational algebra oper- ation, called join, requires a sorting step (Section 12.5.2). Although main memory sizes are increasing, as usage of database systems increases, increasingly larger datasets are becoming common as well. When the data to be sorted is too large to fit into available main memory, we need to use an external sorting algorithm. Such algorithms seek to minimize the cost of disk accesses. We introduce the idea of external sorting by considering a very simple algorithm in Section 11.1; using repeated passes over the data, even very large datasets can be sorted with a small amount of memory. This algorithm is generalized to develop a realistic external sorting algorithm in Section 11.2. Three important refinements are discussed. The first, discussed in Section 11.2.1, enables us to reduce the number of passes. The next two refinements, covered in Section 11.3, require us to consider a more detailed model of I/O costs than the number of page I/Os. -
Memory Hierarchy Summary
Carnegie Mellon Carnegie Mellon Today DRAM as building block for main memory The Memory Hierarchy Locality of reference Caching in the memory hierarchy Storage technologies and trends 15‐213 / 18‐213: Introduction to Computer Systems 10th Lecture, Feb 14, 2013 Instructors: Seth Copen Goldstein, Anthony Rowe, Greg Kesden 1 2 Carnegie Mellon Carnegie Mellon Byte‐Oriented Memory Organization Simple Memory Addressing Modes Normal (R) Mem[Reg[R]] • • • . Register R specifies memory address . Aha! Pointer dereferencing in C Programs refer to data by address movl (%ecx),%eax . Conceptually, envision it as a very large array of bytes . In reality, it’s not, but can think of it that way . An address is like an index into that array Displacement D(R) Mem[Reg[R]+D] . and, a pointer variable stores an address . Register R specifies start of memory region . Constant displacement D specifies offset Note: system provides private address spaces to each “process” . Think of a process as a program being executed movl 8(%ebp),%edx . So, a program can clobber its own data, but not that of others nd th From 2 lecture 3 From 5 lecture 4 Carnegie Mellon Carnegie Mellon Traditional Bus Structure Connecting Memory Read Transaction (1) CPU and Memory CPU places address A on the memory bus. A bus is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices. Register file Load operation: movl A, %eax ALU %eax CPU chip Main memory Register file I/O bridge A 0 Bus interface ALU x A System bus Memory bus I/O Main Bus interface bridge memory 5 6 Carnegie Mellon Carnegie Mellon Memory Read Transaction (2) Memory Read Transaction (3) Main memory reads A from the memory bus, retrieves CPU read word xfrom the bus and copies it into register word x, and places it on the bus. -
Lecture 22: Mass Storage
Lecture 22: Mass Storage Fall 2019 Jason Tang Slides based upon Operating System Concept slides, http://codex.cs.yale.edu/avi/os-book/OS9/slide-dir/index.html Copyright Silberschatz, Galvin, and Gagne, 2013 "1 Topics • Mass Storage Systems! • Disk Scheduling! • Disk Management! • Boot Process "2 Mass Storage Systems • After startup, OS loads programs from secondary storage into main memory:! • ROM / EPROM / EEPROM / FPGA! • Magnetic hard disk! • Non-volatile random-access memory (NVRAM) ! • Tape drive ! • Or others: boot CD, Zip drive, punch card, … "3 EPROM • Erasable programmable read-only memory! • Manufacturer or OEM burns image into EPROM! • Use in older computing systems and in modern embedded systems "4 Magnetic Hard Disk (HDD) • Spindle motor spins a stack$ of platters coated with$ magnetic material! • Spins from 5400 to over$ 10000 RPMs! • Actuator motor moves a disk$ head over the platters, to$ sense polarity of the track$ underneath https://www.technobu%alo.com/2012/11/24/western-digital- "5 expands-high-performance-wd-black-hard-drive-line-to-4tb/ Magnetic Hard Disk (HDD) • Transfer rate: rate which data flow between drive and computer! • Positioning time (random-access time): time to move disk arm to desired cylinder (seek time) plus time for desired sector to rotate under disk head (rotational latency)! • Head crash: when disk head hits platter! • Attached to computer via a bus: SCSI, IDE, SATA, Fibre Channel, USB, Thunderbolt, others! • Host controller in computer uses bus to talk to disk controller "6 Magnetic Hard Disk -
External Sorting Why Sort? Sorting a File in RAM 2-Way Sort of N Pages
Why Sort? A classic problem in computer science! Data requested in sorted order – e.g., find students in increasing gpa order Sorting is the first step in bulk loading of B+ tree External Sorting index. Sorting is useful for eliminating duplicate copies in a collection of records (Why?) Chapter 13 Sort-merge join algorithm involves sorting. Problem: sort 100Gb of data with 1Gb of RAM. – why not virtual memory? Take a look at sortbenchmark.com Take a look at main memory sort algos at www.sorting-algorithms.com Database Management Systems, R. Ramakrishnan and J. Gehrke 1 Database Management Systems, R. Ramakrishnan and J. Gehrke 2 Sorting a file in RAM 2-Way Sort of N pages Requires Minimum of 3 Buffers Three steps: – Read the entire file from disk into RAM Pass 0: Read a page, sort it, write it. – Sort the records using a standard sorting procedure, such – only one buffer page is used as Shell sort, heap sort, bubble sort, … (100’s of algos) – How many I/O’s does it take? – Write the file back to disk Pass 1, 2, 3, …, etc.: How can we do the above when the data size is 100 – Minimum three buffer pages are needed! (Why?) or 1000 times that of available RAM size? – How many i/o’s are needed in each pass? (Why?) And keep I/O to a minimum! – How many passes are needed? (Why?) – Effective use of buffers INPUT 1 – Merge as a way of sorting – Overlap processing and I/O (e.g., heapsort) OUTPUT INPUT 2 Main memory buffers Disk Disk Database Management Systems, R. -
Tuning IBM System X Servers for Performance
Front cover Tuning IBM System x Servers for Performance Identify and eliminate performance bottlenecks in key subsystems Expert knowledge from inside the IBM performance labs Covers Windows, Linux, and VMware ESX David Watts Alexandre Chabrol Phillip Dundas Dustin Fredrickson Marius Kalmantas Mario Marroquin Rajeev Puri Jose Rodriguez Ruibal David Zheng ibm.com/redbooks International Technical Support Organization Tuning IBM System x Servers for Performance August 2009 SG24-5287-05 Note: Before using this information and the product it supports, read the information in “Notices” on page xvii. Sixth Edition (August 2009) This edition applies to IBM System x servers running Windows Server 2008, Windows Server 2003, Red Hat Enterprise Linux, SUSE Linux Enterprise Server, and VMware ESX. © Copyright International Business Machines Corporation 1998, 2000, 2002, 2004, 2007, 2009. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Contents Notices . xvii Trademarks . xviii Foreword . xxi Preface . xxiii The team who wrote this book . xxiv Become a published author . xxix Comments welcome. xxix Part 1. Introduction . 1 Chapter 1. Introduction to this book . 3 1.1 Operating an efficient server - four phases . 4 1.2 Performance tuning guidelines . 5 1.3 The System x Performance Lab . 5 1.4 IBM Center for Microsoft Technologies . 7 1.5 Linux Technology Center . 7 1.6 IBM Client Benchmark Centers . 8 1.7 Understanding the organization of this book . 10 Chapter 2. Understanding server types . 13 2.1 Server scalability . 14 2.2 Authentication services . 15 2.2.1 Windows Server 2008 Active Directory domain controllers . -
POWER7 and POWER7+ Optimization and Tuning Guide
Front cover POWER7 and POWER7+ Optimization and Tuning Guide Discover simple strategies to optimize your POWER7 environment Analyze and maximize performance with solid solutions Learn about the new POWER7+ processor Brian Hall Steve Munroe Mala Anand Francis P O’Connell Bill Buros Sergio Reyes Miso Cilimdzic Raul Silvera Hong Hua Randy Swanberg Judy Liu Brian Twichell John MacMillan Brian F Veale Sudhir Maddali Julian Wang K Madhusudanan Yaakov Yaari Bruce Mealey ibm.com/redbooks International Technical Support Organization POWER7 and POWER7+ Optimization and Tuning Guide November 2012 SG24-8079-00 Note: Before using this information and the product it supports, read the information in “Notices” on page vii. First Edition (November 2012) This edition pertains to Power Systems servers based on POWER7 and POWER7+ processor-based technology. Specific software levels and firmware levels used are noted throughout the text. © Copyright International Business Machines Corporation 2012. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . vii Trademarks . viii Preface . ix The team who wrote this book . ix Now you can become a published author, too! . xiii Comments welcome. xiv Stay connected to IBM Redbooks . xiv Chapter 1. Optimization and tuning on IBM POWER7 and IBM POWER7+ . 1 1.1 Introduction . 2 1.2 Outline of this guide . 2 1.3 Conventions that are used in this guide . 4 1.4 Background . 4 1.5 Optimizing performance on POWER7 . 5 1.5.1 Lightweight tuning and optimization guidelines. 6 1.5.2 Deployment guidelines . 13 1.5.3 Deep performance optimization guidelines. -
Fasttrak Tx2200 / Tx2300 Tx4200 / Tx4300 User Manual
FASTTRAK TX2200 / TX2300 TX4200 / TX4300 USER MANUAL Version 1.8 FastTrak TX2200/2300,TX4200/4300 User Manual Copyright © 2005 Promise Technology, Inc. All Rights Reserved. Copyright by Promise Technology, Inc. (Promise Technology). No part of this manual may be reproduced or transmitted in any form without the expressed, written permission of Promise Technology. Trademarks Promise, and the Promise logo are registered in U.S. Patent and Trademark Office. All other product names mentioned herein may be trademarks or registered trademarks of their respective companies. Important data protection information You should back up all data before installing any drive controller or storage peripheral. Promise Technology is not responsible for any loss of data resulting from the use, disuse or misuse of this or any other Promise Technology product. Notice Although Promise Technology has attempted to ensure the accuracy of the content of this manual, it is possible that this document may contain technical inaccuracies, typographical, or other errors. Promise Technology assumes no liability for any error in this publication, and for damages, whether direct, indirect, incidental, consequential or otherwise, that may result from such error, including, but not limited to loss of data or profits. Promise Technology provides this publication “as is” without warranty of any kind, either express or implied, including, but not limited to implied warranties of merchantability or fitness for a particular purpose. The published information in the manual is subject to change without notice. Promise Technology reserves the right to make changes in the product design, layout, and driver revisions without notification to its users. This version of the User Manual supersedes all previous versions. -
Introduction to Computer Systems 15-213/18-243, Spring 2009
Carnegie Mellon The Memory Hierarchy 15-213: Introduction to Computer Systems 11th Lecture, Feb. 16, 2016 Instructors: Franz Franchetti & Seth Copen Goldstein, Ralf Brown, and Brian Railing Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 1 Carnegie Mellon Today Storage technologies and trends Locality of reference Caching in the memory hierarchy Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 2 Carnegie Mellon Random-Access Memory (RAM) Key features . RAM is traditionally packaged as a chip. Basic storage unit is normally a cell (one bit per cell). Multiple RAM chips form a memory. RAM comes in two varieties: . SRAM (Static RAM) . DRAM (Dynamic RAM) Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 3 Carnegie Mellon SRAM vs DRAM Summary Trans. Access Needs Needs per bit time refresh? EDC? Cost Applications SRAM 4 or 6 1X No Maybe 100x Cache memories DRAM 1 10X Yes Yes 1X Main memories, frame buffers Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 4 Carnegie Mellon Nonvolatile Memories DRAM and SRAM are volatile memories . Lose information if powered off. Nonvolatile memories retain value even if powered off . Read-only memory (ROM): programmed during production . Programmable ROM (PROM): can be programmed once . Eraseable PROM (EPROM): can be bulk erased (UV, X-Ray) . Electrically eraseable PROM (EEPROM): electronic erase capability . Flash memory: EEPROMs. with partial (block-level) erase capability . Wears out after about 100,000 erasings Uses for Nonvolatile Memories . Firmware programs stored in a ROM (BIOS, controllers for disks, network cards, graphics accelerators, security subsystems,…) . -
Introduction to Computer Systems 15-213/18-243, Spring 2009
Carnegie Mellon The Memory Hierarchy 15-213: Introduction to Computer Systems 11th Lecture, June 11, 2019 Instructor: Brian Railing Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 1 Carnegie Mellon Today Storage technologies and trends Locality of reference Caching in the memory hierarchy Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 2 Carnegie Mellon Random-Access Memory (RAM) Key features . RAM is traditionally packaged as a chip. Basic storage unit is normally a cell (one bit per cell). Multiple RAM chips form a memory. RAM comes in two varieties: . SRAM (Static RAM) . DRAM (Dynamic RAM) Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 3 Carnegie Mellon SRAM vs DRAM Summary Trans. Access Needs Needs per bit time refresh? EDC? Cost Applications SRAM 4 or 6 1X No Maybe 100x Cache memories DRAM 1 10X Yes Yes 1X Main memories, frame buffers Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 4 Carnegie Mellon Enhanced DRAMs Basic DRAM cell has not changed since its invention in 1966. Commercialized by Intel in 1970. DRAM cores with better interface logic and faster I/O : . Synchronous DRAM (SDRAM) . Uses a conventional clock signal instead of asynchronous control . Allows reuse of the row addresses (e.g., RAS, CAS, CAS, CAS) . Double data-rate synchronous DRAM (DDR SDRAM) . Double edge clocking sends two bits per cycle per pin . Different types distinguished by size of small prefetch buffer: – DDR (2 bits), DDR2 (4 bits), DDR3 (8 bits) . By 2010, standard for most server and desktop systems .