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Intel Atom® Processor S1200 Product Family for Microserver Datasheet

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Intel Atom® Processor S1200 Product Family for Microserver Datasheet Intel® Atom™ Processor S1200 Product Family for Microserver Datasheet, Volume 2 of 2 December 2012 Document Number: 328195-001 INFORMATIONLegal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Copyright © 2012, Intel Corporation. All rights reserved. Intel® Atom™ Processor S1200 Product Family for Microserver Datasheet—Volume 2 of 2 December 2012 2 Document Number: 328195-001 Revision History Date Revision Description November 2012 1.0 Initial Release.. Intel® Atom™ Processor S1200 Product Family for Microserver December 2012 Datasheet—Volume 2 of 2 Document Number: 328195-001 3 Contents 1Introduction............................................................................................................17 1.1 Overview ..........................................................................................................17 1.2 Terminology......................................................................................................18 1.3 Related Documents ............................................................................................20 1.4 State of Data ....................................................................................................20 1.5 Register Attribute Definitions...............................................................................21 1.6 Register Bit Nomenclature...................................................................................22 2 Configuration Process and Registers........................................................................23 2.1 Device Mapping .................................................................................................23 2.2 Processor PCI Devices (CPUBUSNO(0)) .................................................................24 2.3 Configuration Register Rules ...............................................................................25 2.3.1 PCI Configuration Space Registers (CSRs) ..................................................25 2.3.2 CSR Access............................................................................................25 2.4 Configuration Mechanisms ..................................................................................26 2.4.1 Standard PCI Express Configuration Mechanism ..........................................26 3 Processor Integrated I/O (IIO) Registers................................................................27 3.1 Fabric Registers.................................................................................................27 3.2 PCI Express Root Port Registers (RP)....................................................................29 3.2.1 Introduction...........................................................................................32 3.2.2 PCI Standard Header Registers .................................................................33 3.2.3 Implementation Specific Registers.............................................................69 3.3 SMBus 2.0 Controller Registers............................................................................73 3.3.1 PCI Configuration Registers (SMBus—Bus 0:D19:F0-1) ................................74 3.4 SMBus Memory-Mapped Registers........................................................................94 3.5 Intel Legacy Block............................................................................................ 121 3.5.1 Introduction......................................................................................... 125 3.5.1.1 ILB Modules............................................................................ 126 3.5.1.2 Legacy ACPI ........................................................................... 127 3.5.1.3 ACPI GPE0 Block (GPE0BLK) ..................................................... 130 3.5.2 High Precision Event Timer – HPET.......................................................... 138 3.5.3 T0CV, T1CV, T2CV – Timer N Comparator Value........................................ 143 3.5.4 8254 Timer .......................................................................................... 144 3.5.4.1 Counter 0, System Timer ......................................................... 144 3.5.4.2 Counter 1, Refresh Request Signal............................................. 144 3.5.4.3 Counter 2, Speaker Tone.......................................................... 144 3.5.5 Timer I/O Registers............................................................................... 145 3.5.6 Real Time Clock – RTC........................................................................... 148 3.5.6.1 I/O Registers .......................................................................... 148 3.5.6.2 Indexed Registers ................................................................... 148 3.5.7 8259 Programmable Interrupt Controller.................................................. 153 3.5.7.1 I/O Registers .......................................................................... 154 3.5.8 IOxAPIC 1.1......................................................................................... 159 3.5.8.1 Index Registers....................................................................... 160 3.5.9 Interrupt Delivery - Interrupt Message Format.......................................... 162 3.5.10 LPC 1.1 ............................................................................................... 163 3.5.10.1 PCI Header............................................................................. 163 3.5.11 Root Complex Register Block Configuration .............................................. 169 3.5.12 SPI - Host Interface Registers ................................................................ 170 3.5.13 SMBus 1.0 ...........................................................................................177 3.5.13.1 I/O Registers .......................................................................... 177 3.5.13.2 Command Register (CMD) ........................................................ 180 Intel® Atom™ Processor S1200 Product Family for Microserver Datasheet—Volume 2 of 2 December 2012 4 Document Number: 328195-001 3.5.13.3 HD0 - Data 0 (HD0) ................................................................ 180 3.5.13.4 HD1 - Data 1 (HD1) ................................................................ 180 3.5.14 GPIO .................................................................................................. 181 3.5.14.1 Core Well GPIO I/O Registers ................................................... 181 3.5.14.2 Resume Well GPIO I/O Registers............................................... 184 3.5.15 Watch Dog Timer ................................................................................. 187 3.5.16 CPU Interface I/O Registers ................................................................... 192 3.5.16.1 Software SMI Control Port (SWSMICTL:
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