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AMD ENERGY STAR Server Energy Efficiency Technology AMD Opteron Energy Efficiency Technology ENERGY STAR Computer Servers Off-Season Meeting June 2014 David Reiner | Server Performance & Power Optimization Manager Donna Sadowy | Sr. Manager, Government Relations AMD 2013-2014 SERVER ROADMAP 2013 2014 AMD Opteron™ 6300 and 4300 Series “Warsaw” CPU 2P and 4P 4, 6, 8, 12 or 16 “Piledriver” CPU Cores 12 or 16 “Piledriver” CPU Cores Enterprise, 35W-140W Mainstream Platforms 32nm 32nm AMD Opteron™ 3300 Series “Berlin” CPU/APU 4 or 8 “Piledriver” CPU Cores 4 “Steamroller” CPU Cores 25W-65W TDP GCN Graphics Compute Units (APU) HSA Features (APU) 32nm 28nm 1P Web/Enterprise Services Clusters AMD Opteron™ X1150 CPU and X2150 APU “Seattle” CPU 4 “Jaguar” CPU Cores ARM “A57” CPU Cores GCN Graphics Compute Units (APU) 9W-22W 28nm SoC 28nm SoC AMD roadmaps are subject to change without notice or obligations to notify of changes. Placement of boxes intended to represent first year of production shipments. A History of Energy Efficiency 2010 2011 2012 2013 2014 2015 Finer grained power Integrated Dynamic power tracking and tracking, increased voltage management with DVFS “Kaveri” 10X voltage granularity regulation 10.0x Thermal aware Dynamic thermal 9.0x power tracking for short Platform aware dynamic management term boost thermal management 8.0x “Richland” 7.0x Video decode Video encode Audio Inter-frame “Trinity” acceleration acceleration acceleration power gating 6.0x Voltage-adaptive Per part 5.0x Finer grained Fine grained power frequency adaptive voltage planes gating “Llano” scaling voltage 4.0x “Danube” Intelligent boost and ACPI driven workload Dynamic CPU GPU 3.0x Performance aware energy ENERGY EFFICIENCY (LOG SCALE) (LOG EFFICIENCY ENERGY specific optimization power sharing “Tigris” optimization 2.0x “Puma” 1.0x Power efficient APU architecture OpenCL GPU compute moving to 2008 2009 2010 2011 2012 2013 2014 integrating GPU+CPU and accelerators full HSA enabled programming In market In product In development CHIP-LEVEL POWER DISTRIBUTIONS TDP 100% Power consumption 90% Core 3 VCE C A D ay (and hence performance) l & sp s 80% i is set by the cooling Y D GPU GPU GPU H Core 2 P capabilities of the power power power L2$ platform 70% 60% Core 1 S Power varies a lot by D CPU A GPU 50% P workload CPU power CPU Core 0 power power 40% We measure and Display Display Display 30% power power manage the power of power UVD H each component on the FCH FCH FCH MC 20% C chip to generate the best power power power F 10% performance/watt Other chip Other chip Other chip Memory PADS power power power 0% App 1 App 2 App 3 AMD Turbo Core Technology CPU CPU CPU CPU To manage temperature and Monitor Events send the power wherever Weights Weights Weights Weights it’s needed, we use power Weights Events monitors in all chip CAC CAC CAC CAC components Add-in Leakage Monitor Monitor Monitor Monitor “Kyoto” has power monitors Calculate Power APU in each CPU, the GPU, the (P = P + C V2f) P-states display interface, and the Leakage ac FCH Pboost Add in calculated GPU power AMD Turbo CORE P1 Manager The central controller uses Change P2 CAC Monitor FCH P-state based this information to optimize (Microcontroller) on TDP credits performance within thermal Pmin constraints GPU Display EVOLUTION OF AMD TURBO CORE TECHNOLOGY Boosting decision Year Processor based on Notes . Single boost Pstate used if half or more cores are inactive 2010 AMD Phenom™ II . Number of cores active . Coarse-grain power margin exploited . Unidirectional power transfer between thermal entities 1st-Generation 2011 . Calculated power . GPUCPU AMD A-Series APU . Exploit fine-grain power margin . Bidirectional power transfer between thermal entities 2nd-Generation . Calculated power . GPUCPU 2012 AMD A-Series APU . Calculated temperature . CPUGPU . Exploit temperature margin . Calculated power . Designed to more effectively exploit temperature margin 3rd-Generation . Calculated temperature by detecting favorable thermal conditions in real time 2013 AMD A-Series APU . Measured/Sensor temperature ("Richland“) . Efficiency of power usage by individual . Intelligent Boost entities (CPU, GPU, etc.) CHIP-LEVEL POWER DISTRIBUTIONS: GPU-CENTRIC Lower-power cores serve as a heat sink TDP for the active GPU 100% 90% Core 3 80% GPU power Core 2 70% 60% Core 1 GPU 50% CPU power Core 0 40% Display 30% power 20% FCH power 10% Other chip power 0% App 1 CHIP-LEVEL POWER DISTRIBUTIONS: CPU-CENTRIC Lower-power GPU serves as a TDP heat sink for the active CPUs 100% 90% Core 3 80% GPU power Core 2 70% 60% Core 1 GPU 50% CPU power Core 0 40% 30% Display power 20% FCH power 10% Other chip power 0% App 2 Avoiding power waste with Intelligent Boost control • Intelligent Boost is designed to avoid power waste that results from boosting applications that Different benefit very little from higher applications frequency gain) BOOST • Enables long battery life and freq THESE cool operation while gain for % for gain maintaining great performance perf Frequency Frequency Sensitivity • Power management micro- % (i.e. DON’T controller tracks application BOOST behavior real-time to determine THESE frequency sensitivity • Boost behavior is adjusted Performance metrics tracked by power manager accordingly FABRICS REDUCE THE POWER CONSUMPTION OF EVERY SERVER ~70% of energy consumption in servers SHARE from components • Sharing instead of replicating components beyond CPU eliminates pieces from motherboard Eliminate unnecessary • Reduces power and space components and POWER OPTIMIZE SeaMicro functions TIO • Turning off unneeded IOVT logic blocks saves Remove tiers of power networking equipment and thousands of cables LINK EFFICENT UNITS Freedom Supercompute • A low cost, on board Fabric interconnect allows removal of top of rack switching and increases bandwidth Slide Sources - ““Richland” Client APU” Presentation by Praveen Dongara, Lloyd Bircher, John Darrilek - Hot Chips 25, August 2013 - “AMD Product and Tech Roadmaps 5.5.14” - “Energy Efficiency” by Sam Naffziger, June 16, 2014 - “AMD “Kabini” APU SOC” by Dan Bouvier, Ben Bates, Walter Fry, Sreekanth Godey – Hot Chips 25, August 2013 - “Energy Efficiency Messaging” May 9, 2014 - “AMD Advanced Power Management” by Sam Naffziger, April 2014 24 DISCLAIMER & ATTRIBUTION The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILLAMD BE LIABLE TO ANY PERSON FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLYADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ATTRIBUTION © 2014 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Names are for informational purposes only and may be trademarks of their respective owners. 25.
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