LT4320/LT4320-1 Ideal Bridge Controller Features Description n Maximizes Power Efficiency The LT ®4320/LT4320-1 are ideal diode bridge controllers n Eliminates Thermal Design Problems that drive four N-channel MOSFETs, supporting n DC to 600Hz rectification from DC to 600Hz typical. By maximizing n 9V to 72V Operating Voltage Range available voltage and reducing power dissipation (see n IQ = 1.5mA (Typical) thermograph comparison below), the ideal diode bridge n Maximizes Available Voltage simplifies power supply design and reduces power supply n Available in 8-Lead (3mm × 3mm) DFN, 12-Lead cost, especially in low voltage applications. MSOP and 8-Lead PDIP Packages An ideal diode bridge also eliminates thermal design Applications problems, costly heat sinks, and greatly reduces PC board area. The LT4320’s internal charge pump supports an all- n Security Cameras NMOS design, which eliminates larger and more costly n Terrestrial or Airborne Power Distribution Systems PMOS switches. If the power source fails or is shorted, a n Power-over-Ethernet Powered Device with a fast turn-off minimizes reverse current transients. Secondary Input The LT4320 is designed for DC to 60Hz typical voltage n Polarity-Agnostic Power Input rectification, while the LT4320-1 is designed for DC to n Diode Bridge Replacement 600Hz typical voltage rectification. Higher frequencies of L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear operation are possible depending on MOSFET size and Technology Corporation. All other trademarks are the property of their respective owners. Patent pending. operating load current.

Typical Application Thermograph of Passive Diode Bridge

+

Temperature Rise

OUTP DIODE TG1 TG2 MOSFET SBM CURRENT 2.5mΩ 1040 LT4320 4320 TA01b OUTPUT SBM1040 (×4) ~ IN1 IN2 9V TO 72V 2A 0.6°C 15°C Thermograph of LT4320 4A 3.5°C 32°C BG2 BG1 Driving Four MOSFETs 6A 6.7°C 49°C OUTN 8A 11°C 66°C INPUT DC TO 600Hz (TYP) 10A 16°C 84°C DC Input, On Same PCB – ~ 4320 TA01a

4320 TA01c LT4320+2.5mΩ FET (×4) CONDITIONS: 24V ACIN, 9.75A DC LOAD ON SAME PCB 4320fb

For more information www.linear.com/LT4320 1 LT4320/LT4320-1

Absolute Maximum Ratings (Notes 1, 2) Supply Operating Junction Temperature Range IN1, IN2...... –3V to 80V LT4320I...... –40°C to 85°C OUTP...... –0.3V to 80V LT4320H...... –40°C to 125°C Output Voltages (Note 3) LT4320MP...... –55°C to 125°C BG1, BG2, TG1, TG2...... –0.3V to 80V Storage Temperature Range...... –65°C to 150°C TG1-IN1, TG2-IN2...... –0.3V to 12V Lead Temperature (Soldering, 10 sec) MSE, PDIP Packages...... 300°C

Pin Configuration

TOP VIEW TOP VIEW TOP VIEW IN2 1 12 IN1 IN2 1 8 IN1 TG2 2 11 TG1 IN2 1 8 IN1 TG2 2 7 TG1 NC 3 10 NC 9 13 TG2 2 7 TG1 BG2 3 6 OUTP NC 4 9 OUTP BG2 5 8 NC BG2 3 OUTP BG1 4 5 OUTN 6 BG1 6 7 OUTN BG1 4 5 OUTN MSE PACKAGE DD PACKAGE N8 PACKAGE 12-LEAD PLASTIC MSOP 8-LEAD (3mm × 3mm) PLASTIC DFN 8-LEAD PLASTIC DIP TJMAX = 150°C, θJC = 10°C/W TJMAX = 150°C, θJC = 5.5°C/W EXPOSED PAD (PIN 13) MUST BE TJMAX = 150°C, θJC = 45°C/W EXPOSED PAD (PIN 9) MUST BE CONNECTED TO OUTN (PIN 7) CONNECTED TO OUTN (PIN 5)

Order Information

OPERATING JUNCTION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT4320IDD#PBF LT4320IDD#TRPBF LGCV 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4320HDD#PBF LT4320HDD#TRPBF LGCV 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4320IDD-1#PBF LT4320IDD-1#TRPBF LGCW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4320HDD-1#PBF LT4320HDD-1#TRPBF LGCW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4320IMSE#PBF LT4320IMSE#TRPBF 4320 12-Lead Plastic MSOP –40°C to 85°C LT4320HMSE#PBF LT4320HMSE#TRPBF 4320 12-Lead Plastic MSOP –40°C to 125°C LT4320MPMSE#PBF LT4320MPMSE#TRPBF 4320 12-Lead Plastic MSOP –55°C to 125°C LT4320IMSE-1#PBF LT4320IMSE-1#TRPBF 43201 12-Lead Plastic MSOP –40°C to 85°C LT4320HMSE-1#PBF LT4320HMSE-1#TRPBF 43201 12-Lead Plastic MSOP –40°C to 125°C LT4320MPMSE-1#PBF LT4320MPMSE-1#TRPBF 43201 12-Lead Plastic MSOP –55°C to 125°C LT4320IN8#PBF NA LT4320N8 8-Lead PDIP –40°C to 85°C LT4320HN8#PBF NA LT4320N8 8-Lead PDIP –40°C to 125°C LT4320IN8-1#PBF NA LT4320N8-1 8-Lead PDIP –40°C to 85°C LT4320HN8-1#PBF NA LT4320N8-1 8-Lead PDIP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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2 For more information www.linear.com/LT4320 LT4320/LT4320-1

E lectrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS OUTP Voltage Range l 9 72 V OUTP Undervoltage Lockout (UVLO) Threshold INn = OUTP, Other IN = 0V l 6.2 6.6 7.0 V l VINT INn Turn-On/Off Threshold OUTP = 9V, Other IN = 0V 1.3 3.7 V l IOUTP OUTP Pin Current INn = OUTP+ ∆VSD(MAX) + 5mV, Other IN = 0V 1.0 1.5 mA

IINn INn Pin Current INn = OUTP+ ∆VSD(MAX) + 5mV, Other IN = 0V at 9V l 44 63 µA at 72V l 0.3 0.4 mA

∆VSD Topside Source-Drain Regulation Voltage (INn – OUTP) LT4320 l 8 20 35 mV LT4320-1 l 26 40 55 mV l ∆VTGATE Top Gate Drive (TGn – INn) INn = OUTP+ ∆VSD(MAX) + 5mV, 10μA Out of 6.6 10.8 V TGn, Other IN = 0V l VBGATE Bottom Gate Drive (BGn) INn = OUTP, 10μA Out of BGn, Other IN = 0V 7.0 12 V l ITGUn Top Gate Pull-Up Current TGn – INn = 0V, INn = OUTP + 0.1V 425 µA TGn – INn = 5V, INn = OUTP + 0.1V l 120 µA Current Flows Out of TGn, Other IN = 0V l ITGSn Top Gate Pull-Down Current to INn TGn – INn = 5V, INn = OUTP – 0.25V 1.25 mA Current Flows Into TGn, Other IN = 0V l ITGGn Top Gate Pull-Down Current to OUTN INn = 0V, Other IN = OUTP = 9.0V, TGn = 5V 6.0 mA Current Flows Into TGn l IBGUn Bottom Gate Pull-Up Current BGn = 5V; INn = OUTP = 9.0V, Other IN = 0V 1.9 mA Current Flows Out of BGn l IBGDn Bottom Gate Pull-Down Current BGn = 5V; INn = 0V, Other IN = OUTP = 9.0V 12.5 mA Current Flows Into BGn

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 2: All voltages are referenced to OUTN = 0V unless otherwise specified. may cause permanent damage to the device. Unless otherwise specified, Note 3: Externally forced voltage absolute maximums. The LT4320 may exposure to any Absolute Maximum Rating condition for extended periods exceed these limits during normal operation. may affect device reliability and lifetime.

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For more information www.linear.com/LT4320 3 LT4320/LT4320-1 Typical Performance Characteristics

IINn and IOUTP vs OUTP IOUTP vs OUTP ∆VTGATE vs OUTP 1200 1200 11 OTHER IN = 0V IN1 AND IN2 FLOATING OTHER IN = 0V

1000 OUTP 1000 10

800 800 9 (V)

600 (µA) 600 TGATE OUTP I

∆V 8 CURRENT (µA) 400 400

INn 7 200 200 ∆VSD = 100mV ∆VSD = 40mV 0 0 6 0 20 40 60 80 0 20 40 60 80 9 13 17 21 25 INn = OUTP (V) OUTP (V) OUTP (V)

4320 G01 4320 G02 4320 G03

VBGATE vs OUTP TGn Pull-Up Strength TGn Pull-Down Strength to INn 12 1000 5 INn = OUTP + 100mV INn = OUTP – 250mV 900 OTHER IN = 0V OTHER IN = 0V 11 800 4 700 10 600 3 (V) (mA) 9 (µA) 500 TGn BGATE I TGSn V 400 I 2 8 300 200 7 OUTP = 9V 1 100 OUTP = 12V OUTP = 9V OTHER IN = 0V OUTP = 72V OUTP = 72V 6 0 0 9 13 17 21 25 0 2 4 6 8 10 12 0 2 4 6 8 10 12 OUTP (V) ∆VTGATE (V) ∆VTGATE (V)

4320 G04 4320 G05 4320 G06

TGn Pull-Down Strength to OUTN BGn Pull-Up Strength BGn Pull-Down Strength 60 5 35 INn = 0V OTHER IN = 0V OTHER IN = OUTP 50 30 4 25 40 3 20 (mA) (mA) (mA) 30 TGGn BGDn

BGUn 15 I I I 2 20 10 1 OUTP = 9V VINn = 9V 10 5 OUTP = 12V VINn = 12V OUTP = 72V VINn = 72V 0 0 0 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 TGn (V) VBGATE (V) VBGATE (V)

4320 G07 4320 G08 4320 G09

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4 For more information www.linear.com/LT4320 LT4320/LT4320-1

Pin Functions (DFN, PDIP/MSOP) IN2 (Pin 1/Pin 1): Bridge Input. IN2 connects to OUTP (Pin 6/Pin 9): OUTP is the rectified positive output the external NMOS transistors MTG2 source, MBG1 drain voltage that powers the LT4320 and connects to the drains and the power input. of MTG1 and MTG2. TG2 (Pin 2/Pin 2): Topside Gate Driver Output. TG2 pin TG1 (Pin 7/Pin 11): Topside Gate Driver Output. TG1 pin drives MTG2 gate. drives MTG1 gate. BG2 (Pin 3/Pin 5): Bottom-Side Gate Driver Output. BG2 IN1 (Pin 8/Pin 12): Bridge Rectifier Input. IN1 connects pin drives MBG2 gate. to the external NMOS transistors MTG1 source, MBG2 BG1 (Pin 4/Pin 6): Bottom-Side Gate Driver Output. BG1 drain, and the power input. pin drives MBG1 gate. NC (Pins 3, 4, 8, 10, MSOP Only): No Connections. Not OUTN (Pin 5/Pin 7): OUTN is the rectified negative output internally connected. voltage, and connects to the sources of MBG1 and MBG2. Exposed Pad (Pin 9/Pin 13): Exposed Pad, DFN and MSOP. Must be connected to OUTN.

Block Diagram

MTG1 ~ + MTG2

TG2 TG1 LT4320

IN1 OUTP

CONTROL IN2

OUTN

BG2 BG1

MBG2 ~ – MBG1 LT4320 BD

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For more information www.linear.com/LT4320 5 LT4320/LT4320-1 Operation Electronic systems that receive power from an AC power bridge also eliminates thermal design problems, costly source or a DC polarity-agnostic power source often em- heat sinks, and greatly reduces PC board area. ploy a 4-diode rectifier. The traditional diode bridge comes The LT4320 is designed for DC to 60Hz typical voltage with an efficiency loss due to the voltage drop generated rectification, while the LT4320-1 is designed for DC to across two conducting . The voltage drop reduces 600Hz typical voltage rectification. Higher frequencies of the available supply voltage and dissipates significant operation are possible depending on MOSFET size and power especially in low voltage applications. operating load current. By maximizing available voltage and reducing power dis- Figure 2 presents sample waveforms illustrating the gate sipation, the ideal diode bridge simplifies power supply pins in an AC voltage rectification design. design and reduces power supply cost. An ideal diode

MTG1 ~ + MTG2

INPUT TO LOAD TG2 TG1 IN1 OUTP

LT4320 CLOAD IN2 OUTN BG2 BG1

MBG2 ~ – MBG1 4320 F01 Figure 1. LT4320 with Four N-Channel MOSFETS, Illustrating Current Flow When IN1 Is Positive

40V

30V

20V

10V VTG1 VIN1 VTG2 VOUTP VBG1 VIN2 VBG2 0V 4320 F02 Figure 2. 24V AC Sample Waveform

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6 For more information www.linear.com/LT4320 LT4320/LT4320-1 Applications Information MOSFET Selection the maximum operating frequency, creates unintended efficiency losses, adversely increases turn-on/turn-off A good starting point is to reduce the voltage drop of the times, and increases the total solution cost. The LT4320 ideal bridge to 30mV per MOSFET with the LT4320 (50mV gate pull-up/pull-down current strengths specified in the per MOSFET with the LT4320-1). Given the average output Electrical Characteristics section, and the MOSFET total load current, IAVG, select RDS(ON) to be: gate charge (Qg), determine the MOSFET turn-on/off times 30mV and the maximum operating frequency in an AC applica- RDS(ON) = for a DC power input IAVG tion. Choosing the lowest gate capacitance while meeting or RDS(ON) speeds up the response time for full enhancement, regulation, turn-off and input shorting events. 30mV R = for an AC power input V must be a minimum of 2V or higher. A gate thresh- DS(ON) 3 •I GS(th) AVG old voltage lower than 2V is not recommended since too In the AC power input calculation, 3 • IAVG assumes the much time is needed to discharge the gate below the duration of current conduction occupies 1/3 of the AC threshold and halt current conduction during a hot plug period. or input short event. Select the maximum allowable drain-source voltage, V , DSS C Selection to be higher than the maximum input voltage. LOAD A 1μF ceramic and a 10μF minimum electrolytic Design Example must be placed across the OUTP and OUTN pins with the 1µF ceramic placed as close to the LT4320 as possible. For a 24W, 12V DC/24V AC application, IAVG = 2A for 12V DC. To cover the 12V DC case: Downstream power needs and voltage tolerance determine how much additional capacitance between 30mV OUTP and OUTN is required. CLOAD in the hundreds to RDS(ON) = = 15mΩ 2A thousands of microfarads is common. such that: For the 24V AC operation, IAVG = 1A. To cover the 24V A good starting point is selecting CLOAD AC case: CLOAD ≥ IAVG/(VRIPPLE • 2 • Freq) 30mV where IAVG is the average output load current, VRIPPLE is RDS(ON) = = 10mΩ 3 • 1A the maximum tolerable output ripple voltage, and Freq is the frequency of the input AC source. For example, in This provides a starting range of RDS(ON) values to choose a 60Hz, 24VAC application where the load current is 1A from. and the tolerable ripple is 15V, choose CLOAD ≥ 1A/(15V Ensure the MOSFET can handle a continuous current of • 2 • 60Hz) = 556µF. 3 • IAVG to cover the expected peak currents during AC rec- CLOAD must also be selected so that the rectified output tification. That is, select ID ≥ 3A. Since a 24V AC waveform voltage, OUTP-OUTN, must be within the LT4320/LT4320-1 can reach 34V peak, select a MOSFET with VDSS >>34V. specified OUTP voltage range. A good choice of VDSS is 60V in a 24V AC application. Transient Voltage Suppressor Other Considerations in MOSFET Selection For applications that may encounter brief overvoltage Practical MOSFET considerations for the LT4320-based events higher than the LT4320 absolute maximum rating, ideal bridge application include selecting the lowest avail- install a unidirectional transient voltage suppressor (TVS) able total gate charge (Qg) for the desired RDS(ON). Avoid between the OUTP and OUTN pins as close as possible oversizing the MOSFET, since an oversized MOSFET limits to the LT4320. 4320fb

For more information www.linear.com/LT4320 7 LT4320/LT4320-1 Typical Applications

B360B 4 COMPACT FETs*

CONDITION: 13VDCIN, 3A LOAD ON SAME PCB *19mΩ, 60V EACH FET Figure 3. Thermograph: B360B vs LT4320 +4 Compact FETs

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8 For more information www.linear.com/LT4320 LT4320/LT4320-1 Typical Applications

Figure 4. Demonstration Circuit 1902A Used in Figure 3 Thermograph

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For more information www.linear.com/LT4320 9 LT4320/LT4320-1 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698 Rev C)

0.70 ±0.05

3.5 ±0.05 1.65 ±0.05 2.10 ±0.05 (2 SIDES)

PACKAGE OUTLINE

0.25 ±0.05 0.50 BSC 2.38 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.125 0.40 ±0.10 TYP 5 8

3.00 ±0.10 1.65 ±0.10 (4 SIDES) (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 0509 REV C 4 1 0.200 REF 0.75 ±0.05 0.25 ±0.05 0.50 BSC 2.38 ±0.10 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD

NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE

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10 For more information www.linear.com/LT4320 LT4320/LT4320-1 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSE Package 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev G)

BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 2.845 0.102 ± (.112 ±.004) (.112 ±.004) 0.889 ±0.127 (.035 ±.005) 1 6 0.35 REF

5.10 1.651 ±0.102 1.651 ±0.102 3.20 – 3.45 (.201) (.065 ±.004) 0.12 REF MIN (.065 ±.004) (.126 – .136) DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. 12 7 FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.42 ±0.038 0.65 4.039 ±0.102 (.0256) (.0165 ±.0015) (.159 ±.004) TYP BSC (NOTE 3) 0.406 0.076 RECOMMENDED SOLDER PAD LAYOUT ± 12 11 10 9 8 7 (.016 ±.003) REF DETAIL “A” 0.254 (.010) 3.00 ±0.102 0° – 6° TYP 4.90 ±0.152 (.118 ±.004) (.193 .006) GAUGE PLANE ± (NOTE 4)

0.53 ±0.152 (.021 ±.006) 1 2 3 4 5 6 DETAIL “A” 1.10 0.86 0.18 (.043) (.034) (.007) MAX REF

SEATING PLANE 0.22 – 0.38 0.1016 ±0.0508 (.009 – .015) (.004 ±.002) TYP 0.650 NOTE: (.0256) MSOP (MSE12) 0213 REV G 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

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For more information www.linear.com/LT4320 11 LT4320/LT4320-1 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

N Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510 Rev I)

.400* (10.160) MAX

8 7 6 5

.255 ±.015* (6.477 ±0.381)

1 2 3 4

.300 – .325 .045 – .065 .130 ±.005 (7.620 – 8.255) (1.143 – 1.651) (3.302 ±0.127)

.065 (1.651) .008 – .015 TYP (0.203 – 0.381) .120 (3.048) .020 +.035 MIN (0.508) .325 –.015 .100 .018 ±.003 MIN +0.889 8.255 (2.54) (0.457 ±0.076) N8 REV I 0711 –0.381 ( ) BSC NOTE: INCHES 1. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

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12 For more information www.linear.com/LT4320 LT4320/LT4320-1 Revision History

REV DATE DESCRIPTION PAGE NUMBER A 11/13 Clarified that input frequency ranges use typical numbers (60Hz, 600Hz) 1, 6 Added PDIP package 2, 12 Reduced MOSFET drop to 30mV from 70mV in “MOSFET Selection” and “Design Example” sections 7 Provided additional guidance in “Other Considerations in MOSFET Selection” section 7 Updated MSE package drawing 10 B 2/14 Added H- and MP-grade information 2

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnectionFor moreof its circuits information as described www.linear.com/LT4320 herein will not infringe on existing patent rights. 13 LT4320/LT4320-1 Typical Application

MTG1 ~ + MTG2 DIODE LT4320 IDEAL BRIDGE BRIDGE MTG1,MTG2 OPERATING LOAD C1 POWER POWER TG2 TG1 MBG1, MBG2 VOLTAGE CURRENT (MIN) LOSS LOSS IN1 OUTP + 55V DC 3.5A 10µF 0.22W 4.2W INPUT LT4320 1µF C1 TO LOAD BSZ110N06NS3 IN2 OUTN 24V AC 1.5A 560µF 0.13W 1.9W BG2 BG1 55V DC 30A 10µF 4.5W 36W BSC031N06NS3 24V AC 10A 3.3mF 1.6W 12W PSMN040-100MSE 72V DC 2A 10µF 0.24W 2.4W MBG2 ~ – MBG1 4320 TA02

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4320fb Linear Technology Corporation LT 0214 REV B • PRINTED IN USA 14 1630 McCarthy Blvd., Milpitas, CA 95035-7417For more information www.linear.com/LT4320 ● ● (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LT4320  LINEAR TECHNOLOGY CORPORATION 2013