Microfabricated Thermionic Electron Emitters

K. Blair Huffman

Stanford University

To fulfill the undergraduate Honor’s Program requirements for the

Department of Electrical Engineering

June 2014

I certify that I have read this Honor’s thesis and that, in my opinion, it is fully adequate in scope and quality to fulfill the requirements for the undergraduate Honor’s Program for the Department of Electrical Engineering

______Roger T. Howe, Principal Adviser

______R. Fabian Pease, Second Reader

Acknowledgements

I would like to first thank Professor Roger Howe for his constant advice and assistance on this project and on my academic aspirations. None of this would have been possible without his support throughout my undergraduate career, and I cannot thank him enough.

Prof. Howe’s energy group has been a tremendous resource for me. I would especially like to thank Dr. Justin Snapp for helping me with the fabrication.

Next, I would like to thank Professor Fabian Pease and Dr. J Provine for introducing me to nanofabrication during my freshman year. They both helped me find my passion and have helped me pursue it during my undergraduate career.

I would also like to thank the Department of Electrical Engineering for providing me with support on my project over the summer in 2013. I would like to thank the STEM fellowship, the American Indian Science and Engineering Society, Google, and Intel for providing funding.

The School of Engineering’s Engineering Diversity Programs Office has given me tremendous support throughout my career. Dr. Noé Lozano and his staff introduced me to engineering and have been huge supporters of my academic pursuits. They have provided me with a community of scholars that have been crucial for my success at

Stanford. They always had confidence in me even when I did not have confidence in my own abilities.

Lastly, I would like to thank my parents, Bill and Susan Huffman for their continuous support. They are my biggest fans and support me in all that I do, even if they do not know what thermionic energy converters do. They have provided me with a fantastic education, love, and support, to help me reach my future goals.

Abstract

Thermionic energy converters (TECs) convert very high temperature to electricity without any moving parts. Specifically, the heat gives rise to electron emission from one electrode (‘emitter’) to a nearby electrode (‘collector’) and the resulting current can drive a load. To produce a useful current, both the temperature and the work functions of the emitter and collector must be sustainably controlled. Previous work established that the gap between the two electrodes should be in the range of 1 - 10 µm to minimize space charge at larger gaps and excessive heat transfer at smaller gaps. The microfabricated thin-film emitter is thermally isolated from the substrate by a poly-SiC suspension. This thesis describes the redesign of the suspended emitter and its fabrication process. The suspended plate is optimized for vertical emission by eliminating the recessed emitter surface in the previous design. Furthermore, the process includes the etching of apertures in the silicon substrate, so that underside of the suspended plate can be heated by laser illumination. The thermal resistance of the emitter suspension beams is increased by

50% in the new designs. The five-mask fabrication process is in progress in the Stanford

Nanofabrication Facility.

Table of Contents

1. Introduction ...... 1.1 Motivation...... 1 1.2 History of Thermionic Energy Converters ...... 2 1.3 Physics of Thermionic Energy Converters ...... 5 1.4 Thesis Overview ...... 8

2. Thermionic Emitter Redesign ...... 2.1 Motivation...... 9 2.2 Emitter design process...... 11 2.3 Micro Thermionic Energy Converter Test Assembly Design ...... 17 2.4 Chapter Summary ...... 20

3. Fabrication ...... 3.1 Introduction...... 22 3.2 Layout design ...... 23 3.3 Fabrication Methodology ...... 27 3.4 Chapter Summary ...... 30

4. Next Steps ...... 4.1 Introduction...... 32 4.2 Device Testing ...... 32 4.3 Chapter Summary ...... 36

5. Conclusion ...... 5.1 Summary...... 37 5.2 Future Work ...... 38

Chapter 1

Introduction

1.1 Motivation

Many energy conversion methods, from internal combustion or Stirling engines to steam turbines, are based on taking heat and turning it into electricity. While our current methods use mechanical moving parts as an intermediary step in conversion, thermionic energy converters (TECs) perform the same task without any moving mechanical parts.

TECs have the potential to have a competitive efficiency compared to the Stirling engine

Figure 1: Illustration of the functionality of a thermionic energy converter. Its functionality is based on the concept of electrons evaporating from the emitter and being collected by the collector, creating a current. [1]

1 Figure 2: The maximum energy conversion efficiency versus the emitter temperature for collector work functions of 0.5, 1.0, and 1.5 eV. The emitter work function, ϕ E, is assumed to be TE[K]/750eV. The inset shows the exergy efficiency (also known as the second-law efficiency), i.e., the energy conversion efficiency divided by the Carnot efficiency, 1- TC/TE, for the corresponding emitter and collector temperatures [12].

[2]. They can be used as a topping stage in tandem energy converters because the TEC’s rejected heat can be hot enough to power conventional heat engines [3]. Previous work on TECs has primarily focused on space applications [4]. With the use of wafer-scale processes, fabrication cost will drop and terrestrial applications become feasible.

Terrestrial applications include solar concentrators, nuclear power plants, and photon enhanced thermionic energy conversion in solar applications [2].

1.2 History of Thermionic Energy Converters

When a material is heated, electrons can escape from the surface of the material by overcoming the material’s work function. Thomas Edison was one of the first to discover this phenomenon, known as thermionic emission, in 1880 when he was working on filaments for his light bulbs. His filament burned for a couple of hours and coated the

2 interior of the bulb with carbon. More importantly, Edison noticed that the bulb carried a charge after the interior of the bulb had been coated [5]. He concluded that charge carriers had been emitted from the heated filament.

In 1915, W. Schlichter first conceptualized thermionic energy conversion [6]; and in 1941, two Soviet researchers, M. Y. Gurtovoy and G. I. Kovalenko, were the first to demonstrate a working thermionic energy converter [7]. The former Soviet Union decided to investigate thermionics, and in the 1960s, launched a full-scale program to develop and test in-core thermionic reactors [4]. The program cumulated with an operational thermionic converter on the TOPAZ-II space reactor, Figure 3 [8]. These converters had an operational efficiency of 6% with emitter temperatures of 1700 K,

Figure 3: TOPAZ-II thermionic space reactor at the Kirkland Air Force Base [1] collector temperatures of 600K, and an emitter-collector gap on the order of 100 microns

[8]. The Soviet Union and the United States had a joint effort on thermionic research, the

TOPAZ International Program, which ended in 1996 [4]. While thermionic energy converters are a potential candidate for high performance power applications, their high cost and technical challenges have discouraged major investment [4].

3 It was not until the past 15 years that the possibility of micro-miniature thermionic energy converters have been explored. Potential benefits of a microscale thermionic energy converter (µTEC) include: low maintenance, long life, compactness, and the lack of an ionizing plasma to neutralize the space charge region [9]. Additionally, by utilizing integrated circuit manufacturing and MEMS technology, µTECs have the potential of being relatively inexpensive to produce. In 2000, Sandia National Labs estimated that an emitter-collector gap on the 1 µm scale would eliminate space charge and have conversion efficiency between 15-25% [8]. They identified lower work functions along with better thermal isolation as critical in obtaining high efficiency. In a patent on microminiature thermionic energy converters, filled 1998 and issued in 2003, they propose using silicon oxide as a thermally isolating spacer between the emitter and anode [9]. However, a US government study in 2001 concluded “it would be extremely difficult to maintain, for any reasonable period of time, a temperature difference of nearly

1000 K between two surfaces held apart by a miniaturized spacer that is a few microns thick” [4].

In recent years, researchers in the NEMS group at Stanford University led by

Prof. Roger Howe have been working on µTEC technology. In 2012, the group’s initial prototype successfully proved it is possible to achieve a temperature difference of over

1000K with a 1.7 micron gap [10]. More recently, in 2014, the group reported a relatively low work function thermionic emitter that is thermally robust and could be used in a converter with efficiency of about 0.5% [1].

4 1.3 Physics of Thermionic Energy Conversion

Thermionic energy conversion is based on the principle of thermionic emission.

Thermionic current density, defined by density of the emission of electrons from the surface of a material, is governed by the Richardson-Dushman law:

2 ϕ (1) J0 = AT exp(− ) kBT where T is the temperature of the material, kB is Boltzmann’s constant, ϕ is the work function of the material, and A is a material specific Richardson-Dushman constant € 6 -2 -2 € where A = λA0, A0 = 1.20 x 10 A m K and λ is the material specific correlation coefficient, with an ideal value of 1. However, conventional TECs are limited in obtaining this ideal current density for a particular work function because of space charge

Figure 4: Energy diagram of a thermionic converter, where EF,E and EF,C are the Fermi levels of the emitter and collector, respectively. Evac is the vacuum level for each respective electrode, and ϕ E and ϕ C are the work functions of the emitter and collector [1].

5 in the interelectrode gap, the gap between the emitter and collector, and an opposing thermionic current density from the collector.

When an electron is emitted from the emitter, the electron must travel in the interelectrode gap toward the collector. When the electron is within this gap, it creates a negative voltage barrier, which repels other electrons entering this region. As the density of electrons within this region increase, so does the negative voltage barrier, which causes emitted electrons to return to the surface of the emitter; therefore, the space charge severely limits the output current of the thermionic energy converter.

In order to combat this inefficiency, cesium plasma in the interelectrode gap is used to neutralize the negative space charge effect [4]. Incorporating cesium plasma adds complexity to the thermionic converter and also limits the total output performance of the device [11]. An alternative to cesium plasma is to decrease the interelectrode spacing between the emitter and collector. By making the interelectrode gap less than the mean free path of the emitted electrons (less than 5µm), space charge within the interelectrode gap decreases such that cesium plasma is no longer necessary [4]. However, the interelectrode gap can be too small. With small gaps, less than 500nm, near-field evanescent-wave radiative heat transfer begins to dominate the device and inhibits power conversion efficiency by increasing the necessary heat input to the emitter [12]. In order to avoid space charge limitations and near-field evanescent wave radiative heat transfer, vacuum encapsulated µTECs should maintain an interelectrode gap between 1µm and

10µm [12].

As stated earlier, thermionic emission is governed by the Richardson-Dushman equation. However, in order to accommodate space charge inefficiencies and the

6 emission of electrons from the collector, the current density of a thermionic energy

converter is defined as the difference in the emitter and collector current densities:

Jnet = Jemitter − Jcollector (2) 2 ϕemitter +ϕME 2 ϕcollector +ϕMC = ATemitter exp(− ) − ATemitter exp(− ) kBTemitter kBTcollector € where ϕME and ϕMC are the additional barriers created by the electrostatic space charge

€ field in the interelectrode gap. The barriers ϕME and ϕMC can be calculated by Langmuir’s space charge theory [12]. The efficiency of a simple, close-spaced electrode thermionic

energy converter where ϕME and ϕMC are zero, can be defined as:

Pout Jnet (V0 − Jnet Rlead ) (3) η = = Pin Qtotal

where Jnet is the current density of the thermionic energy converter as defined above, Rlead

is the normalized€ resistance per unit area of the leads from the emitter and collector to the

external load, Qtotal is the total energy flux between the electrodes, and V0 is the voltage

difference between the emitter and collector [12] where:

(4) V0 = (ϕemitter +ϕME ) − (ϕcollector +ϕMC )

Increased thermal isolation, such that Temitter is larger than Tcollector, improves the

output current density of the device, Jnet. However, as the current increases, the voltage € loss in the connected leads to and from the device also increases. Additionally, the total

energy flux between the electrodes also increases. Therefore, to obtain an in increase in

efficiency, the collector work function must be smaller than the emitter’s work function

in order to maximize V0, which increases the total current density and deceases the total

energy flux. Lastly, Rlead should be minimized to minimize output power losses.

7 1.4 Thesis Overview

In the following sections, I will describe my work on improving the performance of next generation vacuum encapsulated microfabricated thermionic energy converters.

Over the past year, I have worked to design a new microfabricated emitter based on the work of Dr. Jae-Hyung Lee [1][13]. I will describe the new design of the emitter to create a smaller interelectrode gap to decrease space charge, improve thermal isolation, prevent leakage current, create a more robust fabrication process, and optimize a design for flexible testing of new emitter and anode.

Chapter 2

Thermionic Emitter Redesign

2.1 Motivation

My work on the thermionic micro-emitters involved building on the work of Dr.

Jae-Hyung Lee and in his recently published paper in the Journal of

Microelectromechanical Systems [1] and thesis [13]. Dr. Lee was able to produce a thermally isolated thermionic emitter with a work function of 1.7eV [1]. However, the emitter was not optimal. By decreasing the suspended leg width while maintaining structural integrity, better thermal isolation can be obtained. Additionally, Dr. Lee’s

Figure 5: Scanning electrode microscope image at a 45˚ angle of a 500µm x 500µm plate, thermally isolated, suspended, emitter with sidewalls of 30µm and leg width of 10µm [1] 9 Figure 6: Final layout cross-section of device in Figure 5 going from the contact pad on the left of the device to the contact pad on the right of the device. This figure depicts the device after the low work function coating, which is not shown in Figure 5. In this cross-section, the n-doped poly- silicon carbide structure is being anchored to two pillars made of silicon and a silicon oxide layer [1]. device was not optimized for integration with a collector on the frontside because his device was originally designed for downward emission toward the silicon substrate, which previously had served as a collector. The emission area for the emitter was recessed, as seen in Figures 5 and 6, to create a micron scale gap with the substrate-based collector and to retain the low work function coating. Unfortunately, when testing this emitter with a collector other than the substrate, the interelectrode gap will be 30µm because of the recess, much larger than the ideal gap size. Thus, it is important that we redesign the emitter for upward emission. While Dr. Lee demonstrated a method for using an ITO collector on a separate substrate that could test different combinations of emitters and collectors, the interelectrode gap was about 100µm [1]. On the next design iteration, it was important to devise a method to test the optimized emitter with an equally optimized collector with a 1 micron-scale gap size. In the following sections, I will address how I designed a thermionic emitter to improve deficiencies of the previous device.

10 2.2 Emitter design process

In order to have a large current output, it is crucial there is sufficient thermal isolation between the emitter and collector. Dr. Lee maintained thermal isolation through

10µm wide, suspended, silicon carbide, thermally isolating legs that connected to the substrate using a silicon pillar with a silicon oxide layer [1]. However, thermal isolation can be improved by making the leg width smaller because there is less area for thermal conduction. There is major constraint when shrinking the legs: the legs must be stiff enough that the structure does not buckle upon heating. We know from Dr. Lee’s previous emitters that plate sizes of 500µm x 500 µm are stable using 10µm wide legs, which are include on the new layout. Additionally, we included 200µm x 200µm plates with 5µm legs in order to increase thermal isolation by 50% and 10µm so we have a conservative alternative.

The original emitter was designed for downward emission and also served as a receptacle for the work function lowering material. However, by recessing the emitter, the interelectrode gap increases. Therefore, on the subsequent devices, we decided to raise the emitter plate to be flush with the top of the sidewalls as seen in the next chapter.

Raising the plates may seem trivial, but because the device will be functioning at temperatures over 1000K, thermal expansion is a serious concern. With an ideal gap of

~5µm, buckling due to thermal expansion could cause the emitter to touch the collector and short the device. Therefore, out of plane rigidity was increased to stiffen the suspension beams. Not only are the legs U-shaped like Dr. Lee’s previous device [1], but the new designs also have a U-shaped trench around the perimeter of their plates.

11 Figure 7: Optical image of 3x3 waffle pattern plate after the 'anchor' and 'mold' etches described in the next chapter. The spaces between the squares are about 10 µm deep, the same depth as the legs

In order to increase rigidity in the plate, I created two new plate designs. One design involved creating a U-shaped ‘moat’ with a depth of ~10µm around the perimeter of the plate. This design maximized the amount of surface area of the device while providing desired rigidity. The other design involved creating a waffle pattern that provides even stiffer rigidity than the previous design. The plate is separated into a 3 x 3 grid, where the lines separating each grid is a 10µm etched U-shaped trench, Figure 7.

These U-shaped trenches are the same depth as the legs. Finally, the last design was the same as Dr. Lee; however, the depth of the plate was decreased to approximately 10µm from 30µm.

Another consideration for the plate design is the dispensing of low work function coatings. Previously, BaO/SrO/CaO liquid was coating was dispensed using a micropipette onto the device plate, Figure 8. By having the emitter recessed, the coating stayed on the plate. However, by raising the plate, the work function lowering material may spill off the plate before annealing. While the ‘moat’ pattern may provide the most surface area, it will be the most difficult to apply the coating because of the lack of

12 Figure 8: The previous emitter after the application of the BaO/SrO/CaO coating before annealing completing the Figure 5 cross-section, lowering the work function to about 1.7eV [1]. Notice that the drop casting caused the coating to be applied to a larger area than the plate, which is undesired.

Figure 9: Dr. Lee’s emitter after annealing using optical heating with temperatures of 1600-1800K for one hour. While the physical appears changes, the work function of the emitters remain approximately 1.7eV. topography; however, the waffle pattern is not tremendously better for work function adhesion because of the lack of a recess. Therefore, it is important that the previous plate design is not completely abandoned so that we can test different low work function

13 coatings. A conformal deposition process, such as atomic layer deposition, would eliminate these concerns of work function coating adhesion.

The emitter plate recess was not the only aspect limiting the proximity of the emitter and collector. Previously, each emitter had to be independently wire-bonded to two contact pads in order to be tested. Consequently, the interelectrode gap must be minimally greater than the radius of the bond-wire (10µm) because the thermionic converter would short, if the collector touched the bond-wire.

Figure 10: Layout of three devices electrically connected to a contact pad

14 In order to minimize the number of wire bonds and their location on the chip, we introduced two new designs. First, the rationale for having two contact pads was so that the emitters could be both resistively heated an optically heated; however, we decided to focus on optical heating. Ideally, all four legs of the emitter would be grounded for this method. If two sets of legs were attached to two different bond pads that were each connected to a local ground such as the device in Figure 5, the two grounds could be slightly different causing an unwanted voltage difference across the device. Therefore, I devised a method to connect all four legs to the same bias by using a contact ring around the emitter.

Now that all of the devices only need a single contact to ground, we can introduce the next optimization, the creation of arrays of emitters, Figure 10. For each emitter in a column, its contact ring is connected to a rail leading to a contact pad. The contact pads run along the perimeter of the chip in order to prevent wire bonding from interfering with emitter-collector testing. Because we intend to only test a few of the emitters at a time, we only need to wire-bond to a particular side of the chip and can then lay a collector

Figure 11: Layout of emitter with a guard ring

15 across the emitters under test.

However, some of the wafers have an additional rail that can also be connected.

This rail connects to a guard-ring, Figure 11, a structure that helps electrically isolate the individual emitters from the rest of the chip. The guard-ring helps combat leakage current by having a gold electrical contact surrounding the device that is also grounded. Leakage current affects the output performance of the device by charging the oxide layer, which could decrease the thermionic current. The guard ring may not improve our device because the voltage difference is small and may not produce a significant leakage current.

By optimizing the emitter for upward emission and limiting the amount of wire

Figure 12: Test Structures after etching the ‘mold’ and ‘anchor’ masks as described in the next chapter. Top to Bottom: Guckel rings, cantilevers, beams

16 bonding for individual emitters, we can eliminate physical limitations affecting our ability to reach the ideal interelectrode gap. The redesigned emitter will not introduce unwanted space charge limitations.

Lastly, I included a variety of test structures on the chip in order to better understand the physical limitations of the structure. I included an array of cantilevers in order to measure the stress gradient of the U-shaped SiC, an array of SiC clamped- clamped beams to measure compressive stress, and an array of Guckel rings in order to determine the tensile stress of the U-shaped SiC, Figure 12. Lastly, I provided an area to measure the SiC with a 4-point probe to determine the resistivity of the carbide.

The Guckel rings give a rough estimate of the tensile stress by buckling. When the Guckel ring is released, a force is applied to the ends of the crossbar and causes the crossbar to buckle laterally or out of plane. The smallest radius the buckling occurs is the critical radius. We can then derive the stress [14]. Similarly, the clamped-clamped beams buckle when enough compressive stress is applied. The largest beam that bends is the critical beam and can be used to derive the compressive stress. Using a profilometer, we can measure the beams to determine if there is curvature [14]. Lastly, the cantilevers measure the gradient stress of the carbide. The gradient stress can be determined by using a profilometer the to measure the deflection of the cantilever and knowing the physical and material properties of the cantilever [14].

2.3 TEC Test Assembly Design

The emitters are optically heated. Currently, in order to test a thermionic device, the emitter array is placed in a test fixture that uses ITO as the collector, Figure 13. The

17 Figure 13: Test fixture developed by Dr. Lee. Uses ITO as a transparent collector [1]. benefit of ITO is that it is transparent so the laser can pass through the collector and optically heat the emitter. Unfortunately, the low work function collectors are not transparent. One method to optically heat by way of frontside illumination is to shine the laser into the interelectrode gap at an angle. However, if we aim to have a gap on the order of 1 micron, laser illumination is impractical. Thus, frontside illumination TEC testing is not feasible, and we will focus on backside illumination.

We can shine the laser into the aperture to heat the emitter by creating an aperture in the silicon substrate below the emitter we would like to test. While this solution solves our problem of optical heating, there are several design considerations. First, we would like to keep the substrate of the chip cool. If the aperture is smaller than the spot size, which it is in our case, then the laser will also heat the substrate. We can mitigate the substrate heating by applying a reflective metal coating to the backside of the wafer to deflect the laser.

Another major concern with the backside apertures is maintaining the structural integrity of the chip. If each emitter had a backside aperture, there would be an etched

18 hole for each device. By having this many perforations in the structural handle of the chip, the chip would become fragile and liable to break during die repositioning.

The next major chip level integration is the introduction of spacer beads to create the interelectrode gap between the emitter and collector. Along the perimeter of the chip containing the emitters, we can place alumina ceramic microbeads in an etched trench to serve as structural separators. Additionally, heat cannot conduct easily through alumina, and thus allow for the beads to maintain thermal isolation when integrated with the collector [15].

After the beads are placed along the perimeter of the chip, we can lay the collector atop of the chip. In order to guarantee the collector chip does not fall and damage the emitters, it is important that the collector covers the emitter under test, but the collector or collector holder overlaps three sides of the emitter chip. Additionally, we do not need to worry if the beads would move and damage the emitter devices because we place the beads within a trench along the perimeter of the emitter chip. A benefit of the microbead separators is the ability to easily exchange different emitters as long as the emitter chip or the emitter holder is large enough to be supported by the microbeads.

Thus, by creating backside apertures and integrating the emitter and collector chips using microbeads, we are able to create a process that can easily test µTEC collectors while using a variety of potential emitters. This was a very important design decision from a research perspective because we have discovered a way to move toward complete integration and manufacturability. In practice, one side of the converter is heated, while the other is unaffected. With our new integration design, not only are we able to mimic real use scenario by heating a signal device while having a collector at a

19 small gap, we are also able to swap collectors with different work functions to help determine the best materials for the collector. Additionally, it was previously impossible to test collectors than were not transparent. Now with the new design, the only restraint on the emitter is that it can be assembled with a holder that is supported by the microbeads. Lastly, the whole package testing ability will illustrate the potential efficiency of a µTEC and provide insight for whole device fabrication processes.

2.4 Chapter summary

This chapter provided motivation for redesigning a microfabricated thermionic emitter for better thermal isolation and decreased space charge. The emitter redesign focused on raising the plate for upward emission, in order to decrease spacing between the emitter and collector. To also help with interelectrode spacing, we changed the contact pad layout to decrease the amount of wire bonding. The plates were redesigned designs to improve emitter rigidity and leg widths were decreased to help improve thermal isolation.

The chip level redesign focused on optimizing the layout for optical heating.

Because we would like to test a variety of opaque collectors using the emitter devices, we decided to optically heat the emitters using backside illumination through an aperture.

We can create an interelectrode gap of ~5µm by using ceramic alumina microbeads, which are placed on the emitter to support the collector.

By redesigning both on the chip level and device level, we create a more robust process that aims to improve efficiency. Additionally, we are now being able to construct

20 a thermionic converter with optimal work functions and an ideal gap size. Thus, these improvements will provide insight on the future of µTECs.

Chapter 3

Fabrication

3.1 Introduction

A robust fabrication process is critical for improving the yield of devices on a wafer. In Dr. Lee’s previous design, he depended on a high-risk structural release processing step. He performed a timed XeF2 isotropic silicon etched to remove the silicon below the emitter plate and the emitter thermal isolation suspension legs [13]. However, the legs were anchored to a silicon pillar [12], so if the silicon is over-etched, the emitter plate would collapse because the legs would no longer be supported. Such risky fabrication processes are not scalable nor are they desirable, and therefore, do not support our goal of proving commercial viability. Next, the previous fabrication process was examined to address any unnecessary difficulties, such as large topography introduced too early, affecting subsequent lithography steps. Additionally, a fabrication redesign was important to address new desired features such as the backside aperture.

22 3.2 Layout design

All reticles for the lithography steps were designed in CleWin4. The first major redesign consideration was to eliminate the timed release etch in XeF2. Because XeF2 does not etch silicon carbide (SiC) or silicon oxide (SiO2), we can anchor the SiC emitter to the SiO2 buried oxide (BOx) layer, instead of to a silicon pillar. Additionally, the

Figure 14: Layout designs. (A) 'Mold' mask, exposing the gold area. (B) 'Anchor' mask (fuchsia) overlapping A, etching the fuchsia area. (D) 'SiC Protect' mask in teal, overlapping B, etching non- colored regions. (D) 'Gold' mask, depositing gold in black region.

23 Figure 15: Image using an optical microscope of a guard ring structure with a waffle pattern and a 200µm x 200µm plate after the mold and anchor etches contact pads sat on the raised Si device layer. If the silicon below the contact pads was

etched, the contact pads could either be released or weakened and not survive wire-

bonding. Anchoring the emitter to the BOx layer has another advantage: no need for

release holes. Because we have a high tolerance for over-etching, release holes are

unnecessary to aid in the release of the plate. Therefore, by eliminating the release holes,

we are able to increase the surface area of the plate and no longer have holes the liquid

work lowering coating could drip through. Thus, we had to redesign the first two major

reticles: the ‘mold’ and ‘anchor’ masks.

The ‘mold’ mask allows us to expose the plate and leg designs. Everywhere that

requires the U-shaped trough as mentioned in the previous chapter is exposed using this

reticle. The ‘anchor’ reticle allows us to expose all areas that we would like the SiC to

attach to the BOx layer. This includes all areas we would like gold to be deposited, such

as rails and contact pads, and also at the ends of the suspension anchors. Additionally, the

trench for the microbeads mentioned in Section 2.3 is also exposed in this lithography

step.

24 Figure 16: Overall digital layout of the chip excluding perimeter etching masks. All layers are overlapping. From top left: structures using Dr. Lee’s previous design, Dr. Snapp’s experimental designs. Middle: emitters connected using guard rings. Bottom left: test structures, hexagonal emitter, 200µm x 200µm plate emitters, 500µm x 500µm emitters. Notice the bond pads are along the perimeter of the chip to increase area the collector can lay without shorting due to contact with a bonding wire. The next mask design defines the emitter. This reticle, ‘SiC Pattern’, protects all areas where we would like the SiC to remain while exposing the rest of the chip. This step defines the emitter and electrical contacts. Additionally, this step allows us to expose holes in the trench around the perimeter of the chip where the microbeads can fit and be stable.

The backside mask has the same functionality as the frontside ‘SiC Pattern’ mask, except it protects the entire backside of the wafer except where we would like the optical

25 Previous Fabrication Process

Figure 17: Fabrication process for a suspended thermionic micro-emitter. (a) Initial 4-inch SOI wafer (35 µm device layer, 4 µm BOX). (b) After patterning DRIE etching to define 30 µm deep silicon trenches. (c) After depositing 2-µm-thick n-type polycrystalline 3C-SiC. (d) After patterning poly-SiC layer using SPR 220-7 thick resist and anisotropic RIE. (e) After DRIE etch of the exposed silicon layer to minimize undercut of the contact area. (f) After deposition of gold contact. (g) After releasing the emitter using XeF2. (h) After removing buried oxide layer using vapor HF etching. (i) BaO/SrO/CaO liquid was coated on the emitter. (i’) The suspended poly-SiC emitters were sputtered with ∼50 nm of tungsten. (j’) The emitter was manually coated with BaO/SrO/CaO dissolved in a solvent; subsequent heating in vacuum results in a stabilized coating on the W-coated poly-SiC [1]

26 apertures. This mask does not have an opening for each emitter because of the structural integrity issue described in the previous chapter.

Lastly, I designed two masks that allow us to make shadow masks for the metal evaporation steps for tungsten and gold. The tungsten mask allows us to evaporate tungsten onto the emitter plates to help with adhesion of the work function lowering material. The gold mask allows us to deposit gold in the trenches where we want to electrically contact.

3.3 Fabrication methodology

The fabrication process for the µTEC involves 14 primary steps. All machines used and processes performed were done in the Stanford Nanofabrication Facility except for the SiC deposition that was performed at the Marvell Nanofabrication Laboratory at

UC Berkeley. Additionally, all lithography exposure was done in the SNF’s ASML 5500 stepper. We start with a SOI wafer with a device layer of 25µm, a BOx layer of 500nm, and a handle of 400µm. Following the process flow, Figure 18, we pattern the wafer using the ‘mold’ mask and etch (~10µm deep in the STS deep RIE etcher)(Step A). Next, we perform a secondary lithography process with spin-coated resist and expose the

‘anchor’ pattern. Because of the topography introduced in the first etch, the photoresist has to be much thicker than normal, introducing process complication. Afterwards, the

‘anchors’ are etched completely through the device layer in the STS etcher and stopping on the BOx (Step B). The wafers are then deposited with either a 900nm or a 1.6µm layer of SiC (Step C). A LCPVD layer of low-stress, conformal, oxide, twice as thick as the

Fabrication Process

(A) (B)

(E) (F)

(G) (H)

28 (I) (J)

(K) (L)

(M) (N)

(O) (P)

Figure 18: Fabrication process of the µTEC using an SOI wafer with a BOx layer of 500nm, device layer of 25µm, and handle of 400µm. Steps A and B define the shape of the emitters and anchors it to the BOx layer, the width of the corrugations is exaggerated in these cross-sections. Step C is the deposition of highly n-doped SiC. Steps D and E define the low temperature oxide hard mask for the SiC etch. Step F is the front side SiC etch. Steps G through I define the backside aperture. Step J is the isotropic removal of oxide. Step K is the deposition of a backside metal reflective coating. Step L is the isotropic device release in XeF2. Step M is the deposition of W. Step N is the deposition of Au. Step O is the deposition of a low work function coating after drop-casting. Step P is the BaO/SrO/CaO coating after annealing.

29 SiC layer, is deposited on the wafers to serve as a hard mask for future lithography steps

(Step D). Next, the oxide on the frontside of the wafer is etched using P5000 (Step E).

After the hard mask has been etched, the SiC is etched in Lampoly until reaching the silicon device layer (Step F). The process then transitions to the backside aperture. The backside oxide is etched (Step G), then the SiC (Step H) using the same tools as Steps E and F, respectively. Then, the aperture is etched using STS until reaching the BOx layer

(Step I). The oxide is then removed using isotropic etching in HF acid (Step J). Not only does this step strip the oxide hard mask, but it also removes the BOx layer between the device and the aperture. The metal reflective coating mentioned in Chapter 2 is then evaporated onto the backside of the wafer at an angle to prevent it from covering the area where the BOx was located (Step K). The wafers are then diced into nine die (not pictured). The die are individually placed in the Xactix machine in order to release the structures using an isotropic etch of silicon in XeF2 (Step L). Afterwards, Tungsten then

Gold is evaporated onto the front side of the wafer using hard masks (Step M and N).

Lastly, a work function lowering coating is either drop-cast on to the plates (Step O) or applied using atomic layer deposition. We will then anneal the coating using optical heating in a vacuum chamber with temperatures of 1600-1800K for one hour (Step P).

3.4 Chapter Summary

In this chapter, the new process was described. I proposed eliminating silicon based supporting structures for the contact pads and anchors for the suspended legs by instead anchoring directly to the BOx layer. Additionally, I described the purpose of etch reticle used in the lithography process and illustrated each major process step. Processing

30 difficulties include applying thick photoresist and the creation of the backside aperture.

Overall, the new fabrication process allows us to have a more robust process and allow us to gain better results when testing because of the ability to utilize a backside aperture.

Chapter 4

Next Steps

4.1 Introduction

The current state of the fabrication run is Step D of the fabrication process as of

May 21, 2014. Next steps include finishing the fabrication of the devices and testing the emitters. Using the test structures, we can measure the physical stress and strain of the

SiC along with its conductivity. More importantly, we will need to measure the functionality of the emitters. Future tests include independent functionality testing of the emitter, as done by Dr. Lee, and packaged testing of the emitters with a variety of collectors.

4.2 Testing

The initial tests that can be performed are those involving the test structures immediately after Step L. Using optical profile measurements, we can inspect the Guckel rings in order to determine the residual tensile strain in the SiC, the clamped-clamped beams to determine the compressive stresses, and the cantilevers to obtain an estimated

32 Figure 19: Schematic of testing layout and image of setup. The emitters are on the XYZ manipulator and the metal anode (collector) is directly above [13] stress gradient [14]. It is important that these measurements are performed before and after heating the sample in order to and measure the stress stability under thermal cycling.

After gold deposition (Step N), we can begin testing the emitter without the work function lowering coating; however, the performance will improve after the application of the coating (Step O). The initial emitter testing will follow Dr. Lee’s testing procedure.

The emitter chip is mounted on a specially designed printed circuit board (PCB) with vacuum grease and the bond pad of the array of emitters we would like to test is wire bonded to a grounded bond pad on the PCB. The sample is then placed on the XYZ stage on the vacuum chamber’s flange. A blue laser diode (440nm – 455nm wavelength) with a spot size of ~750µm is placed in line with the sample and aligned to illuminate a single emitter [1]. After alignment, the flange is carefully placed inverted (Z-plane) into a high vacuum chamber (<10-6 Torr) [1]. After pump down, we apply a large voltage bias to the collector plate so that there is a strong enough electric field that the space charge affects will be minimal. Then, we can begin to increase the power of the laser to increase the emitter plate temperature. The plate temperature is recorded using an optical pyrometer (PYRO MicroTherm, 550-nm operating wavelength) [13]. The output current and laser output power are measured using a MATLAB script [13].

33 Figure 20: Thermionic current verses incident optical power for Dr. Lee’s device. Approximately 0.4 mA was measured at relatively low temperatures, 900-1400K, by applying 5-15V to a transparent collector located 100-200 µm away from the emitter, the same test setup as Figure 13. Assuming an output voltage of 0.8V, the estimated conversion efficiency is ∼0.5% [1].

Figure 21: Dr. Lee's experimental results measuring bare SiC, and SiC plates coated with Ba and BaO [13]

34 If we use the same work function lowering material as Dr. Lee, we can expect similar output performance for our 500µm x 500µm plates and will have a baseline comparison for our future combined emitter-collector testing. However, we hope to see a slight improvement in performance in thermal isolation between the emitter and the Si substrate. Because the collector does not touch the Si substrate in this setup, the thermal isolation should have no effect on the output current generated.

After using Dr. Lee’s testing setup, we will be integrating the collector and emitter as described in Section 2.3. The results will expose all critical design decisions concerning thermal isolation and the emitter-collector gap because the collector will be connected the substrate via the microbeads and a large voltage bias to induce a large electric field is not possible for the collectors tested.

The emitter chip will be placed on a PCB board that has a hole in the middle and only provides support on the perimeter of the chip in order to allow the laser to shine on the apertures. The chip will be secured using vacuum grease. The microbeads will be carefully drop-casted in the designated perimeter trench as described in Section 2.3. The collector will then be placed on top of the emitter but supported by the microbeads. To secure the collector, we will be using vacuum compatible insulated clamps to clamp the collector to the PCB board. The board will then be placed on an XYZ with Z-tilt digital translation stage on a flange so the laser can be focused after placing the flange in vacuum chamber. In order to know if the laser is focused, we also will need a photodetector to measure the reflection off of the backside reflective coating. When the photodetector current is at a minimum, the laser is focused. This setup is still being finalized because it is difficult to detect the deflected photons since the laser is in the

35 same plane. One solution is to use a specialized beam splitter that would allow for the laser to pass through the beam splitter from the laser to the sample but deflect the reflected photons away from the laser and toward a photodetector. Using Figure 19, the beam splitter could be between the lens and the sample, and the photodetector could be in a similar position as the metal anode (collector). The testing procedure will then follow

Dr. Lee’s experiments after the flange is placed in the vacuum chamber. We will be using an engineered graphene collector with a work function of about 1eV and an emitter with a work function of about 1.7eV during the integrated emitter-collector tests. This combination has a maximum efficiency potential of over 40% [12].

4.3 Chapter Summary

This chapter discussed the future processes needed for the thermionic emitter and converter. After fabrication is complete, we will test the individual emitter using two different setups. One involves testing the emitters using Dr. Lee’s setup, utilizing a high voltage collector plate to mitigate space charge while heating the samples using frontside illumination. The second set of tests will involve emitter-collector integration with backside illumination. These tests are crucial in demonstrating the viability of the future of µTECs and will be the foundation for future works.

Chapter 5

Conclusion

5.1 Summary

This honor’s thesis explored four key areas of next-generation microfabricated thermionic energy converters (µTEC) and specific improvements on the thermionic emitter. First, I explained the background of thermionic emission and the development of thermionic energy research that peaked during TOPAZ research era. Next, I described the physics of thermionic emission and clarified the Richardson-Dushman law and how it relates the output current of a µTEC to parameters corresponding to the emitter and collector. In the next chapter, I explained the purpose of redesigning the Dr. Lee’s previous emitter in order to increase efficiency and output current. Improvements focused on decreasing the interelectrode gap, improving thermal isolation, and optimizing for integration with low work function collectors. I then explained the layout design of the chips and the fabrication process involved in creating the new emitters. Lastly, I described the variety of testing that will be performed with the emitters. This includes testing the emitters independently and after assembly with collectors. My work on thermionic electron emitters has demonstrated a more manufacturable process.

37 5.2 Future work

Future work includes creating a robust design for an integrated thermionic energy converter array. By creating a densely packed chip of devices, the overall efficiency would be improved. However, major difficulties include applying two different work function lowering coatings to plates that are only separated by a couple microns. It may be that we would have to assemble the emitter and collector substrates after deposition of the coatings, similar to what we are doing for the current iteration.

An additional feature would be to integrate inverter functionality into the converter. By tuning the suspension legs to a particular resonant frequency to oscillate the plate in the interelectrode gap, we can produce an AC current. We would have to physically vibrate the converter, which would decrease the overall efficiency but because inverters already introduce inefficiencies to the system, an emitter with an integrated inverter may prove to be a better solution.

References

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