12th MRAM Global Innovation Forum

Virtual Forum, part of Intermag2021 Live part: 27 April 2021, 2:00 am Europe CEST / 8:00 am Asia CST / 7:00 pm (26 April) USA CDT

Sessions Topics Invited Speakers Welcome & Introduction (Bernard Dieny)

On- Ultrathin free layers for lowering the switching Tiffany Santos current in STT-MRAM ()

hysics, hysics, demand P ntegration I Co-optimization of thin film deposition, etching, Sahil Patel aterials and On-

M and encapsulation processes for high (Applied MRAM rocess rocess P demand performance STT-MRAM Materials)

On- Development of high-performance MRAM and Eric Edwards technology trade-offs (IBM) demand

Jeong-Heon On- Current status and future prospect of STT-MRAM for a mainstream memory Park demand (Samsung)

Johannes On- Line of Defense Strategies for Embedded STT- Product Development MRAM High Volume Manufacturing Muller demand (GLOBALFOUNDRIES) MRAM On- STT-MRAM in 16 nm FinFET for Solder-Reflow Yuan-Jen Lee demand Applications (TSMC)

On- Advanced MRAM based memory systems for near Shinobu Fujita demand future computing applications (KIOXIA) Technology Technology - On- A 2MB, 16nm, sub 5ns Reads, MRAM-based Jack Guedj Interaction demand Memory IP Core (Numem) Design

Shunsuke On- SOT-MRAM and emergent applications Fukami MRAM

- demand (Tohoku University) On- On-Chip 3D caches for advanced heterogenous Manu SoCs – A cross layer look at discerning MRAM Perumkunnil Beyond STT demand design and technology requirements (Imec) Live Question & Answer Session with Invited Speakers, moderated by Kevin Garello What do we need to bring MRAM to the next level? Panel Moderator: Luc Thomas () Discussion Live Panelists: Simone Bertolazzi (Yole), Gouri Sankar Kar (Imec), Daniel Worledge (IBM), Seung Kang (), Ko-Min Chang (NXP Semiconductor) 17:30 Closing remarks

Tiffany Santos Sahil Patel

Senior Manager, Senior Process Engineer, Western Digital Applied Materials

Sahil Patel is a process technologist with a background in film deposition and etching for spintronic devices. Prior to Tiffany Santos is a Senior Manager at Western Digital in joining Applied Materials where he works in the Advanced San Jose, California, working in the Research division on Product and Technology Development Group, he worked materials for non-volatile memory technology. She first on PVD and etch for STT-MRAM devices at TDK- joined the company in 2011, when it was previously Headway technologies. Sahil is interested in linking process known as Global Storage Technologies, to work conditions to final device performance in order to design on research of media for heat-assisted magnetic new processes and tools that can enable the next generation recording. She received her SB and PhD in Materials of semiconductor devices. Science and Engineering from the Massachusetts Institute of Technology, where she did her thesis research Co-optimization of thin film deposition, on magnetic tunnel junctions and thin film magnetism. etching, and encapsulation processes for After receiving a PhD, she became a Distinguished Postdoctoral Fellow, and later an Assistant Scientist, in high performance STT-MRAM the Center for Nanoscale Materials at Argonne Laboratory. In 2009, she was awarded a L’Oreal USA For compatibility with advanced node transistors, as well as Fellowship for Women in Science. to reduce overall chip power consumption to compete with conventional SRAM memory designs, STT-MRAM bits must be fabricated at reduced CD <50nm in order to reduce Ultrathin free layers for lowering the switching current, Ic. While for technologies at CD >50nm, switching current in STT-MRAM much of the focus on MRAM development has centered around MRAM stack deposition using etch processes that Tiffany S. Santos, Neil Smith, Goran Mihajlović, Jui- result in high bit yields, current development must focus on Lung Li, Matthew Carey, Jordan A. Katine, and Bruce the interplay of the MTJ film stack, etching, and D. Terris, Western Digital Research Center, Western encapsulation and their combined effect on the sidewall, Digital Corporation, San Jose, CA 95119 which represents a large portion of the final device. In this A primary challenge in the creation of a high-density talk, I will highlight experiments from our team at Applied spin-transfer torque magnetic random access memory Materials on mini-array short loop test vehicles which (STT-MRAM) technology is lowering the switching illustrate the need for 3-way co-optimization of film, etch current needed to switch the magnetization of the free and encapsulation to enable the next generation of MRAM layer (FL) when writing a bit in the MRAM , technologies. I will focus on unit processes, and how while maintaining high thermal stability for data improvements in unit processes can significantly improve retention. As the critical switching current density Jc0 the final device performance, but, more importantly, I will is proportional to the damping parameter α, saturation illustrate how these unit processes interact and can be magnetization MS and thickness tF of the FL, one combined to improve the final device performance and route toward lowering Jc0 is to lower tF. We present meet targets for specific MRAM applications. our approach to reduce tF while maximizing MS and minimizing α, thereby improving FL film quality and ultimately leading to lower Jc0. Conventional FLs typically have thickness > 2 nm. We have modified the FL design such that we can reduce tF down to 1.2nm while minimizing the magnetic dead layer, so that high MS > 1700 emu/cm3, high exchange constant Aex ~ 2.0 µerg/cm, and low α ~ 0.003 was obtained. We fabricated STT-MRAM devices having a ladder of FL thicknesses. Our device measurements show that Jc0 is lowest for the thinnest FLs, while the thermal stability factor ∆ remains high, so that overall, the thinnest FLs have the highest spin-transfer torque efficiency. Ref: T.S. Santos et al, J. Appl. Phys. 128, 113904 (2020) 1

Eric Edwards Jeong-Heon Park

Advisory Engineer, Principal Engineer, IBM Samsung

Jeong-Heon Park is a Principal Engineer at and currently works on Research and Eric Edwards is a member of the Advanced Logic & Development of STT-MRAM and emerging memories. He Memory Technology Research, Semiconductor, and AI is responsible for developing MTJ stack and module Hardware Group of IBM Research at the Thomas J. process for Samsung’s next generation MRAM and Watson Research Center. He received his PhD from the emerging devices with higher speed and higher density. He University of Muenster in 2012 with a thesis on the started his career at Samsung in 1999 where he had optical study of magnetization dynamics in thin films, developed integration processes for DRAM and Flash followed by postdoctoral work at the University of memories. He received a Ph. D in Materials Science and Regensburg and Martin Luther University Halle- Engineering at Carnegie Mellon University in 2010 where Wittenberg. From 2015 to 2018, he was a National he had studied perpendicular magnetoresistive devices for Research Council postdoctoral researcher at the National STT-MRAM and Spin Torque Oscillator. He has authored Institute of Standards and Technology in Boulder, or co-authored more than 50 research papers and holds more than 30 U.S. and international patents. Colorado working on high performance magnetic materials. He joined IBM Research in 2018, where he Current status and future prospect of works on the development of MRAM technology for STT-MRAM for a mainstream memory hybrid-cloud applications. With the recent evolution of data-intensive computing Development of high-performance systems, STT-MRAM has emerged as one of the most promising candidates of non-volatile memory solution with MRAM and technology trade-offs its high performance and logic process compatibility. In the conventional memory hierarchy, there exists a huge Twenty-five years after the invention of spin-transfer performance gap between high-speed cache and high- torque MRAM, the technology has reached wide density storage. As processor core-count rises and key adoption in the industry. MRAM has proven to be a applications require higher volume of data processing, the versatile technology able to cover a large range of performance gap causes significant increase in latency and applications, from non-volatile embedded memory to power consumption. This has called broad interest in DRAM-like standalone products. In its next incarnation, embedded non-volatile memory (eNVM) for its potential MRAM will be targeted to higher performance use as persistent on-chip memory to fill in the gap, resulting applications such as last-level cache for CPUs. In this in the improvement of the entire system performances. talk, we will review the new challenges faced by the With the fundamental benefits of harvesting “spin” instead industry for such applications and discuss what of “electrical charge”, STT-MRAM is regarded as a unique technological trade-offs are available. We will present a eNVM having high read/write speed, practically unlimited holistic view of our advanced MRAM technology from endurance and robust data security. Although STT-MRAM MTJ device physics to system-level considerations. We lies no longer on the pursuit of universal memory, its will see how the recent demonstrations of reliable high- superior adaptability makes it to be a very attractive speed switching and integration of sub-40nm MTJs on building block for diverse IoT and computing applications. 14nm FinFET indicate great potential for future high- The performance adaptability originates from tailoring performance MRAM technologies. magnetic tunnel junction (MTJ), key storage element of STT-MRAM. Non-volatility modulation is a possible way to customize MRAM performances by changing the magnitude of magnetic anisotropy energy in MTJs. In this case, reducing or enhancing magnetic anisotropy energy tunes the thermal stability of magnetic bits, which shifts the practical range of operating temperature and retention time with the corresponding scaling of write energy. While this type of short-range tunability expands the applicability of MRAM, fundamental breakthrough is needed to overcome the chasm of this technology and to pull it into the main stream of future memory sub-system. Here we discuss progress and challenge for enabling such technological innovations. 2 nnesMu high endurance lower level cache replacement may as well Johannes Müller be envisioned.

However, even though the technological challenges for this Group Manager NVM, first generation of embedded STT-MRAM have been GLOBALFOUNDRIES overcome, the passing of the baton as a full eFLASH replacement has not yet completed. Especially the vast amount of field data collected for classical eFLASH solutions and decades of manufacturing experience are still decisive factors that are slowing down the paradigm shift towards more advanced memory solutions. Here STT- MRAM needs to prove its ability to sustain the qualified Dr. Johannes Müller is a member of the eNVM reliability and yield in the course of volume ramp, as well development team at GLOBALFOUNDRIES Dresden and as its potential for continuous yield enhancement and wafer currently acts as the responsible MTJ-Module Integrator cost reduction. To gain this trust, inline methodologies to for the 22FDX™ STT-MRAM technology. Prior to joining tightly control the magnetic and electrical properties of the GLOBALFOUNDRIES he was heading the group for MTJ-based bit cell become an essential prerequisite. This Non-Volatile Memories at Fraunhofer IPMS (formerly is especially true for the foundry approach, where final known as CNT) overseeing direct industry collaborations assembly and functional test of the NVM-containing and European projects focused on FERAM, FeFET, STT- product are often directly conducted by the customer or a MRAM, RRAM, and FLASH. His research & third party, which leaves only inline data and electrical test development interests are primarily focused on the device sites to safeguard the quality of the outgoing material. physics, material development and integration of Consequently, a solid, multi-walled line of defense (LoD) embedded memory solutions, with a special interest lying is of utmost importance to first and foremost protect the in the exploration of emerging ferroelectric and customer and guarantee a reliable wafer disposition. ferromagnetic device concepts. Naturally, not only the detection of an excursion at the earliest manufacturing step possible, but also the entire Line of Defense Strategies for Embedded prevention of multiple non-conforming wafers, needs to be STT-MRAM High Volume part of the LoD strategy. This is highly rewarding since due to the late insertion point of BEOL-placed embedded Manufacturing memories the wafer has already acquired the largest part of its value when entering the MTJ processing steps. After several decades of trying to intercept FLASH based NVM solutions the frequently used term emerging In this presentation we will address the aforementioned memories began to slowly transition from a bold vision to challenges based on a 1T-1MTJ perpendicular STT- an everlasting stigma. Especially in the primarily cost per MRAM technology embedded into an advanced, low bit driven mass data storage segment the introduction of power CMOS platform (22nm Fully-Depleted Silicon-On- 3D-NAND FLASH further solidified the dominance of Insulator, 22FDX® technology). The unprecedented charge-based memories and provided a roadmap to complexity of this new memory technology needs to be continuously raise the entry-barrier to the stand-alone counteracted by an equally unprecedented reservoir of market. On the contrary, the window of opportunity for versatile and profound characterization methodologies that emerging memories to conquer the embedded NVM are capable of predicting the yield and reliability critical market kept opening wider from technology node to properties of the final memory cell. To enhance the turn- technology node. This shift towards emerging BEOL- around time of tool monitoring and to enable on-product placed memories, such as spin-transfer-torque magnetic film level and patterned MTJ metrology, the transition of random access memory (STT-MRAM), is mainly due to classical lab-based methodologies, such as perpendicular the constantly increasing incompatibility of FLASH-based magneto-optical Kerr effect (pMOKE), current-in-plane bit cells to advanced CMOS platforms. Main drawbacks tunneling (CIPT) and ferromagnetic resonance (FMR), to are the intrinsically exhausted planar scalability of full inline capability is essential. Correlation of these FLASH, its need for high voltage devices, as well as the magneto-electric and magneto-optical parameters to the challenging FEOL integration of Poly-SiON based End of Line wafer electrical test and reliability monitoring memory transistors into High-K-Metal-Gate technologies. are key for establishing a strong LoD. As a consequence, and with the break even in terms of mask adder and bit cell size being reached for the 2X nm This work was funded in the framework of the Important nodes, solder reflow capable pSTT-MRAM (1T-1MTJ) Project of Common European Interest (IPCEI) by the technologies are now entering the market as an economical Federal Ministry for Economics and Energy and by the eFLASH replacement [1]. Considering the unique State of Saxony tunability of the endurance-retention trade-off in magnetic devices and the emergence of alternative write concepts, [1] V.B. Naik et al., IEDM (2019) [2] T. Nozaki et al. such as voltage controlled magnetic anisotropy (VCMA) Micromachines (2019) [3] K. Garello et al. VLSI (2019) [2] and spin-orbit –torque (SOT) [3], a roadmap extending beyond this initial entry point all the way to high speed, 3

Yuan-Jen Lee Shinobu Fujita

Technical Manager, Senior Fellow, TSMC KIOXIA

Yuan-Jen Lee is a Technical Manager of MRAM Program Shinobu Fujita received his PhD from the University of in Embedded Technology Division at TSMC. He has 16 Tokyo and joined in 1989. He has been working years of professional experiences in the research and for new nonvolatile memory (NVM) circuit, system and development MRAM. Prior to joining TSMC, he was a application development for over 15 years. His major Senior Manager in the STT-MRAM team at TDK- applications are ReRAM-based NV-logics, ReRAM- Headway Technologies. He received Ph.D. degree in based-FPGA, NVM-based secure random number Physics from National Taiwan University in 2003. He has generators, NV-SRAM based cache memories, “normally- published 30+ MRAM relative papers and holds 20+ off processors” with STT-MRAM, persistent memory issued U.S. patents. systems with STT-MRAM. These are used from cloud computing to IoT edge computing and mobile devices. STT-MRAM in 16 nm FinFET for Currently, he is a Senior Fellow of KIOXIA corporation Solder-Reflow Applications (formally Toshiba Memory Corporation) and working on various NVM application projects including next

generation flash memories. Embedded STT-MRAM (eMRAM) can be used in a wide range of applications, such as microcontrollers (MCU), artificial intelligence (AI), and Internet of Things (IoT), to Advanced MRAM based memory name a few. This versatility is enabled by its non- systems for near future computing volatility, good endurance, reliable write, read performance, radiation hardness and CMOS process applications compatibility. TSMC has successfully demonstrated 22 nm (N22) eMRAM for solder-reflow capability with high Various kinds of advanced MRAM technologies and yield, reliability, and magnetic immunity. N22 eMRAM is memory systems have been intensively developed. This paper describes prospective views of near future currently in the mass production stage. computing applications from mobile/IoT edge computing Here we present eMRAM scaling at the next technology to cloud computing using MRAM. There applications use node, N16 FinFET. Stable, high yield has been three beneficial points of MRAM: fast persistent data demonstrated. Even with the smaller cell size compared to storage, performance improvement and energy saving of N22, this cell retains reflow capability and a data retention memory hierarchy. These are shown using some of 10 years at > 200oC. Compared to the N22 eMRAM, examples of computing applications in details. we demonstrate faster read access time and lower write power consumption at a wide temperature range— -40oC to 125oC. Endurance bit-error-rate (BERs) are low and no significant aging effect was observed after 1 M cycles.

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Jack Guedj Shunsuke Fukami

Co-Founder/CEO, Professor, Numem Tohoku University

Shunsuke Fukami, Ph.D. is a Professor of the Research Jack was President and CEO of Tensilica since 2008 where, Institute of Electrical Communication in Tohoku he transformed Tensilica into a rapidly growing company University. His areas of expertise include spintronics ascending to the #1 position in merchant DSP and physics/materials/devices and their application to ultimately leading to the Cadence acquisition in 2013 where integrated circuits and computing technologies. He he served as Corporate VP, Tensilica Products. received his Master’s degree in Nagoya University in

2005, and joined NEC Corporation. He received his Prior to Tensilica Jack led the spin-out of Magnum from Doctor degree from Nagoya University in 2012. In Cirrus Logic serving as founder, president and CEO. Jack 2011, he moved to Tohoku University. He received a led Magnum’s growth from ground zero to leadership in number of awards for his research, including the JSAP Multimedia SOCs for the Professional Video Broadcast, Young Scientist Presentation Award, the Young Consumer PVR TV/Camcorder/DVD Recorder and Set Scientists' Prize of Science and Technology by the Top Box markets and the acquisition of the Consumer MEXT, Asian Union of Magnetics Societies, Young Products Group of LSI Corporation (C Cube). Prior to Researchers Award, the Outstanding Research Award Cirrus, Jack was President of Tvia, Inc., leading that of the Magnetics Society of Japan, and the JSAP company’s successful IPO in August 2000. Jack holds an Outstanding Paper Award. MBA from the UCLA Graduate School of Management. Jack attained a MSEE from Pierre & Marie Curie SOT-MRAM and emergent Engineering School of Paris, and a doctoral degree from the applications University of Pierre & Marie Curie. Magnetoresistive random access memories (MRAMs) are A 2MB, 16nm, sub 5ns Reads, MRAM- promising to drastically reduce the power consumption of various integrated circuits while keeping or enhancing based Memory IP Core their performance, due to their nonvolatility and capabilities of fast and reliable operation. While the spin- High-Performance STT MRAM can bring many benefits to transfer torque (STT)-induced magnetization switching SOC designers for replacement of eFlash but also certain has been extensively studied for about two decades and is SRAMs and OTPs. With higher speed Reads, it can be used in the currently commercialized STT-MRAM, spin- ideally suited to meet the requirements of demanding DNN orbit torque (SOT)-induced magnetization switching [1-3] AI coefficient memory applications. has a potential to offer alternative pathway for even higher speed operation. In this presentation, I will show a material The device has been extensively tested using NuTest and device engineering [3,4] for the demonstration of Algorithmic tester both at Wafer level and packaged parts SOT-MRAM with 55-nm CMOS circuits fabricated including Radiation testing for Space/Defense applications through an industry-compatible 300-mm wafer process and accelerated endurance/Read disturb. [5,6]. Using three-terminal magnetic tunnel junction with in-plane magnetic easy axis and Ta/W channel, field-free switching is achieved down to the pulse width of 0.35 ns. I will also discuss emerging applications of STT and SOT technologies. An antiferromagnet/ferromagnet heterostructure controlled by SOT shows analog-like behavior [7], showing promise for artificial synapse in neural networks [8]. Also, stochastic nature of magnetic tunnel junction is useful for probabilistic computing, that has a similar functionality to quantum annealing machine [9]. The work has been carried out in collaboration with H. Ohno, T. Endoh, T. Hanyu, S. Sato, Y. Horio and their team members in Tohoku University as well as S. Datta, K. Camsari and their team members in Purdue University. The work is supported in part by the ImPACT Program of CSTI, JST-CREST JPMJCR19K3, and JSPS KAKENHI 19H05622. 5

Manu Perumkunnil PANEL DISCUSSION: Program Manager, Imec What Do We Need to Take MRAM to the Next Level?

Manu Perumkunnil Komalan completed his Integrated Moderator: Masters in Nanotechnology from Amity University, India in 2011. He received his Ph.D. in Electrical Engineering from Luc Thomas Katholieke Univ. Leuven, Belgium and in Computer Science from Universidad Complutense de Madrid in 2017. He then joined imec as a memory system architecture researcher. His Senior Director, research activity primarily involves exploration, analysis, and Applied Materials optimization of NVMs across the different layers of abstraction. He is also interested in system level design, bridging the gap between hardware and software. Currently, he is the Manager of the Memory INSITE program at Imec.

Luc Thomas is a Senior Director at Applied Materials, On-Chip 3D caches for advanced where he manages MRAM programs. Prior to joining heterogenous SoCs – A cross layer look at Applied Materials in March 2019, he was a Principal discerning MRAM design and technology Technologist in the STT-MRAM R&D group at TDK- Headway Technologies, and a Research Staff Member at requirements the IBM Almaden Research Center. He has authored and co-authored more than 100 publications and patents on For the most advanced CMOS nodes, because of diminished magnetic and spintronics materials and devices. He power, performance and cost returns, dimensional scaling must received his Ph.D. in Physics in 1997 from the University be now complemented by Design and System Technology Co- Joseph Fourier in Grenoble, France, and was elected optimization (DTCO and STCO) strategies, so that SoC fellow of the American Physical Society in 2012. bottlenecks can be mitigated. Performance scaling for SoCs has plateaued over the last decade because dimensional technology scaling has not been able to mitigate the ‘Memory Wall’ problem. This problem will only exacerbate with Machine Learning, Artificial Intelligence, Vision, and other data Panelists: dominated application domains coming to the forefront and also SRAM Power Performance and Area (PPA) gains saturating at advanced nodes. Simone Bertolozzi

To this end, it has become increasingly clear that 3-D integration Technology & Market and partitioning schemes can offer potential routes to continue Analyst, scaling and tackle the Memory Wall via DTCO and STCO innovations. This can be via enabling higher integration density, Yole heterogeneous (and novel) technology integration and extending the number of functions per 3-D chip. The 3-D integration scene has attracted a lot of interest over the past decade with demonstrations as well as commercial products like chiplets (AMD Rome, Milan in EPYC products) and 3D stacking ( Lakefield) more recently. Simone is a Technology & Market Analyst at Yole In this talk, I will give an overview for the need of 3D on-chip Développement (Yole), working with the cache like memories in highly heterogenous advanced SoCs for Semiconductor, Memory and Computing division. He is the future based on commercial references of today like the a member of Yole’s Memory team and contributes daily Apple 13, Kirin 990 etc via a top-down approach. Following to the analysis of memory markets and technologies, this, based on cross layer exploration results and validation by their related materials, and fabrication processes. means of a functional stacked 3D STT-MRAM array, design and Previously, Simone conducted experimental research in technology specifications for MRAM memories (namely STT the fields of nanoscience and nanotechnology, focusing and SOT) needed to make these feasible options for 3D on-chip on emerging semiconducting materials and their device cache like memories are derived. applications. He has authored or co-authored more than

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15 papers in high-impact scientific journals and was and Devices group, and in 2013 he became Senior awarded the Marie Curie Intra-European Fellowship. Manager of MRAM. He discovered perpendicular Simone obtained a PhD in Physics in 2015 from École magnetic anisotropy in CoFeB/MgO and led the team to Polytechnique Fédérale de Lausanne (Switzerland), demonstrate the first practical perpendicular magnetic where he developed cells based on tunnel junctions for Spin Torque MRAM. heterostructures of 2D materials and high-κ dielectrics. ______Simone also earned a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Seung Kang Milano (Italy), graduating cum laude.

______Director of Engineering, Gouri Sankar Kar Qualcomm

Program Director,

Imec

Seung Kang is a recognized semiconductor technologist who has holistically driven system-centric innovations of device, circuit design, and chip architecture. He built and led an advanced memory team at Qualcomm who Gouri Sankar Kar received the PhD degree in pioneered embedded STT-MRAM and delivered the semiconductor device physics from the Indian Institute industry-first product prototype for mobile SOC. He of Technology, Khragput, India in 2002. From 2002 to currently leads a team for developing sub-5nm CMOS 2005, he was a visiting scientist at Max Planck Institute logic architecture, circuit, and co-optimization for Solid State Research, Stuttgart, Germany, where he methodology. He received Ph.D. from U.C. Berkeley and worked with Nobel Laureate (1985, Quantum Hall both B.S. and M.S. from Seoul National University, Effect) Prof. Klaus von Klitzing on quantum dot FET. In Korea. Dr. Kang has published >100 papers and given 2006, he joined Infineon/Qimonda in Dresden, Germany >70 keynote and invited speeches. He served as as lead integration engineer. There he worked on the Distinguished Lecturer for the IEEE Electron Device vertical transistor for DRAM application. In 2009, he Society from 2014 to 2018 and as Visiting Professor at joined imec, Leuven, Belgium, where he is currently the Center for Innovative Integrated Electronic Systems program director. In this role, he defines the research of Tohoku University. He holds >240 granted US strategy and vision for SCM, DRAM, FeRAM and patents. MRAM programs both for stand-alone and embedded applications. He has authored, co-authored more than 200 peer-reviewed publications, many articles and holds Ko-Min Chang patents in the memory domain. ______Senior Director, Daniel Worledge NXP Semiconductor

Distinguished Research

Staff Member and Senior

Manager,

IBM Ko-Min Chang is a Senior Director at NXP. He joined Motorola 35 years ago after receiving the Ph.D from The Ohio State University. He initiated the development of many generations of proprietary embedded flash processes which served as the foundation of a long Dr. Worledge received a BA with a double major in history of popular Motorola/Freescale MCU product Physics and Applied Mathematics from UC Berkeley in families. Many of the flash cells and array concepts 1995. He then received a PhD in Applied Physics from developed by the team were published and were Stanford University in 2000, with a thesis on spin- subsequently adopted by other industry players for polarized tunneling in oxide ferromagnets. After joining embedded applications serving automotive, industrial, the Physical Sciences Department at the IBM T. J. and consumer segments. His focus in recent years has Watson Research Center, he invented and developed shifted to discovering and evaluating technologies that Current-in-Plane Tunneling (CIPT), enabling fast hold promising features to satisfy the explosive demand measurements of magnetic tunnel junctions. In 2003, Dr. on user experiences. Ko-Min holds 35 US patents and Worledge became the manager of the MRAM Materials served on IEDM and VLSI technical committees. 7

12th MRAM Global Innovation Forum INTERMAG 2021, 27 April 2021

1st Forum: San Jose, California 2nd Forum: Tokyo, Japan 3rd Forum: Paris, France 4th Forum: Seoul, South Korea 5th Forum: Tokyo, Japan 6th Forum: Santa Clara, California 7th Forum: Zurich, Switzerland 8th Forum: Seoul, South Korea 9th Forum: San Francisco, California 10th Forum: San Francisco, California 11th Forum: San Francisco, California

Chair: Bernard Dieny (SPINTEC, Univ. Grenoble Alpes /CEA/CNRS, France)

Program Co-Chairs: Luc Thomas (Applied Materials, USA) Kevin Garello (SPINTEC, France)

Acknowledgements: This Forum is the 12th of a series initiated by Samsung Semiconductor in 2013. We are grateful to this year’s Forum Sponsors, our two partners: