12Th MRAM Global Innovation Forum
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12th MRAM Global Innovation Forum Virtual Forum, part of Intermag2021 Live part: 27 April 2021, 2:00 am Europe CEST / 8:00 am Asia CST / 7:00 pm (26 April) USA CDT Sessions Topics Invited Speakers Welcome & Introduction (Bernard Dieny) On- Ultrathin free layers for lowering the switching Tiffany Santos current in STT-MRAM (Western Digital) hysics, hysics, demand P ntegration I Co-optimization of thin film deposition, etching, Sahil Patel aterials and On- M and encapsulation processes for high (Applied MRAM rocess rocess P demand performance STT-MRAM Materials) On- Development of high-performance MRAM and Eric Edwards technology trade-offs (IBM) demand Jeong-Heon On- Current status and future prospect of STT-MRAM for a mainstream memory Park demand (Samsung) Johannes On- Line of Defense Strategies for Embedded STT- Product Development MRAM High Volume Manufacturing Muller demand (GLOBALFOUNDRIES) MRAM On- STT-MRAM in 16 nm FinFET for Solder-Reflow Yuan-Jen Lee demand Applications (TSMC) On- Advanced MRAM based memory systems for near Shinobu Fujita demand future computing applications (KIOXIA) Technology Technology - On- A 2MB, 16nm, sub 5ns Reads, MRAM-based Jack Guedj Interaction demand Memory IP Core (Numem) Design Shunsuke On- SOT-MRAM and emergent applications Fukami MRAM - demand (Tohoku University) On- On-Chip 3D caches for advanced heterogenous Manu SoCs – A cross layer look at discerning MRAM Perumkunnil Beyond STT demand design and technology requirements (Imec) Live Question & Answer Session with Invited Speakers, moderated by Kevin Garello What do we need to bring MRAM to the next level? Panel Moderator: Luc Thomas (Applied Materials) Discussion Live Panelists: Simone Bertolazzi (Yole), Gouri Sankar Kar (Imec), Daniel Worledge (IBM), Seung Kang (Qualcomm), Ko-Min Chang (NXP Semiconductor) 17:30 Closing remarks Tiffany Santos Sahil Patel Senior Manager, Senior Process Engineer, Western Digital Applied Materials Sahil Patel is a process technologist with a background in film deposition and etching for spintronic devices. Prior to Tiffany Santos is a Senior Manager at Western Digital in joining Applied Materials where he works in the Advanced San Jose, California, working in the Research division on Product and Technology Development Group, he worked materials for non-volatile memory technology. She first on PVD and etch for STT-MRAM devices at TDK- joined the company in 2011, when it was previously Headway technologies. Sahil is interested in linking process known as Hitachi Global Storage Technologies, to work conditions to final device performance in order to design on research of media for heat-assisted magnetic new processes and tools that can enable the next generation recording. She received her SB and PhD in Materials of semiconductor devices. Science and Engineering from the Massachusetts Institute of Technology, where she did her thesis research Co-optimization of thin film deposition, on magnetic tunnel junctions and thin film magnetism. etching, and encapsulation processes for After receiving a PhD, she became a Distinguished Postdoctoral Fellow, and later an Assistant Scientist, in high performance STT-MRAM the Center for Nanoscale Materials at Argonne National Laboratory. In 2009, she was awarded a L’Oreal USA For compatibility with advanced node transistors, as well as Fellowship for Women in Science. to reduce overall chip power consumption to compete with conventional SRAM memory designs, STT-MRAM bits must be fabricated at reduced CD <50nm in order to reduce Ultrathin free layers for lowering the switching current, Ic. While for technologies at CD >50nm, switching current in STT-MRAM much of the focus on MRAM development has centered around MRAM stack deposition using etch processes that Tiffany S. Santos, Neil Smith, Goran Mihajlović, Jui- result in high bit yields, current development must focus on Lung Li, Matthew Carey, Jordan A. Katine, and Bruce the interplay of the MTJ film stack, etching, and D. Terris, Western Digital Research Center, Western encapsulation and their combined effect on the sidewall, Digital Corporation, San Jose, CA 95119 which represents a large portion of the final device. In this A primary challenge in the creation of a high-density talk, I will highlight experiments from our team at Applied spin-transfer torque magnetic random access memory Materials on mini-array short loop test vehicles which (STT-MRAM) technology is lowering the switching illustrate the need for 3-way co-optimization of film, etch current needed to switch the magnetization of the free and encapsulation to enable the next generation of MRAM layer (FL) when writing a bit in the MRAM cell, technologies. I will focus on unit processes, and how while maintaining high thermal stability for data improvements in unit processes can significantly improve retention. As the critical switching current density Jc0 the final device performance, but, more importantly, I will is proportional to the damping parameter α, saturation illustrate how these unit processes interact and can be magnetization MS and thickness tF of the FL, one combined to improve the final device performance and route toward lowering Jc0 is to lower tF. We present meet targets for specific MRAM applications. our approach to reduce tF while maximizing MS and minimizing α, thereby improving FL film quality and ultimately leading to lower Jc0. Conventional FLs typically have thickness > 2 nm. We have modified the FL design such that we can reduce tF down to 1.2nm while minimizing the magnetic dead layer, so that high MS > 1700 emu/cm3, high exchange constant Aex ~ 2.0 µerg/cm, and low α ~ 0.003 was obtained. We fabricated STT-MRAM devices having a ladder of FL thicknesses. Our device measurements show that Jc0 is lowest for the thinnest FLs, while the thermal stability factor ∆ remains high, so that overall, the thinnest FLs have the highest spin-transfer torque efficiency. Ref: T.S. Santos et al, J. Appl. Phys. 128, 113904 (2020) 1 Eric Edwards Jeong-Heon Park Advisory Engineer, Principal Engineer, IBM Samsung Jeong-Heon Park is a Principal Engineer at Samsung Electronics and currently works on Research and Eric Edwards is a member of the Advanced Logic & Development of STT-MRAM and emerging memories. He Memory Technology Research, Semiconductor, and AI is responsible for developing MTJ stack and module Hardware Group of IBM Research at the Thomas J. process for Samsung’s next generation MRAM and Watson Research Center. He received his PhD from the emerging devices with higher speed and higher density. He University of Muenster in 2012 with a thesis on the started his career at Samsung in 1999 where he had optical study of magnetization dynamics in thin films, developed integration processes for DRAM and Flash followed by postdoctoral work at the University of memories. He received a Ph. D in Materials Science and Regensburg and Martin Luther University Halle- Engineering at Carnegie Mellon University in 2010 where Wittenberg. From 2015 to 2018, he was a National he had studied perpendicular magnetoresistive devices for Research Council postdoctoral researcher at the National STT-MRAM and Spin Torque Oscillator. He has authored Institute of Standards and Technology in Boulder, or co-authored more than 50 research papers and holds more than 30 U.S. and international patents. Colorado working on high performance magnetic materials. He joined IBM Research in 2018, where he Current status and future prospect of works on the development of MRAM technology for STT-MRAM for a mainstream memory hybrid-cloud applications. With the recent evolution of data-intensive computing Development of high-performance systems, STT-MRAM has emerged as one of the most promising candidates of non-volatile memory solution with MRAM and technology trade-offs its high performance and logic process compatibility. In the conventional memory hierarchy, there exists a huge Twenty-five years after the invention of spin-transfer performance gap between high-speed cache and high- torque MRAM, the technology has reached wide density storage. As processor core-count rises and key adoption in the industry. MRAM has proven to be a applications require higher volume of data processing, the versatile technology able to cover a large range of performance gap causes significant increase in latency and applications, from non-volatile embedded memory to power consumption. This has called broad interest in DRAM-like standalone products. In its next incarnation, embedded non-volatile memory (eNVM) for its potential MRAM will be targeted to higher performance use as persistent on-chip memory to fill in the gap, resulting applications such as last-level cache for CPUs. In this in the improvement of the entire system performances. talk, we will review the new challenges faced by the With the fundamental benefits of harvesting “spin” instead industry for such applications and discuss what of “electrical charge”, STT-MRAM is regarded as a unique technological trade-offs are available. We will present a eNVM having high read/write speed, practically unlimited holistic view of our advanced MRAM technology from endurance and robust data security. Although STT-MRAM MTJ device physics to system-level considerations. We lies no longer on the pursuit of universal memory, its will see how the recent demonstrations of reliable high- superior adaptability makes it to be a very attractive speed switching and integration of sub-40nm MTJs on building block for diverse IoT and computing applications. 14nm