DATASHEET
RZ/V Series, VisionAI_ASSP RZ/V2M R01DS0372EJ0100 Rev.1.00 Apr 28, 2021
Section 1 Overview
1.1 Features This LSI chip includes the AI dedicated accelerator (DRP-AI) and 4K-compatible image signal processor (ISP). This processor is vision-AI ASSP for real-time human and object recognition.
The AI dedicated hardware IP, DRP-AI, configured with the dynamic reconfigurable processor (DRP) and AI-MAC, combines both a high-speed AI inference and low power consumption and realizes 1TOPS/W class power performance. In addition, the image signal processor (ISP) is highly robust, producing a stable image independent of the environment, allowing for a high AI recognition accuracy. With these features, this LSI realizes low power consumption, which is a critical factor for embedded devices, making heat dissipation measures easier. The result is that it is ideal for vision AI applications in a wide range of embedded markets, including surveillance security, retail, office automation (OA), industrial automation, and robotics. In addition, this LSI also features abundant high-speed communication interfaces such as USB 3.1, PCI Express®, Gigabit Ethernet, and many CPU peripheral functions, so it can also be used in a variety of applications.
CPU and DDR Memory Interfaces High Speed Interfaces ● Cortex®-A53 Dual (996 MHz maximum) ● 1× Gigabit Ethernet ● 32-bit LPDDR4-3200 ● 1× USB3.1 Gen1 Host/Peripheral ● 1× PCIe® Gen 2 (2 lanes) ● 2× SDIO 3.0 Vision and AI ● 1× NAND Flash Interface ONFI1.0 ● AI accelerator: DRP-AI (1.0 TOPS/W class) ● 1× eMMC™ 4.5.1 ● Image signal processor (ISP) with multi-stream capability ● Camera interface: 2× MIPI CSI ● Face and Human Detection Engine Hardware Security Engine provided
Video and Graphics, Display Package ● H.265/H.264 Multi Codec ● FCBGA (15×15 mm, 0.5-mm pitch) Encoding: H.265 up to 2160p30, H.264 up to 1080p120 Decoding: H.265 up to 2160p30, H.264 up to 1080p120 ● 2D Graphics Engine: 200 MPixels/s ● Display: MIPI-DSI (4-lane), HDMI 1.4a
R01DS0372EJ0100 Rev.1.00 Page 1 of 123 Apr 28, 2021
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GPIO IIC (4 ch.) CSI (6 ch.) SDI (2 ch.) UART (2 ch.) USB3.1 ( eMMC (1 ch.)* Host/Peripheral Motor controller LPDDR4 (32 bits) Individual tray Full carton Packing Ethernet MAC (1 ch.) NAND Flash (1 ch.)* Peripheral I/F Peripheral PCI Express (2 lanes) Environment sensor I/F External memory I/F Security Trusted Secure IP FPU 32 KB
A A L1 D cache - -
1 MB RAMB Core 1 JPEG codec cache (face, human body) 2D graphics engine Neon 32 KB Multi-target detection L1 I
PRBG0841KA PRBG0841KA Package CPU (DRP-AI)
Memory AI accelerator L2 cache: 512 KB FPU D cache 32 KB Arm Cortex-A53 L1
Video and graphics
Sensing and analyzing Core 0 RAMA 200 KB accelerator Camera ISP cache Neon 32 KB
General processing L1 I H.265/H.264 multi codec
Temperature sensor (2 ch.)
Analog Part Number for Ordering R9A09G011GBG#ACC R9A09G011GBG#BCC
.) Rev.1.00
Product Lineup Diagram of Functional Overview I2S (1 ch.) (v1.4a TX) Timers System WDT (2 ch.) (CoreSight) (4 lanes × 2) HDMI (1 ch.) ADC (20 ch.) PWM (16 ch.) Power control Timer (32 ch.) Audio I/F Arm debugger DMAC (16 ch MIPI CSI-2 v1.2 Display I/F (D-PHY TX v1.1)
MIPI DSI (4 lanes)
1 Product Lineup 1 The useThe of NAND flash memory and eMMC is exclusive of each other. Image Sensor I/F 1.1-
1.2-
igure R9A09G011GBG Product Part Number
Table 1.2 products. following the of consists currently group The
F Note 1. R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Overview 3 Page Page Section 1 Section
ontact sales our representative when
CA53 core 1)
) : 1 channel
: 16 channels
: 996 MHz
bit width)
-
/SWD)
: 2 channels (CA53 core 0, ) PHY Ver.1.2
: 32 channels
KB (with ECC)
AI
- 1
MB * 1.2/ D-
A53 dual core (CA53) Kbyte trace RAM), ETR, and STM incorporated - (16 channels) - match timer 2 Ver. -
purpose accelerator ) , Neon™ extension - (RAMA): 200 (RAMB): 1 4 width modulation timer (PWM)
/ target detectiontarget (face, human body time clock (RTC) Cortex A B - - ® ontroller (1 External trace output (16 ETF (64 YUV422: 8 bits CoreSight™ debugging components incorporated L1 cache: instructions) 32 KB (for data)+ 32 KB (for each for core L2 cache: 512 KB FPU ECC supported RAW: 8/10/12 bits
c – – – – – – – – –
4 lanes × 2, 2.5 lane:Gbps per Supports2 sensor inputs Audio sampling 32 kHz, rate: 44.1 kHz, 48 kHz AI accelerator (DRP Multi General Watchdog timer (WDT) Compare Pulse- Real MIPI CSI- Formats: Supports WDR extraction Virtual channel Arm Debugger interface (JTAG RAM RAM 128ROM: KB
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s
Rev.1.00
Overview of Functions
unction
F 1 using this format. Inputting data in this limits format functions the of the LSI that can be used . Please c
1.3-
able Sensing analyzing and Audio interfaces DMA controller image sensorCMOS interfaces Timers Memory Item CPU
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60 fps decoding 60 fps decoding × 30 fps decoding p process compliant
MHz clock, single pipeline)
speed DDRand HS400 are not supported)
based process/baseline -
- size
60 fps encoding, 1920 × 1080 p × 60 fps encoding, 1920 × 1080 p ×
are supportedMB are (high-
× 30 fps encoding, 3840 × 2160
main profile at level5
supported
GB bit data bus
bit ECC ) slice H.264/H.265 supported for encoding and decoding - bit data width 4
/ bit data width /8- /P 1920 × 1080 p × 3840 × 2160 p H.264/AVC baseline/main/high profile at level 5.1 H.265/HEVC H.265 encoding and H.265 decoding, H.264 or encoding and H.264 decoding 640 × 480 p × 800 fps encoding 1920 × 1080 p × 640 × 480 p × 800 fps encoding (2 4096 × 4096 texture Up to 4 JPEG extended DCT 3840 × 2160 p × 30 fps / 1920 × 1080 p × 30 fps × / 640 ×2 p × 480 800 fps supported WDR processing 3D noise reduction Fisheye correction
H.265 encoding and decoding performance ONFI1.0 compliant Supports KIOXIA’s BENAND™ not supportedEDO 8- 128 MB and 256 Supports HS200 1/4/8- I- 200 Mpixels second per fill- (200 rate 3200 Mbps 32- 4- Supported functions Support encoding/decoding standard Color format: YUV Image data rate: Max. 16 samples/clock cycle H.264 encoding and decoding performance
– – – – – – – – – – – – – – – – – – – – – – – – – PEC codec
NAND flash interface eMMC interface conforming to eMMC version 4.51 J 2D graphics engine LPDDR4 interface H.265/H.264 multi codec Camera ISPCamera
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able External memory interfaces Video & graphics Item
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speed Mbps), (12 and low- - 4 lanes , duplex mode -
(12 bits, (12 600 ksamples /sec) 1.1)
resolution
PHY Ver. PHY
bit SD bus)
D- speed (480 Mbps), full
I/SDR12, SDR25, SDR50, and SDR104 transfer modes
-
bit/4- -
: 2 lanes
speed is onlysupported for the host controller)
:
speed, UHS
loosely packed) : 2 channels (SD specification version compliant) 3.01 MIPI DSI Ver.1.3.1/ 8 6 ( 6 5 - - - - speed (5 Gbps), high Gbps), (5 speed- - 8 6 6 6 with 1280 × 720 p, 1920 × 1080 p
- - - - 4 channels
oot complex/endpoint
super xpress base specification revision 4.0 compliant
role device function supported (static switching of the host controller function and the TX: Max. 1024 bytes TX: Max. 128 bytes RX: Max.128 bytes digital video output format, supported - ) bit RGB 8 bit RGB 6 bit RGB 6 bit RGB 5 - - -
/4
224/256 tamper proofing algorithms implemented HS 24- 18- 18- 16- LP LP - (3 (DDR50, not supported) Supports card detection and write protection SD memory card access SD, for SDHC, SDXC and Supports default, high- Transmission and reception of command packets
Supports IEEE802.3 PHY GMII, MII compliant interface Supports the video formats SD memory / I/O card interface (1 Resolution conversion, picture compositing, and image frame adjustment Supports r
Supports DTV YUV HDCP, CEC, and HEAC, not supported Supports transfer at 1000 Mbps, and 100 Mbps in full Display control HDMI via and MIPI DSI interfaces USB3.1 Gen1 standard compliant Dual PCI E peripheral controller function) speed Mbps) (1.5 transfer (low- Supports
xternal supply power sequence control – – – – – – – – – – – – – – – – – –
AES and ARC4 encryption and decryption algorithms implemented RSA2048 signature verification algorithm implemented SHA Hardware Random Number Generator A/D converter: 12 channels, A/D converter: 8 channels Temperature sensor: 2 channels E Internal power domain control HDMI Tx interface v1.4a: 1 channel LCD control interface ( Ethernet MAC interface: 1 channel IIC bus interface: Clocked serial: 6 channels interface UART: 2 channels controlMotor Stepping control, motor serial interface dedicated to driver the motor Environment sensor interface Acquisition of external device data and transfer to the DRAM by an internal timer GPIO Display control USB interface: 1 channel PCI Express interface Gen2 (5GT/s) SD host interface (SDI)
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Rev.1.00
Overview of Functions
1 engine 1.3-
able Power control Analog Security Display interfaces Peripheral interfaces Item
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V switchable supply power
)
ower supply
/4 V p V/1.8- Vpower supply Vpower supply Vpower supply Vpower supply V power supply (4
PAMODVDD, PBMODVDD, PCMODVDD, IM0MODVDD, IM1MODVDD, NAMODVDD, SD0MODVDD, SD1FMODVDD,GEMODVDD USVD330, USVPH, VDD33 LVRXAVDD, HDAVDD08, DSMSVDD0P8, PCVDD08, USDVDD, USVP, USVPTX VDD08, RTVDD08,PWVDD08, LPVDD, PLDVDD08n (n = 1, 2, 3, 4, 6, 7), OTVDD08, TSnDVDD08A (n = 0, 1), LPVDDQ DSMVDD12 RTVDD PLVDDn = (n 1, 2, 3, 4, 6, 7), OTVDD18, TSnAVDD18 = (n 0, 1), ADnAVCCA = (n LVRXAVCC, 0, 1), LPVAA, HDAVDD18, DSMSVDD18, PCVDD18, USVDDH, PWVDD, VDD18, PAPREDVDD, PBPREDVDD, PCPREDVDD, IM0PREDVDD, IM1PREDVDD, NAPREDVDD, SD0PREDVDD, SD1FVDD,GEPREDVDD, PREDVDD33 3.3- 3.3- 1.1- 1.2- 1.5- 1.8- 0.8-
40 to +125ºC
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Rev.1.00
Tj) ( Overview of Functions
1 1.3-
able Temperature range Power voltage Item
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 of
7 AJ AJ GND XIN XOUT GND GND GERXD3 GERXD7 GEMDC GEPPS GECO L PAMODVDD PA PR E DV DD GE PRE DVDD GE MODVDD U SRESREF U SVD330 USVDDH HDREXT HDHPD HDSDA HDAVDD1 8 DSM VREG0P4V DSM DNDAT A0 DSMVDD1 2 NADAT4 NAMODVDD NAPRE DVDD NADAT5 NAWPN AH AH GND GND GND GND GND GND GND GND GND GND GETXEN GECLK GERXD0 GETXD1 GETXD2 GEMDIO PAMODVDD GETXER GE MODVDD USVBUS USVPH HDSCL HDAVDD1 8 DSM DP DAT A0 DSMVDD1 2 NADAT6 NAMODVDD NAREN NARBN Section 2 Section Page Page AG AG GND GND GND GND GND GND GND GND GND GND GETXD0 GETXC GETXD7 GETXD5 GETXD6 GE GTXCLK GETXD4 G ELI NK GERXC GERXD5 U SOTGID HDTXCP HDTX2P DSM DNDAT A3 DSMDPCLK NADAT0 NACLE NAALE LPDQS B T1 AF AF GND GND PM4 GEINT GND USDP GND GND GND GND GND GND CSRXD3 CSTXD3 CSCS3 CSSCL K3 GETXD3 GERXDV GECRS USRX0P HDTXCM HDTX2M DSM DP DAT A3 DSMDNCLK NADAT2 NADAT3 NACEN LPDQB11 LPDQS B C 1 AE AE PM5 PM7 GND GND USDM GND GND GND GND GND GND GND CSRXD1 CSSCL K1 CSTXD1 CSCS1 CSSCL K2 CSRXD2 GERXER GERXD1 USRX0M DSM DNDAT A2 DSM DNDAT A1 NADAT7 NAWEN LPDQB10 LPDMDBIB1 LPDQB14 LPDQB15 AD AD PM0 PM1 PM2 PM6 GND GND GND GND GND GND GND CSSCLK0 CSCS0 CSTXD0 CSRXD0 CSTXD2 CSCS2 GERXD2 GERXD6 USTX0P HDTX0P HDTX1P DSM DP DAT A2 DSM DP DAT A1 NADAT1 LPDQB8 LPDQB9 LPDQB13 LPDQB12 AC AC P0605 P0607 P0603 P0611 P0604 P0601 P0602 GND PM3 GND GND GND GND GND GND GND GND GND PC PR E DV DD GERXD4 USTX0M HDTX0M HDTX1M DSSDPCL K DSSDPDAT A0 LPVDDQ LPVDDQ LPVDDQ LPVDDQ AB AB GND P0609 GND P0606 P0610 P0608 P0600 GND GND GND GND RSTN GND USVP GND GND GND GND GND PCMODVDD USVPTX VDD18 DSSDNCL K DSSDN DAT A0 LPDQB0 LPDQB2 LPDQB1 LPDQB6 LPDMDBIB0 AA AA GND MD6 MD5 GND GND GND GND GND GND GND GND I2SDA1 I2SDA0 I2SCL1 I2SCL0 INEXINT4 VDD08 VDD08 U SDVDD U SDVDD PLDVDD0 8 7 HDAVDD0 8 DSM SVDD0 P 8 DSM SVDD0 P 8 LPDQS B T0 LPDQS B C 0 LPDQB3 LPDQB5 LPDQB7 Y Y GND MD3 MD7 MD4 GND GND GND GND GND GND GND GND GND VDD18 VDD18 INEXINT7 INEXINT3 VDD08 VDD08 VDD08 VDD08 PLVSS7 HDAVDD0 8 DSMSVDD1 8 DSMSVDD1 8 LPVDDQ LPVDDQ LPVDDQ LPVDDQ W W MD2 MD1 GND GND GND GND GND GND GND GND GND INEXINT6 INEXINT2 INEXINT0 INEXINT1 DETDO INEXINT5 VDD08 VDD08 VDD08 VDD08 PLVDD7 VDD08 VDD08 LPVDD LPDQB4 LPCAB0 L PCKEB1 L PCKEB0 V V GND MD0 GND GND GND GND GND GND GND GND GND GND LPZN VDD33 VDD33 DETDI DETCK USOVC PC R S TOU TB VDD08 VDD08 VDD08 VDD08 VDD08 VDD08 LPVDD LPCSB0 LPCSB1 LPCAB1 U U GND GND GND GND GND GND GND GND GND I M0 MODV DD I M1 MODV DD DESRSTN DETMS MTTXD1 MTTXD0 MTDRV2 VDD08 VDD08 VDD08 VDD08 T S1 DVDD0 8 A TS1AVDD18 LPVDD LPDTEST LPCAB 3 LPCLKBC LPCLKBT LPVAA LPVAA T T GND GND GND GND GND GND GND GND IM0PRE DVDD IM1PRE DVDD PRE DVDD3 3 MTRXD1 MTDRV4 MTDRV5 VDD08 VDD08 PLVDD6 PLVDD4 PLVDD2 PLVDD1 VDD08 VDD08 PLVSS3 PLVDD3 LPVDD LPVDDQ LPVDDQ LPVDDQ LPVDDQ R R GND GND GND GND GND GND GND MTDRV6 USPWEN MTDRV3 MTCS1 MTCS0 MTDC PLS 0 MTDC PLS 3 MTDRV0 VDD08 VDD08 PLVSS6 PLVSS4 PLVSS2 PLVSS1 PLDVDD0 8 3 LPVDD LPATEST LPCLKAC LPCAB 4 LPCAB 5 LPCAB 2 LPMRESETL P P GND GND GND GND GND GND GND GND GND MTSCL K0 MTSCL K1 DETRSTN MTDRV7 MTDRV1 MTDC PLS 2 RETEST1 VDD08 VDD08 PLDVDD0 8 6 PLDVDD0 8 4 PLDVDD0 8 2 PLDVDD0 8 1 VDD08 VDD08 LPVDD LPCLKAT LPCSA1 L PCKEA1 LPCAA1 N N GND GND GND GND GND GND GND GND GND GND PBMODVDD PBMODVDD IMSH U T1 IMSH U T0 RETEST0 MTRXD0 MTDC PLS 1 VDD08 VDD08 VDD08 VDD08 VDD08 VDD08 LPVDD LPCAA2 LPCAA5 LPCAA0 L PCKEA0 LPCSA0 M M PM9 MD8 GND GND GND GND GND GND GND GND GND GND PB PR E DV DD IM1SCL K IMSTSIG1 IMSTSIG0 IM0SIG1 IM0CS VDD08 VDD08 VDD08 VDD08 VDD08 VDD08 LPVDD LPVDDQ LPVDDQ LPVDDQ LPVDDQ L L PM15 PM8 PM10 GND GND GND GND GND GND GND GND GND IM1HS IM1VS IM1SIG1 IM0SIG2 IM0TXD VDD08 VDD08 VDD08 VDD08 VDD08 VDD08 LPVDD LPCAA3 LPCAA4 LPDQSAC0 LPDQA7 LPDQA4
K K
AUDI AUDO GND PM14 PM12 GND GND GND GND GND GND GND GND GND GND GND IM0HS AULRCK AUBI CK OTVDD08 T S0 DVDD0 8 A VDD08 VDD08 VDD08 VDD08 LPDQA0 LPDQSAT0 LPDQA3 LPDQA5
J J view) GND GND PM13 PM11 GND GND GND GND GND GND GND GND GND GND GND
OTVDD18 TS0AVDD18 AUMCLK AUPLLCLK VDD08 VDD08 VDD08 VDD08 VDD08 VDD08 LPDQA2 LPDQA1 LPDMDBIA0 LPDQA6
H H GND GND GND GND GND GND GND GND GND GND GND I M1CLK IM1SIG2 CSRXD5 CSCS5 CSSCL K5 CSCS4 CSTXD4 LVRXAVDD LVRXAVDD LVRXAVDD LVRXAVDD PCVDD08 PCVDD08 SD0 P RE DVDD LPVDDQ LPVDDQ LPVDDQ LPVDDQ (Top
G G GND GND GND GND GND GND IM0VS IM1CS IM1RXD CSTXD5 CSRXD4 CSSCL K4 LVRXAVSS LVRXAVSS LVRXAVSS LVRXAVSS PCVDD18 PCVDD18 SD1 FDAT2 SD0DAT0 AD1AIN 0 AD1AVCCA AD0AVCCA AD0AIN 0 PWSYSRSTN LPDQA8 LPDQA13 LPDQA15 LPDQA12 F F
Pins GND GND GND IM1TXD IM1SIG0 I M0CLK IM0SIG0 LVRXAVSS LVRXCK1 P LVRXAVSS LVRXCK0 P LVRXAVSS LVRXAVSS LVRXAVSS PCVDD18 PCVDD18 SD 1FWP SD1 FDAT0 SD0CD AD1AIN 2 AD1AVSSA AD0AVSSA AD0AIN 1 PWKY4N PWEN0 LPDQA9 LPDMDBIA1 LPDQA11 LPDQA14 Rev.1.00
E E GND GND GND GND GND GND GND IM0SCL K IM0RXD LVRXAVSS LVRXAVSS LVRXCK1 M LVRXAVSS LVRXCK0 M LVRXAVSS LVRXAVSS SD1 FDAT3 SD1FCMD SD0CMD AD1AIN 6 AD1AIN 3 AD0AIN 6 AD0AIN 2 PWC TE S T0 PWEN4 PWEN2 PWOUT1 LPDQA10 LPDQSAC1 D D
GND GND GND GND LVRXAVSS L VRXD7P LVRXAVSS L VRXD5P LVRXAVCC L VRXD3P LVRXAVSS L VRXD1P LVRXAVSS PCREFCKM PCRXD0P PCRXD1P SD0DAT3 SD0DAT2 SD0CLK AD1AIN 1 AD0AIN 4 AD0AIN 3 PWM EM SWIENA PWSD1SEL PWEN5 PWEN3 PWKY3N PWRSTN LPDQSAT1 Pin Assignment Pin C C GND GND GND GND LVRXAVSS L VRXD7M LVRXAVSS L VRXD5M LVRXAVCC L VRXD3M LVRXAVSS L VRXD1M LVRXAVSS PCREFCKP PCRXD0M PCRXD1M SD1 FDAT1 SD1FCL K SD0DAT1 AD1AIN 4 AD0AIN 7 AD0AIN 5 PWTEST PWPWM PWKY2N PWVBAT PWKY0N PWISO RTISO
1 B B Pin Assignment GND GND GND GND GND GND GND RTXIN LVRXAVSS L VRXD6P LVRXAVSS L VRXD4P LVRXAVCC L VRXD2P LVRXAVSS L VRXD0P LVRXAVCC PCTXD0P PCTXD1P SD 1FCD SD0WP AD1AIN 5 AD0AIN 11 AD0AIN 9 PWC TE S T1 PWSD0SEL PWOUT0 PWDE TR S TN RTRSTN 2.1- A A GND GND GND LVRXAVSS L VRXD6M LVRXAVSS L VRXD4M LVRXAVCC L VRXD2M LVRXAVSS L VRXD0M LVRXAVCC L VRXREXT PCTXD0M PCTXD1M PCREXT SD1FVDD SD1 F M ODVDD SD0 MODVDD AD1AIN 7 AD0AIN 8 AD0AIN 10 PWVDD PWVDD08 RTVDD08 RTVDD PWKY1N PWEN1 RTXOUT
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Section 2 Section Page Page LVRXCK0P LVRXAVSS AD0AIN6 AD0AIN2 PWCTEST0 PWEN4 PWEN2 PWOUT1 GND GND LPDQA10 LPDQSAC1 IM1TXD IM1SIG0 IM0CLK IM0SIG0 LVRXAVSS LVRXCK1P LVRXAVSS External Pin Name LPDQA14 LVRXAVSS LVRXAVSS GND PCVDD18 PCVDD18 SD1FWP SD1FDAT0 SD0CD AD1AIN2 AD1AVSSA AD0AVSSA AD0AIN1 GND PWKY4N PWEN0 GND LPDQA9 LPDMDBIA1 LPDQA11 IM0VS IM1CS IM1RXD CSTXD5 CSRXD4 GND
F29 G1 G2 G3 G4 G5 G6 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 Ball Ball Num. E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 F1 F2 F3 F4 F5 F6 F7
GND GND SD1FDAT3 SD1FCMD SD0CMD AD1AIN6 AD1AIN3 AD0AIN3 PWMEMSWIENA PWSD1SEL PWEN5 PWEN3 PWKY3N PWRSTN GND LPDQSAT1 IM0SCLK GND IM0RXD LVRXAVSS LVRXAVSS LVRXCK1M LVRXAVSS LVRXCK0M LVRXAVSS LVRXAVSS GND GND LVRXD5P LVRXAVCC LVRXD3P LVRXAVSS LVRXD1P LVRXAVSS PCREFCKM GND PCRXD0P GND PCRXD1P GND SD0DAT3 SD0DAT2 SD0CLK AD1AIN1 AD0AIN4 External Pin Name
E13 E14 E15 E16 E17 E18 E19 D21 D22 D23 D24 D25 D26 D27 D28 D29 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 Ball Ball Num. D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20
) /5 (1
AD0AIN5 PWTEST PWPWM PWKY2N PWVBAT PWKY0N PWISO RTISO GND LVRXAVSS PCREFCKP GND PCRXD0M GND PCRXD1M GND SD1FDAT1 SD1FCLK SD0DAT1 AD1AIN4 AD0AIN7 LVRXAVSS LVRXD7P RTXIN LVRXAVSS LVRXD7M LVRXAVSS LVRXD5M LVRXAVCC LVRXD3M LVRXAVSS LVRXD1M LVRXAVSS SD0WP AD1AIN5 AD0AIN11 AD0AIN9 GND PWCTEST1 PWSD0SEL GND PWOUT0 PWDETRSTN RTRSTN GND External Pin Name
D3 C21 C22 C23 C24 C25 C26 C27 C28 C29 D1 D2 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 B29 C1 C2 C3 C4 C5 C6 C7 C8 C9 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 Ball Ball Num. B17
Rev.1.00
Ball Numbers and External Pin Names
1 GND GND SD1FCD GND PCTXD0P GND PCTXD1P LVRXAVSS LVRXD6P LVRXAVSS LVRXD4P LVRXAVCC LVRXD2P LVRXAVSS LVRXD0P LVRXAVCC PWEN1 RTXOUT GND PWVDD PWVDD08 RTVDD08 RTVDD PWKY1N SD1FMODVDD SD0MODVDD AD1AIN7 AD0AIN8 AD0AIN10 LVRXAVCC PCTXD0M GND PCTXD1M GND PCREXT SD1FVDD LVRXREXT LVRXAVSS LVRXD6M LVRXAVSS LVRXD4M LVRXAVCC LVRXD2M LVRXAVSS LVRXD0M External Pin Name 2.1-
able B14 B15 B16 B12 B13 B9 B10 B11 B6 B7 B8 B4 B5 B1 B2 B3 A27 A28 A29 A25 A26 A22 A23 A24 A19 A20 A21 A17 A18 A14 A15 A16 A11 A12 A13 A9 A10 A6 A7 A8 A3 A4 A5 A1 A2 Ball Ball Num. T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Section 2 Section Page Page RETEST0 MTRXD0 MTDCPLS1 GND GND VDD08 VDD08 PBPREDVDD IM1SCLK IMSTSIG1 IMSTSIG0 IM0SIG1 IM0CS PM9 MD8 VDD08 VDD08 GND GND VDD08 VDD08 GND GND LPVDD GND GND GND GND LPVDDQ LPVDDQ LPVDDQ LPVDDQ PBMODVDD PBMODVDD GND IMSHUT1 IMSHUT0 LPDQSAC0 LPDQA7 GND LPDQA4 VDD08 GND GND VDD08 External Pin Name
N6 N7 N8 N9 N10 N11 N12 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 N1 N2 N3 N4 N5 Ball Ball Num. L26 L27 L28 L29 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13
VDD08 VDD08 LPVDD GND GND LPCAA3 LPCAA4 LPDQA3 LPDQA5 GND IM1HS IM1VS IM1SIG1 IM0SIG2 IM0TXD PM15 PM8 PM10 GND GND VDD08 VDD08 GND GND VDD08 VDD08 GND GND TS0DVDD08A GND GND VDD08 VDD08 GND GND VDD08 VDD08 GND GND GND GND GND LPDQA0 GND LPDQSAT0 External Pin Name
L19 L20 L21 L22 L23 L24 L25 K27 K28 K29 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 Ball Ball Num. K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26
) /5 (2
OTVDD08 LPDMDBIA0 GND LPDQA6 IM0HS AUDI AUDO AULRCK AUBICK GND PM14 PM12 VDD08 GND GND VDD08 VDD08 GND GND GND GND LPDQA2 LPDQA1 GND GND LPVDDQ LPVDDQ LPVDDQ LPVDDQ AUPLLCLK PM13 PM11 GND GND VDD08 VDD08 GND GND VDD08 GND OTVDD18 TS0AVDD18 GND AUMCLK GND External Pin Name
K9 J27 J28 J29 K1 K2 K3 K4 K5 K6 K7 K8 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 H24 H25 H26 H27 H28 H29 J1 J2 J3 J4 J5 Ball Ball Num. H23
Rev.1.00
Ball Numbers and External Pin Names
1 GND GND GND GND GND SD0PREDVDD GND GND LVRXAVDD LVRXAVDD LVRXAVDD PCVDD08 PCVDD08 CSCS5 CSSCLK5 CSCS4 CSTXD4 GND LVRXAVDD GND LPDQA12 IM1CLK IM1SIG2 CSRXD5 PWSYSRSTN GND LPDQA8 LPDQA13 LPDQA15 SD0DAT0 AD1AIN0 AD1AVCCA AD0AVCCA AD0AIN0 GND LVRXAVSS PCVDD18 PCVDD18 SD1FDAT2 GND LVRXAVSS LVRXAVSS External Pin Name LVRXAVSS CSSCLK4 GND 2.1-
able H20 H21 H22 H18 H19 H15 H16 H17 H12 H13 H14 H10 H11 H7 H8 H9 H4 H5 H6 H2 H3 G28 G29 H1 G25 G26 G27 G23 G24 G20 G21 G22 G17 G18 G19 G15 G16 G12 G13 G14 G9 G10 G11 G7 G8 Ball Ball Num. T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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10
Section 2 Section Page Page VDD08 GND GND VDD08 VDD08 PLVDD7 GND GND LPVDD GND GND GND LPCSB0 LPCSB1 LPCAB1 GND LPZN INEXINT6 INEXINT2 INEXINT0 INEXINT1 DETDO INEXINT5 MD2 MD1 GND GND VDD08 GND DETDI DETCK USOVC PCRSTOUTB MD0 VDD08 VDD08 GND GND VDD08 VDD08 GND GND VDD08 VDD08 GND External Pin Name
W12 W13 W14 W15 W16 W17 W18 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 Ball Ball Num. V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
LPCLKBC LPCLKBT GND LPVAA LPVAA VDD33 VDD33 DETMS GND MTTXD1 MTTXD0 MTDRV2 GND GND VDD08 VDD08 GND GND VDD08 VDD08 GND GND TS1DVDD08A TS1AVDD18 LPVDD GND LPDTEST LPCAB3 IM0MODVDD IM1MODVDD DESRSTN External Pin Name PLVDD1 VDD08 VDD08 PLVSS3 PLVDD3 LPVDD GND GND GND GND LPVDDQ LPVDDQ LPVDDQ LPVDDQ
U25 U26 U27 U28 U29 V1 V2 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 Ball Ball Num. T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 U1 U2 U3
) /5 (3
GND LPATEST LPCLKAC LPCAB4 LPCAB5 LPCAB2 GND LPMRESETL IM0PREDVDD IM1PREDVDD PREDVDD33 GND MTRXD1 MTDRV4 MTDRV5 GND VDD08 VDD08 PLVSS6 PLVSS4 PLVSS2 PLVSS1 GND GND PLDVDD083 GND LPVDD GND VDD08 MTDRV6 USPWEN MTDRV3 MTCS1 MTCS0 MTDCPLS0 MTDCPLS3 MTDRV0 GND GND External Pin Name PLVDD2 VDD08 GND GND PLVDD6 PLVDD4
T15 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 R22 R23 R24 R25 R26 R27 R28 R29 T1 T2 T3 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Ball Ball Num. P29
Rev.1.00
Ball Numbers and External Pin Names
1 LPCSA1 LPCKEA1 LPCAA1 LPVDD GND GND LPCLKAT GND PLDVDD081 VDD08 VDD08 GND GND VDD08 GND GND PLDVDD086 PLDVDD084 PLDVDD082 MTSCLK1 DETRSTN MTDRV7 GND MTDRV1 MTDCPLS2 RETEST1 VDD08 LPCSA0 GND LPCAA2 LPCAA5 LPCAA0 LPCKEA0 GND MTSCLK0 GND VDD08 VDD08 LPVDD GND GND GND VDD08 VDD08 GND External Pin Name 2.1-
able P26 P27 P28 P24 P25 P21 P22 P23 P18 P19 P20 P16 P17 P13 P14 P15 P10 P11 P12 P8 P9 P5 P6 P7 P2 P3 P4 N29 P1 N26 N27 N28 N23 N24 N25 N21 N22 N18 N19 N20 N15 N16 N17 N13 N14 Ball Ball Num. T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123
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11
Section 2 Section Page Page GERXER GERXD1 GND USDM GND USRX0M GND GND GND GND DSMDNDATA2 DSMDNDATA1 GND NADAT7 NAWEN CSRXD1 CSSCLK1 CSTXD1 CSCS1 CSSCLK2 CSRXD2 PM5 PM7 GND PM2 External Pin Name LPDQB9 LPDQB13 GND LPDQB12 PM6 GERXD2 GERXD6 GND USTX0P GND GND HDTX0P HDTX1P GND DSMDPDATA2 DSMDPDATA1 GND NADAT1 GND LPDQB8
AE18 AE19 AE20 AE21 AE22 AE23 AE24 AD26 AD27 AD28 AD29 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 Ball Ball Num. AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25
CSCS0 CSTXD0 CSRXD0 CSTXD2 CSCS2 PM0 PM1 GND GND LPDQB0 LPDQB2 LPDQB1 LPDQB6 GND LPDMDBIB0 CSSCLK0 PCPREDVDD P0605 P0607 P0603 P0611 P0604 P0601 P0602 GND External Pin Name PM3 GND GERXD4 GND USTX0M GND GND HDTX0M HDTX1M GND DSSDPCLK DSSDPDATA0 GND GND GND GND LPVDDQ LPVDDQ LPVDDQ LPVDDQ
AD2 AD3 AD4 AD5 AD6 AD7 AD8 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AD1 Ball Ball Num. AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9
) /5 (4
DSSDNDATA0 GND GND GND RSTN GND USVPTX USVP GND GND VDD18 DSSDNCLK LPDQB7 GND PCMODVDD GND P0609 GND P0606 P0610 P0608 P0600 GND HDAVDD08 DSMSVDD0P8 DSMSVDD0P8 GND GND GND LPDQSBT0 LPDQSBC0 LPDQB3 LPDQB5 MD6 MD5 GND GND VDD08 VDD08 GND GND USDVDD USDVDD PLDVDD087 INEXINT4 External Pin Name
AB21 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AA28 AA29 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 Ball Ball Num. AA6
Rev.1.00
Ball Numbers and External Pin Names
1 I2SCL1 I2SCL0 GND LPVDDQ LPVDDQ LPVDDQ I2SDA1 I2SDA0 DSMSVDD18 GND GND GND LPVDDQ GND PLVSS7 HDAVDD08 GND GND DSMSVDD18 MD4 VDD08 GND GND VDD08 VDD08 GND VDD08 GND VDD18 VDD18 GND INEXINT7 INEXINT3 MD3 MD7 LPDQB4 GND LPCAB0 LPCKEB1 LPCKEB0 VDD08 VDD08 LPVDD GND GND External Pin Name 2.1-
able AA3 AA4 AA5 AA1 AA2 Y27 Y28 Y29 Y24 Y25 Y26 Y22 Y23 Y19 Y20 Y21 Y16 Y17 Y18 Y14 Y15 Y11 Y12 Y13 Y8 Y9 Y10 Y6 Y7 Y3 Y4 Y5 W29 Y1 Y2 W27 W28 W24 W25 W26 W21 W22 W23 W19 W20 Ball Ball Num. T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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12
Section 2 Section Page Page HDAVDD18 DSMVREG0P4V GND DSMDNDATA0 DSMVDD12 NADAT4 NAMODVDD NAPREDVDD NADAT5 NAWPN GND — — — GEMODVDD XIN XOUT USRESREF USVD330 USVDDH HDREXT HDHPD HDSDA External Pin Name GERXD3 GERXD7 GEMDC GEPPS GECOL PAMODVDD PAPREDVDD GEPREDVDD
AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 — — — Ball Ball Num. AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18
LPDQSBT1 GETXEN GECLK GERXD0 GETXD1 GETXD2 GEMDIO PAMODVDD GND GETXER External Pin Name GND GND HDAVDD18 GND GND DSMDPDATA0 DSMVDD12 NADAT6 NAMODVDD GND NAREN NARBN GND GND GEMODVDD GND GND USVBUS USVPH GND HDSCL
AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AJ1 Ball Ball Num. AG29 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16
) /5 (5
DSMDNDATA3 DSMDPCLK GND GND NADAT0 GND NACLE NAALE GND GND GERXC GERXD5 GND USOTGID GND GND HDTXCP HDTX2P GND GETXD0 GETXC GETXD7 GETXD5 GETXD6 GEGTXCLK GND GETXD4 GELINK External Pin Name LPDQB11 LPDQSBC1 GND
AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AF28 AF29 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 Ball Ball Num. AF27
Rev.1.00
Ball Numbers and External Pin Names
1 CSSCLK3 PM4 GETXD3 GEINT CSRXD3 GND CSTXD3 CSCS3 GND GND LPDQB10 LPDMDBIB1 LPDQB14 LPDQB15 External Pin Name GND NADAT2 NADAT3 NACEN GND DSMDPDATA3 DSMDNCLK GND USDP GND USRX0P GND HDTXCM HDTX2M GND GERXDV GECRS 2.1-
able AF25 AF26 AF22 AF23 AF24 AF20 AF21 AF17 AF18 AF19 AF14 AF15 AF16 AF12 AF13 AF9 AF10 AF11 AF6 AF7 AF8 AF4 AF5 AF1 AF2 AF3 AE27 AE28 AE29 AE25 AE26 Ball Ball Num.
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) Pins 123 3 3 3 able able able able T T T of and and and
2 2 2
- - - - 2.2 able - 2.2 able - 2.2 able 13 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin — — — —
Section 2 Section
2 2 2 Page Page
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Output — — — — — — — — — Fixed* — — Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* Fixed* — — — — — — — Drive Strength Drive / Selectable Fixed Selectable* Selectable* Selectable* -
ch
- — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — N Open Drain — — —
Input OFF OFF OFF OFF OFF OFF OFF OFF OFF — OFF OFF — — — — — — — — — — — — — — — OFF — -up/Pull -downPull — — — — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — — — — — — — — — — — — — — — — — — Schmitt Trigger — — —
up up up up up up up up down down up down down
Open Pull Pull Pull Pull Pull Pull Pull Open Pull Pull Open Open Open Open Pull Open Pull Pull Pull Pull Open Open Open Open Open Open Open Open Open — Pin State Pin State when not in Use — — — Pull Pull Pull Open Open Open -
Z Z Z Z Z - - - - - Hi Don’tcare Don’tcare Don’tcare Don’tcare Don’tcare Don’tcare L L L L L Don’tcare L Hi Don’tcare Don’tcare Don’tcare L L L L L L L L — CLOCK — — — CLOCK Don’tcare Initial Value Initial Value Power after onReset Hi Hi Hi
V OSC
-
18)
/
(1
I/O power
-V OSC -V OSC
PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O RTCI/O 1.5 PWC supply PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWC core power supply PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O PWCI/O RTC I/O, 1.5 I/O, RTC supply power RTC power core supply PWCI/O PWCI/O 1.5 RTCI/O I/O Group PORT00 I/O PORT00 I/O PORT00 I/O
1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.5 1.5 Voltage (V) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.5 0.8 1.8 1.8 1.5 1.5 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
O I I I I I I O I O I/O — IO IO O O O O I O — IO I O O O O O O O O — — I I I I List of External Pins
List Externalof Pins
External Pins External 1
2.2-
able NADAT2 NADAT1 PWVDD NADAT0 PWISO PWVDD08 PWCTEST0 PWCTEST1 PWMEMSWIENA PWPWM PWSD0SEL PWSD1SEL PWSYSRSTN PWOUT0 PWOUT1 PWEN3 PWEN4 PWEN5 PWDETRSTN PWEN0 PWEN1 PWEN2 PWKY2N PWKY3N PWKY4N PWVBAT PWKY0N PWKY1N PWRSTN PWTEST RTISO RTVDD RTVDD08 RTXIN RTXOUT RTRSTN Pin Name Pin
2.2.1 T 2.2 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) ) ) ) Pins 123 3 3 3 3 3 4 4 4 4 3 3 3 3 3 3 able able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T T of and and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 14 — — 2.2 Multiplexed (see pin 2.2 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T —
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output — Selectable* Selectable* Selectable* — Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* -
ch - — — — — — — — — N Open Drain — — — — — — — — — —
Input — -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — — — — Schmitt Trigger — — — — — — — — — — te
— Pin Sta Pin when not in Use Open Open — Open Open Open Open Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z Z Z Z Z Z Z Z Z Z ------— — Initial Value Initial Value Power after onReset Hi Hi Hi L Hi Hi PU Hi Hi Hi Hi Hi Hi Hi Hi Hi
-driver
18)
/ (2
T01(A) I/O
PORT00 pre PORT00 supply power PORT00 I/O power supply I/O Group PORT00 I/O PORT00 I/O PORT01(A) I/O PORT01(A) POR PORT00 I/O PORT00 I/O PORT00 I/O PORT00 I/O PORT00 I/O I/O PORT01(A) I/O PORT01(A) PORT00 I/O PORT00 I/O PORT00 I/O PORT00 I/O PORT00 I/O
3.3/1.8 Voltage (V) 3.3/1.8 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
— IO I/O IO IO IO O — IO IO IO IO IO IO IO IO IO IO IO List of External Pins
1
2.2-
able PM3 PM2 PM1 NAPREDVDD PM0 NAWPN NAMODVDD NARBN NAALE NACLE NAWEN NAREN NACEN NADAT7 NADAT6 NADAT5 NADAT4 Pin Name Pin NADAT3
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) ) Pins 123 4 4 4 4 4 4 4 5 4 4 4 4 4 able able able able able able able able able able able able able able able T T T T T T T T T T T T T of and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 15 — — Multiplexed Multiplexed (see pin 2.2 Multiplexed Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 T T T T T — —
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output Selectable* — — Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* — — Selectable* Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed -
ch - — — — — — — — — — — — — — — — — — N Open Drain
Input PU/PD/OFF changeable — — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable -up/Pull -downPull — — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — — — — — Schmitt Trigger
— — Open Pin State Pin State when not in Use Open — — Open Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z Z Z Z Z ------— — — — Initial Value Initial Value Power after onReset Hi PD Hi Hi Hi Hi Hi PD Hi Hi PD PD Hi
-driver -driver
18)
/ (3
PORT01(B), PORT01(B), PORT04,PORT07, pre PORT21 supply power PORT01(A), PORT01(A), pre PORT03 supply power PORT01(B), PORT04,PORT07, PORT21 I/O power supply PORT01(A), PORT01(A), PORT03 I/O power supply PORT02 I/O I/O Group PORT01(B) I/O PORT01(B) PORT01(B) I/O PORT01(B) I/O PORT01(B) I/O PORT01(B) I/O PORT01(B) I/O PORT01(B) I/O PORT01(B) PORT01(A) I/O PORT01(A) I/O PORT01(A) I/O PORT01(A) I/O PORT01(A) I/O PORT01(B)
3.3/1.8 3.3/1.8 Voltage (V) 1.8 1.8 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
— — IO I/O IO — IO IO — IO IO IO IO IO IO IO IO IO List of External Pins
1
1
2.2-
able INEXINT0* PBPREDVDD PBMODVDD PM15 PM14 PM13 PM12 PM11 PM10 PM9 PAPREDVDD PM8 PAMODVDD PM7 PM6 PM5 Pin Name Pin PM4
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) Pins 123 5 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 able able able able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T T T T of and and and and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 16 Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed -
ch - — — — — — — — — — — — — — — — — — N Open Drain
Input PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
Schmitt Trigger
Open Open Open Open Open Open Open Pin State Pin State when not in Use Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ------Initial Value Initial Value Power after onReset Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi
18)
/ (4
PORT02 I/O PORT02 I/O PORT02 I/O PORT02 I/O PORT02 I/O PORT02 I/O PORT02 I/O I/O Group PORT03 I/O PORT03 I/O PORT03 I/O PORT03 I/O PORT03 I/O PORT03 I/O PORT03 I/O PORT03 I/O PORT03 I/O PORT03 I/O
Voltage (V) 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
IO IO IO IO IO IO IO IO IO IO IO IO I/O IO IO IO IO IO List of External Pins
1
1 1 1 1 1 1 1
2.2-
able CSRXD2 CSTXD2 CSCS1 CSRXD1 CSSCLK1 CSTXD1 CSCS0 CSSCLK0 CSRXD0 CSTXD0 INEXINT7* INEXINT6* INEXINT5* INEXINT4* INEXINT3* INEXINT2* Pin Name Pin INEXINT1* T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
ns
) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) Pi 123 7 7 7 7 7 7 7 7 8 8 8 6 6 6 6 6 6 able able able able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T T T T of and and and and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 17 Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed Selectable* Selectable* -
ch - — — — — — — — — — — — — — — — N Open Drain — —
Input PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — Schmitt Trigger — —
State State Open Open Open Pin Pin when not in Use Open Open Open Open Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z - - - - - Initial Value Initial Value Power after onReset Hi Hi Hi PD PD PD PD Hi PD PD PD PD PD PD Hi PD PD
18)
/ (5
PORT05 I/O PORT05 I/O PORT05 I/O I/O Group PORT04 I/O PORT04 I/O PORT04 I/O PORT04 I/O PORT03 I/O PORT03 I/O PORT03 I/O PORT04 I/O PORT04 I/O PORT04 I/O PORT04 I/O PORT03 I/O PORT03 I/O PORT03 I/O
Voltage (V) 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 1.8 1.8 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
IO IO IO IO IO IO IO IO IO IO I/O IO IO IO IO IO IO IO List of External Pins
1
1 1 1 2.2-
able I2SDA1* I2SCL0* I2SDA0* CSSCLK5 CSCS5 CSRXD5 CSTXD5 CSCS4 CSSCLK4 CSRXD4 CSTXD4 CSCS3 CSSCLK3 CSRXD3 CSTXD3 CSCS2 Pin Name Pin CSSCLK2 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) )
) ) ) ) ) ) ) ) ) ) ) ) ) Pins 123 9 9 9 9 9 9 9 10 10 10 8 9 9 9 9 9 able able able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T T T of and and and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 18 — Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T —
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output Selectable* — Selectable* Selectable* Selectable* Selectable* Selectable* — Drive Strength Drive / Selectable Fixed Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* -
ch - — — — — — — — — N Open Drain — — — — — — — — — —
Input PU/PD/OFF changeable — -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — Schmitt Trigger — — — — — — — — — —
State State — Open Pin Pin when not in Use Open Open — Open Open Open Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ------— — Initial Value Initial Value Power after onReset Hi Hi PD Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi
-driver
18)
/ (6
PORT06 pre PORT06 supply power PORT06 I/O power supply PORT05 I/O I/O Group PORT07 I/O PORT07 I/O PORT06 I/O PORT07 I/O PORT06 I/O PORT06 I/O PORT06 I/O PORT06 I/O PORT06 I/O PORT06 I/O PORT06 I/O PORT06 I/O PORT06 I/O PORT06 I/O PORT06 I/O
3.3/1.8 Voltage (V) 1.8 3.3/1.8 3.3/1.8 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
IO IO — IO I/O IO — IO IO IO IO IO IO IO IO IO IO IO IO List of External Pins
1
1
2.2-
able AUDI AULRCK AUBICK PCPREDVDD P0611 PCMODVDD P0610 P0609 P0608 P0607 P0606 P0605 P0604 P0603 P0602 P0601 P0600 Pin Name Pin I2SCL1* T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) Pins 123 11 11 11 11 11 12 12 12 12 12 10 10 10 11 11 11 able able able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T T T of and and and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 19 — Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T —
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output — Selectable* Selectable* — Selectable* Selectable* Drive Strength Drive / Selectable Fixed Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* -
ch - — — — — — — N Open Drain — — — — — — — — — — — —
Input — -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — Schmitt Trigger — — — — — — — — — — — —
— Pin State Pin State when not in Use — Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z Z Z Z Z Z Z Z ------— — Initial Value Initial Value Power after onReset PD Hi Hi Hi Hi Hi Hi Hi Hi Hi PU Hi PD PD Hi Hi
-driver
18)
/ (7
PORT08 pre PORT08 supply power PORT08 I/O power supply I/O Group PORT07 I/O PORT08 I/O PORT09 I/O PORT09 I/O PORT09 I/O PORT09 I/O PORT08 I/O PORT08 I/O PORT08 I/O PORT08 I/O PORT08 I/O PORT09 I/O PORT07 I/O PORT07 I/O PORT08 I/O PORT08 I/O
3.3/1.8 Voltage (V) 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
— IO IO I/O IO IO IO IO IO — IO IO IO IO IO IO IO IO IO List of External Pins
1
2.2-
able SD1FDAT2 SD1FDAT0 SD1FDAT1 SD1FCLK SD1FCMD SD0MODVDD SD0PREDVDD SD0CD SD0WP SD0DAT3 SD0DAT2 SD0DAT1 SD0DAT0 SD0CLK SD0CMD AUPLLCLK AUMCLK Pin Name Pin AUDO T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) ) ) Pins 123 13 13 13 13 13 13 13 14 14 12 12 12 13 13 able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T of and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 20 — — — — Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 T T T T T — —
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output — — Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* — Selectable* — Selectable* -
ch - — — — — — — — — N Open Drain — — — — — — — — — — — —
Input — — PU/PD/OFF changeable -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable OFF PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable — PU/PD/OFF changeable — PU/PD/OFF changeable
— — — — Schmitt Trigger — — — — — — — — — — — —
— — Pin State Pin State when not in Use Open Open Open Open Open Open Open Open Open Open Open Open — Open Open Open — Open -
Z Z Z Z Z Z Z ------— — Initial Value Initial Value Power after onReset L L Hi Hi Hi — — PD PD PD Hi PD Hi PD Hi Hi PU PD
-driver -driver
18)
/ (8
PORT10 pre PORT10 supply power PORT09 pre PORT09 supply power I/O Group PORT11 I/O PORT10 I/O PORT10 I/O PORT10 I/O PORT10 I/O PORT10 I/O power supply PORT09 I/O power supply PORT11 I/O PORT11 I/O PORT10 I/O PORT10 I/O PORT10 I/O PORT10 I/O PORT10 I/O PORT09 I/O PORT09 I/O PORT09 I/O PORT10 I/O
Voltage (V) 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
IO IO IO I/O — IO IO O IO IO — — IO O IO IO IO IO — IO IO List of External Pins
1
2.2-
able IM1CLK IM1HS IM0PREDVDD IM1VS IM0MODVDD IM0SIG2 IM0SIG1 IM0SIG0 IM0SCLK IM0RXD IM0CS IM0TXD IM0CLK IM0HS SD1FVDD IM0VS SD1FMODVDD SD1FCD SD1FWP Pin Name Pin SD1FDAT3 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) Pins 123 14 15 15 15 15 16 16 16 16 16 14 14 14 14 14 14 able able able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T T T of and and and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 21 — Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T —
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output Selectable* Selectable* Selectable* Selectable* — Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed — Selectable* Selectable* Selectable* -
ch - — — — — — — — — — — — — — — N Open Drain — — — —
Input PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable — PU/PD/OFF changeable PU/PD/OFF changeable -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — — — — — — — — — Schmitt Trigger — — — —
Open Open Open — Open Open Pin State Pin State when not in Use Open Open Open Open Open Open Open — Open Open Open Open -
Z Z Z Z Z Z Z Z ------— PD PD PD PD PD Initial Value Initial Value Power after onReset Hi Hi Hi Hi — PD Hi Hi Hi PD Hi PD
-driver
18)
/ (9
PORT13 I/O PORT13 I/O PORT13 I/O PORT13 I/O PORT11 pre PORT11 supply power PORT13 I/O I/O Group PORT12 I/O PORT12 I/O PORT11 I/O PORT11 I/O PORT11 I/O power supply PORT12 I/O PORT12 I/O PORT11 I/O PORT11 I/O PORT11 I/O PORT11 I/O PORT11 I/O
Voltage (V) 3.3 3.3 3.3 3.3 3.3/1.8 3.3/1.8 3.3/1.8 1.8 3.3 3.3/1.8 3.3 3.3 3.3 3.3 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
IO IO IO IO IO IO IO IO I/O IO IO — — IO IO IO IO IO IO List of External Pins
1
2.2-
able MTDRV4 MTDRV2 MTDRV3 MTDRV1 MTDRV0 IMSTSIG1 IMSTSIG0 IMSHUT1 IMSHUT0 IM1MODVDD IM1PREDVDD IM1SIG2 IM1SIG1 IM1SIG0 IM1SCLK IM1RXD IM1TXD Pin Name Pin IM1CS T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) Pins 123 16 17 17 17 17 17 17 17 17 18 18 16 16 16 16 16 16 able able able able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T T T T of and and and and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 22 Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed Selectable* -
ch - — — — — — — — — — — — — — — — — N Open Drain —
Input PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — — — — — — — Schmitt Trigger —
Open Open Open Open Open Pin State Pin State when not in Use Open Open Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z Z Z Z Z Z ------Hi Hi PD PD PD Initial Value Initial Value Power after onReset PD Hi Hi PD Hi Hi PD PD Hi Hi Hi Hi
18)
(10/
PORT14 I/O PORT14 I/O PORT13 I/O PORT13 I/O PORT13 I/O I/O Group PORT14 I/O PORT15 I/O PORT14 I/O PORT14 I/O PORT13 I/O PORT14 I/O PORT14 I/O PORT14 I/O PORT13 I/O PORT13 I/O PORT13 I/O PORT15 I/O
Voltage (V) 3.3/1.8 3.3 3.3 3.3 3.3 3.3 3.3 3.3/1.8 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Rev.1.00
IO IO IO IO IO IO I/O IO IO IO IO IO IO IO IO IO IO IO List of External Pins
1
2.2- able GETXEN GETXC MTSCLK1 MTTXD1 MTRXD1 MTCS1 MTSCLK0 MTRXD0 MTTXD0 MTCS0 MTDCPLS3 MTDCPLS2 MTDCPLS1 MTDCPLS0 MTDRV7 MTDRV6 Pin Name Pin MTDRV5 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) 8 Pins 123 18 18 18 18 18 18 18 18 19 19 19 18 1 18 18 18 18 able able able able able able able able able able able able able able able able able able able T T T T T T T T T T T T T T T T T of and and and and and and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 23 Multiplexed Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T T T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* Selectable* -
ch - — — — — — — — — N Open Drain — — — — — — — — —
Input -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — — — — — Schmitt Trigger — — — — — — — — —
Pin State Pin State when not in Use Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ------Initial Value Initial Value Power after onReset Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi
18)
(11/
I/O Group PORT16 I/O PORT16 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT16 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT15 I/O PORT15 I/O
Voltage (V) 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
IO IO IO IO IO IO IO IO I/O IO IO IO IO IO IO IO IO IO List of External Pins
1
2.2- able GERXD4 GERXD3 GERXD2 GERXD0 GERXD1 GERXER GERXDV GERXC GETXD7 GETXD6 GETXD5 GETXD4 GETXD3 GETXD2 GETXD1 GETXD0 Pin Name Pin GETXER T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) ) ) ) ) ) ) ) ) ) Pins 123 19 19 19 19 19 20 19 19 19 19 19 19 able able able able able able able able able able able able able able T T T T T T T T T T T T of and and and and and and and and and and and and
2 2 2 2 2 2 2 2 2 2 2 2
------2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able - 2.2 able 24 — — — — — — — — — — — — 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed Multiplexed Pin Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin 2.2 Multiplexed (see pin T T T T T T —
Section 2 Section
2 2 2 2 2 2 2 2 2 2 2 2 2 2 Page Page
Output — — — Selectable* — — — — — — — Selectable* Selectable* Selectable* Selectable* Selectable* — Selectable* Selectable* Selectable* Drive Strength Drive / Selectable Fixed Selectable* Selectable* Selectable* Selectable* Selectable* -
ch - — — — — — — — — — — — — — — — — — — — — N Open Drain — — — — —
Input PU — — PU OFF PU PD PD PD — PU — -up/Pull -downPull PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable — PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable PU/PD/OFF changeable
— — — — — — — — — — — — — — — — Schmitt Trigger — — — — —
State State Open Open Open Open Open Open Open Open Open down Pull down Pull — Pin Pin when not in Use Open Open — Open Open Open Open Open Open Open Open Open Open -
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ------Hi Hi PU PU Hi PU Hi — PD PU PD PD — Initial Value Initial Value Power after onReset Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi
-driver
18)
(12/
LPDDR4 PHY LPDDR4 PHY DebuggerI/O DebuggerI/O DebuggerI/O DebuggerI/O I/O test LSI I/O test LSI LPDDR4 PHY PORT15,PORT16, pre PORT17 supply power DebuggerI/O PORT15,PORT16, PORT17 I/O power supply I/O Group DebuggerI/O PORT16 I/O PORT16 I/O PORT16 I/O PORT16 I/O PORT16 I/O PORT16 I/O PORT16 I/O PORT16 I/O PORT16 I/O PORT17 I/O PORT16 I/O PORT16 I/O
1.1 1.1 3.3/1.8 1.8 Voltage (V) 1.8 1.8 1.8 3.3 3.3 1.1 1.8 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 3.3/1.8 Rev.1.00
O O — I IO IO IO IO IO I/O I O IO I I I O IO — I IO IO IO IO IO IO List of External Pins
1
2.2-
able LPATEST LPCAA0 LPCAA1 DESRSTN RETEST0 RETEST1 DETDO DETMS DETRSTN DETCK DETDI GEMODVDD GEPREDVDD GEPPS GECLK GEINT GELINK GEGTXCLK GEMDIO GEMDC GECOL GECRS GERXD7 GERXD6 Pin Name Pin GERXD5 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123 of
25 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Multiplexed Multiplexed Pin
Section 2 Section Page Page
Output — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Drive Strength Drive / Selectable Fixed -
ch - — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — N Open Drain
Input — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — -up/Pull -downPull
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Schmitt Trigger
Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Pin State Pin State when not in Use -
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ------Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi L L L L Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Initial Value Initial Value Power after onReset
18)
(13/
LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY I/O Group LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY
1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 Voltage (V) 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 Rev.1.00
IO IO IO IO IO IO IO IO IO IO IO IO O O O O IO IO IO IO IO IO IO IO IO IO O O O O O O O O O O I/O IO IO IO IO IO IO O O O O O O O O List of External Pins
1
2.2- able LPDQB6 LPDQB7 LPDQB3 LPDQB4 LPDQB5 LPDQB0 LPDQB1 LPDQB2 LPDQA13 LPDQA14 LPDQA15 LPDQA9 LPDQA10 LPDQA11 LPDQA12 LPDQA6 LPDQA7 LPDQA8 LPDQA3 LPDQA4 LPDQA5 LPDQA0 LPDQA1 LPDQA2 LPDMDBIA1 LPDMDBIB0 LPDMDBIB1 LPCSB0 LPCSB1 LPDMDBIA0 LPCLKBT LPCSA0 LPCSA1 LPCLKAC LPCLKAT LPCLKBC LPCKEA1 LPCKEB0 LPCKEB1 LPCAB4 LPCAB5 LPCKEA0 LPCAB0 LPCAB1 LPCAB2 LPCAB3 LPCAA3 LPCAA4 LPCAA5 Pin Name Pin LPCAA2 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123
of
26 — — — — — — — — — — — — — — — — — — — — — — — — MPRXCK1M MPRXD0P MPRXD0M MPRXD1P MPRXD1M MPRXD2P MPRXD2M MPRXD3P MPRXD3M MPRXCK0P MPRXCK0M MPRXD4P MPRXD4M MPRXD5P MPRXD5M MPRXD6P MPRXD6M MPRXD7P MPRXD7M MPRXCK1P Multiplexed Multiplexed Pin — —
Section 2 Section Page Page
Output — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Drive Strength Drive / Selectable Fixed — — -
ch - — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — N Open Drain — —
Input — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — -up/Pull -downPull — —
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Schmitt Trigger — —
down down down down down down down down down down down down down down down down down down down down
l down Pull Pull Pull — — — Pull Pull Pull Pull Pull Pull Pul Pull Pull Pull Pull Pull Pull Pull Pull (10KΩ) Open Open Open Pull Pull Pull Pull Open Open — Open Open Open Open Open Open Open Open Open Open Open Open Open Open Pin State Pin State when not in Use — — -
Value
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ------— Hi Hi — — L Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi — Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Initial Power after onReset — — V V - -V
V power V power V power
- -
18)
(14/
PHY
power supply power CIF PHY CIF PHY LPDDR4 PLL 1.8 LPDDR4 PLL supply power LPDDR4core - 0.8 supply power LPDDR4 PHY 1.1 LPDDR4 PHY CIF PHY CIF PHY CIF PHY CIF PHY CIF PHY 1.8 PHY CIF 0.8 PHY CIF CIF PHYGND CIF PHY CIF PHY CIF PHY CIF PHY CIF PHY CIF PHY CIF PHY CIF PHY CIF PHY LPDDR4 PHY LPDDR4 PHY CIF CIF PHY CIF PHY CIF PHY CIF PHY LPDDR4 PHY LPDDR4 PHY supply supply I/O Group LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY LPDDR4 PHY
1.8 1.8 1.8 0.8 1.1 1.1 Voltage (V) 1.8 1.8 1.8 1.8 1.8 1.8 0.8 0 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.1 1.1 1.8 1.8 1.8 1.8 1.8 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 Rev.1.00
I I — — — O IO IO I/O I I I I I — — — I I I I I I I I I IO IO O O I I I I I IO IO IO IO IO IO IO IO IO IO IO IO List of External Pins
1
2.2-
able LVRXAVSS LVRXAVCC LVRXAVDD LVRXCK1P LVRXCK1M LVRXREXT LVRXD6M LVRXD7P LVRXD7M LVRXD5P LVRXD5M LVRXD6P LVRXCK0P LVRXCK0M LVRXD4P LVRXD4M LVRXD2M LVRXD3P LVRXD3M LVRXD1P LVRXD1M LVRXD2P LPDTEST LVRXD0P LVRXD0M LPVDD LPVDDQ LPZN LPVAA LPDQSBT0 LPDQSBT1 LPMRESETL LPDQSAT1 LPDQSBC0 LPDQSBC1 LPDQSAC0 LPDQSAC1 LPDQSAT0 LPDQB12 LPDQB13 LPDQB14 LPDQB15 LPDQB9 LPDQB10 LPDQB11 Pin Name Pin LPDQB8 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123 of
27 — — — — — — — — — — — — — — — — — — — — — — — — — Multiplexed Multiplexed Pin — — — — — — — — — — — — — — — — — —
Section 2 Section
2 Page Page
Output — — — — — — — — — — — — — — — — — — — — Selectable* — — — — — — — — — — — — — — — — — — — — — Drive Strength Drive / Selectable Fixed — -
ch - — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — N Open Drain —
Input — — — — — — — — — — — — — — — — — — — — OFF - — — — -up/Pull -downPull — — — — — - — — — — — — — — — — — —
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Schmitt Trigger — —
down down down down
Open — — Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open — — Open Open Pull Pull Pull Pull Pin State Pin State when not in Use Open (external not capacitor required) Open Open — — — Open Open Open Open Open Open Open Open Open Open Pull — -
Z Z Z Z Z - - - - -
— — Hi — — — X — X — — — CLOCK — — — H L — X CLOCK X — L L Hi Hi — — — L L L L L L L L L Hi L Initial Value Initial Value Power after onReset — Hi
section section -V -V
PHY
18)
Tx PHY
(15/ power supply power supply power power supply power
-V -V -V power supply supply power -V -V V power supply power -V
1.8 0.8 USB PHY HS PHY USB HS PHY USB USB PHY USB PHY PCIe PHY PCIe PCIe PHY PCIe PHY PCIe PHY PCIe PHY PCIe USB PHY USB PHY USB PHY PCIe PHY PCIe PHY PCIe PCIe PHY 0.8 supply power PCIe PHY 1.8 supply power PCIeI/O USB PHY MIPIDSI Tx PHY 1.8 MIPIDSI Tx PHY 1.2 MIPIDSI Tx PHY 0.8 PHY PCIe PHY PCIe PHY PCIe PHY PCIe USB PHY HS section section HS PHY USB 3.3 I/O Group USB RESREF USB PHY MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI Tx PHY MIPIDSI Tx MIPIDSI Tx PHY MIPIDSI Tx PHY
1.8 0.8 3.3 0.8 1.8 1.8 1.8 1.8 1.8 Voltage (V) 0.25 3.3 0.8 0.8 0.8 1.8 1.8 0.8 1.8 3.3 3.3 1.8 1.2 0.8 1.8 1.8 1.8 1.8 3.3 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Rev.1.00
— — I O I IO I O I O I/O I — I I O I I — — O IO IO IO — — — I O I O IO IO IO IO IO IO IO IO IO IO IO IO IO List of External Pins
1
2.2-
able USTX0M USTX0P USVBUS USRX0M USRX0P USVDDH USDVDD USDM USRESREF USVD330 PCRSTOUTB USDP PCTXD1M PCVDD08 PCVDD18 PCRXD1P PCRXD1M PCTXD1P PCREFCKP PCREFCKM PCREXT PCRXD0M PCTXD0P PCTXD0M DSMSVDD0P8 PCRXD0P DSMSVDD18 DSMVDD12 DSSDNDATA0 DSSDPCLK DSSDNCLK DSSDPDATA0 DSMDPCLK DSMDNCLK DSMVREG0P4V DSMDPDATA2 DSMDNDATA2 DSMDPDATA3 DSMDNDATA3 DSMDNDATA0 DSMDPDATA1 DSMDNDATA1 Pin Name Pin DSMDPDATA0 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
) ) ) Pins 123 21 21 21 able able able able T T T of and and and
2 2 2
- - - - 2.2 able - 2.2 able - 2.2 able 28 — — — — — — — — — — — — — — — Multiplexed Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed (see pin 2.2 T Multiplexed Multiplexed Pin — — — — — — — — — — — — — — — — — — — — — —
Section 2 Section
2 2 2 2 Page Page
Output — — — — — — — — — — — — Selectable* Selectable* Selectable* — — — — — — — — — — — — — Selectable* — — — — — — — — — — — Drive Strength Drive / Selectable Fixed -
ch - — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — N Open Drain
Input — — — — — — — — — — — — OFF OFF OFF — OFF -up/Pull -downPull — — — — — — — — — — — OFF — — — — — — — — — — —
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Schmitt Trigger
not in
Open Open Open Open Open Open Open Open — Open — — Open up Pull Pin State Pin State when Use Pull down Pull down Pull down Pull — down Pull down Pull down Pull down Pull down Pull down Pull — Open Open Open Open down Pull down Pull down Pull down Pull down Pull down Pull down Pull down Pull down Pull — — -
Z Z Z Z Z Z Z Z Z Z Z Z ------Hi Hi Hi Hi — — — — — Hi Hi Hi Hi — — — — — — — — — — — — — — — — — — — — L Hi — — Initial Value Initial Value Power after onReset Hi Hi Hi
-V -V section section section section
18)
V power V power -
I/O I/O (16/
power supply power power supply power
PHY SS PHY
-V -V
HDMI PHY HDMI PHY HDMI PHY HDMI PHY ADCAI/O ADCAI/O 1.8ADCA GND ADCA ADCAI/O ADCAI/O ADCA ADCAI/O ADCAI/O ADCAI/O ADCAI/O ADCAI/O ADCAI/O ADCAI/O ADCAI/O ADCA ADCAI/O ADCAI/O ADCAI/O ADCAI/O supply HDMI PHY HDMI PHY 1.8 supply power HDMI PHY 0.8 supply power USB PHY SS USB PHY 0.8 section SS USB PHY power transmitter supply I/O USB I/O USB HDMI PHY HDMI PHY HDMI PHY HDMI PHY USB 3.3 I/O Group PORT20 I/O PORT20 I/O PORT20 I/O
1.8 1.8 1.8 1.8 Voltage (V) 1.8 1.8 1.8 0 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.8 1.8 0.8 0.8 3.3 3.3 1.8 1.8 1.8 1.8 3.3 1.8 1.8 1.8 Rev.1.00
IO O O O O I/O I I — — I I I I I I IO I I I I I I I I I I — — IO IO I — — O I O O O O — List of External Pins
1
2.2-
able AD1AIN4 AD1AIN5 AD1AIN0 AD1AIN1 AD1AIN2 AD1AIN3 AD0AVCCA AD0AVSSA AD0AIN9 AD0AIN10 AD0AIN11 AD0AIN6 AD0AIN7 AD0AIN8 AD0AIN3 AD0AIN4 AD0AIN5 AD0AIN0 AD0AIN1 AD0AIN2 HDHPD HDSDA HDSCL HDREXT HDAVDD18 HDAVDD08 HDTX1M HDTX2P HDTX2M HDTX0P HDTX0M HDTX1P USOVC HDTXCP HDTXCM USVPTX USPWEN USVP USVPH Pin Name Pin USOTGID T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
-2 Pins 123
) able of T
-22 able 2.2 29 — — — — — — — — — — Multiplexed Multiplexed pin (see T Multiplexed Multiplexed Pin — — — — — — — — — — — — — — — — — — — — — and 2.2
Section 2 Section
2 Page Page
Output — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Selectable* Drive Strength Drive / Selectable Fixed -
ch - — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — N Open Drain
Input PU OFF OFF OFF OFF PD PD OFF OFF — -up/Pull -downPull — — — — — — — — — — — — — — — — — — — — — OFF
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Schmitt Trigger
Always in in Always use Always in in Always use in Always use in Always use in Always use in Always use in Always use in Always use Always in in Always use — Pin State Pin State when not in Use Always in in Always use — — — — — — — — — — — — — — in Always use — — Pull down Pull down Pull — in Always use -
Z Z Z Z Z Z Z ------PU Hi Hi Hi PD PD Hi Hi — Hi — — — — — — — — CLOCK — — — — — — — — CLOCK — — — Initial Value Initial Value Power after onReset Hi
-V -V -V -V -V -V -V -V -V
.8 .8 18) power power
V power V power 0 0
-
0 1.8 0 1 1.8 1 -V -V 1 GND 2 GND 3 1.8 3 GND 4 1.8 4 GND 6 1.8 1 1.8 2 1.8 . . . . I/O (17/
h h h h
. h. h. h. h. h. h. h. . h. h. c c c c -0 I/O -0 I/O -0 I/O -0 I/O -0 I/O -0 I/O -0 I/O -0 c c c c c c c c c
-V OSC -V OSC
MD7 MD7 MD7 MD7 MD7 MD7 MD7 MD7 PLL ch. 6 GND ch. 6 PLL PLL PLL PLL PLL PLL PLL PLL 1.8 I/O RSTN PLL PLL OTP 1.8 OTP 0.8 TSU TSU TSU TSU 1.8 supply supply ADCAI/O ADCAI/O 1.8ADCA GND ADCA supply I/O Group power supply power supply power supply power power supply power supply power supply power supply power supply power supply power PORT21 I/O
1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Voltage (V) 0 0 0 1.8 0 1.8 0 1.8 1.8 1.8 1.8 1.8 1.8 0.8 1.8 0.8 1.8 0.8 1.8 3.3/1.8 1.8 1.8 1.8 0 Rev.1.00
I I I I I I IO I I I/O — — — — — — — — O I — — — — — — — — I I I — — List of External Pins
1
2.2-
able PLVSS6 PLVSS4 PLVDD6 PLVDD3 PLVSS3 PLVDD4 PLVDD2 PLVSS2 PLVDD1 PLVSS1 XOUT RSTN TS1DVDD08A XIN TS0DVDD08A TS1AVDD18 OTVDD08 TS0AVDD18 OTVDD18 MD8 MD6 MD7 MD4 MD5 MD2 MD3 MD0 MD1 AD1AIN7 AD1AVCCA AD1AVSSA Pin Name Pin AD1AIN6
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123 of
30 — — — — — — — — — — — — Multiplexed Multiplexed Pin —
Section 2 Section Page Page
Output — — — — — — — — — — — — — Drive Strength Drive / Selectable Fixed -
ch - — — — — — — — — — — — — — N Open Drain
Input — — — — — — — — — — — — -up/Pull -downPull —
— — — — — — — — — — — — — Schmitt Trigger
— — — — — — — — — — — — Pin State Pin State when not in Use — -
— — — — — — — — — — — — — Initial Value Initial Value Power after onReset tandard I/O Characteristics.
V power 18)
-7 I/O) (18/
-V OSC,
-driverpower MD0 LSI testI/O) debugger I/O, I/O, debugger USB I/O, I/O, USB LSI testI/O) RSTNI/O, PORT13I/O, PORT14I/O, PCIeI/O, I/O, USB PORT05I/O, PORT20I/O. 1.8 PORT13I/O, PORT14I/O, PCIeI/O,
(PORT12 I/O, I/O, (PORT12
(PORT02 I/O, I/O, (PORT02 (PORT12 I/O, I/O, (PORT12
I/Osupply power
I/Osupply power VDD33 group VDD33 pre supply VDD08 0.8VDD08 - supply group VDD18 VDD33 group VDD33 GND PLL ch. 7 GND ch. 7 PLL -V 0.8 ch. 2 PLL supply power -V 0.8 ch. 3 PLL supply power -V 0.8 ch. 4 PLL supply power -V 0.8 ch. 6 PLL supply power -V 0.8 ch. 7 PLL supply power -V 1.8 ch. 7 PLL supply power -V 0.8 ch. 1 PLL supply power I/O Group
3.3 0.8 1.8 Voltage (V) 1.8 0 0 0.8 0.8 0.8 0.8 0.8 1.8 0.8 Rev.1.00
— — — I/O — — — — — — — — — — V input tolerant List of External Pins -
1 For 3.3 For the For drive strength, see Section, S 4.4.2
2.2-
able GND PREDVDD33 VDD33 VDD18 PLDVDD087 VDD08 PLDVDD084 PLDVDD086 PLDVDD082 PLDVDD083 PLVSS7 PLDVDD081 Pin Name Pin PLVDD7
Note 1. Note 2. T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123
of
31 — — — — Share Group 7 — — — — — — — — — — ESI — — — ESI — Section 2 Section Page Page
— — — — Share Group 6 — — — — — — — — — — — — — — — —
— — — — Share Group 5 — — — — — — — — — — — — — — — —
— — — — Share Group 4 TRACE TRACE — — — — TRACE — — — — — — — — TRACE
— — — — Share Group 3 — MTR — — — — CSI0 CSI1 CSI2 — — — — MTR MTR Timer/ CLK out — —
— Ex. interrupt Ex. interrupt Ex. interrupt Share Group 2 — Ex. interrupt Ex. interrupt — — — — UART1 IIC2 IIC3 CSI3 IIC0 IIC1 — — Ex. interrupt eMMC Ex. interrupt Ex. interrupt UART0 CSI4 CSI5
Share Group 1 — — ETHER ETHER ETHER HDMI — — — I2S SDI0 SDI1 STG0 STG1 Mechanical shutter NAND PWM — CSI0 CSI1 CSI2 CSI3 CSI4 CSI5
Rev.1.00
List of Multiplexed Functional Blocks Share Group 0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
List Multiplexedof Blocks Functional
2
2.2- able PORT21 PORT16 PORT17 PORT20 PORT13 PORT14 PORT15 PORT11 PORT12 PORT09 PORT10 PORT06 PORT07 PORT08 PORT05 PORT04 PORT03 PORT01 PORT02 I/O Group I/O PORT00
2.2.2 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123
of
32 — — — — — — SDTCS2 SDTCS3 — — — — — — — — — — — Share Pin Share Pin Name7 ESI Share Pin Share Pin Name7 — — — — — — SDTCS1 — — — — — Section 2 Section Page Page — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name6 — Share Pin Share Pin Name6 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name5 — Share Pin Share Pin Name5 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name4 — Share Pin Share Pin Name4 — — — — — — — — — — — —
out — — — — — — GFPLS1 GMCLK0 GMCLK1 — — — — — — — Share Pin Share Pin Name3 Timer/ CLK Share Pin Share Pin Name3 — — — — — — — GFPLS0 GMCLK0 GMCLK1 — — — — —
INEXINT20 INEXINT21 INEXINT22 INEXINT23 INEXINT18 INEXINT19 MMDAT5 MMDAT6 MMDAT7 MMCLK — MMDAT0 MMDAT1 MMDAT2 MMDAT3 MMDAT4 Share Pin Share Pin Name2 interrupt Ex. Share Pin Share Pin Name2 eMMC INEXINT14 INEXINT15 INEXINT16 INEXINT17 INEXINT8 INEXINT9 INEXINT10 INEXINT11 INEXINT12 INEXINT13 MMCMD — — —
in the Multiplexed Mode in the Multiplexed Mode
PM12 PM13 PM14 PM15 PM10 PM11 NADAT5 NADAT6 NADAT7 NACLE NADAT0 NADAT1 NADAT2 NADAT3 NADAT4 Share Pin Share Pin Name1 PWM Share Pin Share Pin Name1 NAND PM6 PM7 PM8 PM9 PM0 PM1 PM2 PM3 PM4 PM5 NAWEN NAALE NARBN NACEN NAREN PORT01
Rev.1.00
P01_12 P01_13 P01_14 P01_15 P01_10 P01_11 P00_11 P00_05 P00_06 P00_07 P00_02 P00_03 P00_04 P00_00 P00_01 Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO P01_06 P01_07 P01_08 P01_09 P01_00 P01_01 P01_02 P01_03 P01_04 P01_05 P00_10 P00_12 P00_13 P00_08 P00_09 I/O Group Group I/O I/O Group PORT00 Group I/O
4 3
2.2- 2.2-
able able PM14 PM15 PM12 PM13 PM9 PM10 PM11 PM6 PM7 PM8 PM4 PM5 PM1 PM2 PM3 External Pin Pin External Name PM0 NARBN NAWEN NACLE NAALE NADAT7 NACEN NAREN NADAT5 NADAT6 NADAT2 NADAT3 NADAT4 Name NADAT0 NADAT1 External Pin Pin External
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Pins 123
of
33 — — — — — — — — SDTTXD SDTRXD SDTSCLK SDTCS0 — — — — — — — — — — — — Share Pin Share Pin Name7 — Share Pin Share Pin Name7 — Share Pin Name7 ESI — — — — — — — — Section 2 Section Page Page — — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name6 — Share Pin Share Pin Name6 — Share Pin Name6 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name5 — Share Pin Share Pin Name5 — Share Pin Name5 — — — — — — — — —
TRDAT3 TRCLK — — TRDAT13 TRDAT12 TRDAT11 TRDAT10 TRDAT9 TRDAT8 TRDAT7 TRDAT6 TRDAT5 TRDAT4 TRDAT2 TRDAT1 TRDAT0 TRCTL — — — — TRDAT15 TRDAT14 Share Pin Share Pin Name4 TRACE Share Pin Share Pin Name4 — Share Pin Name4 TRACE — — — — — — — —
,
SI1 C
,
— — — — — — — — — — — — — — — CSRXD0 — — — CSRXD1 — — — CSRXD2 Share Pin Share Pin Name3 — Share Pin Share Pin Name3 — Share Pin Name3 CSI0 CSI2 — — — — — — — — , ,
IIC2
SI5
, , SI3 C
C , ART1 IC3, IC3, — — I2SCL3 CSRXD3 — — CSRXD4 — — CSRXD5 — — UACTS0N UACTS1N I2SCL2 I2SDA3 — UATX0 UARX0 UARTS0N UATX1 UARX1 UARTS1N I2SDA2 Share Pin Share Pin Name2 CSI4 Name2 UART0 U I Share Pin Share Pin Share Pin Share Pin Name2 interrupt Ex. INEXINT0 INEXINT1 INEXINT2 INEXINT3 INEXINT4 INEXINT5 INEXINT6 INEXINT7
,
SI5 SI1 SI3 in the Multiplexed Mode in the Multiplexed Mode in the Multiplexed Mode
Pin C C C
, , ,
CSRXD4 CSSCLK4 CSCS4 CSTXD5 CSRXD5 CSSCLK5 CSCS5 CSRXD2 CSCS2 CSTXD3 CSRXD3 CSSCLK3 CSCS3 CSTXD4 CSRXD0 CSSCLK0 CSCS0 CSTXD1 CSRXD1 CSSCLK1 CSCS1 CSTXD2 CSSCLK2 CSTXD0 Share Pin Share Pin Name1 CSI4 Name1 CSI0 CSI2 Share Pin Share Pin Share Name1 — — — — — — — — — PORT04 PORT03 PORT02
Rev.1.00
P04_06 P04_07 P04_01 P04_02 P04_03 P04_04 P04_05 P03_15 P04_00 P03_09 P03_11 P03_12 P03_13 P03_14 P03_06 P03_07 P03_10 P03_01 P03_02 P03_03 P03_04 P03_05 P03_08 P03_00 Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO P02_07 P02_05 P02_06 P02_00 P02_01 P02_02 P02_03 P02_04 I/O Group Group I/O I/O Group Group I/O I/O Group Group I/O
7 6 5
2.2- 2.2- 2.2- able able able CSCS5 CSTXD5 CSRXD5 CSSCLK5 CSSCLK4 CSCS4 Name CSTXD4 CSRXD4 External Pin Pin External CSCS3 CSTXD3 CSRXD3 CSSCLK3 CSRXD2 CSSCLK2 CSCS2 CSCS1 CSTXD2 CSTXD1 CSRXD1 CSSCLK1 CSRXD0 CSSCLK0 CSCS0 External Pin Pin External Name CSTXD0 INEXINT7 INEXINT5 INEXINT6 INEXINT2 INEXINT3 INEXINT4 Name INEXINT0 INEXINT1 External Pin Pin External
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Pins 123 of 34 — — — — — — — — Share Pin Share Pin Name7 — Share Pin Share Pin Name7 — Share Pin Name7 — — — — — — — — — — — — — — — Section 2 Section Page Page — — — — — — — — Share Pin Share Pin Name6 — Share Pin Share Pin Name6 — Share Pin Name6 — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name5 — Share Pin Share Pin Name5 — Share Pin Name5 — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name4 — Share Pin Share Pin Name4 — Share Pin Name4 — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name3 — Share Pin Share Pin Name3 — Share Pin Name3 — — — — — — — — — — — — — — —
IIC1 — — — — I2SDA0 I2SDA1 I2SCL1 I2SCL0 Share Pin Share Pin Name2 — Share Pin Share Pin Name2 — Share Pin Share Pin Name2 IIC0, — — — — — — — — — — — — — —
in the Multiplexed Mode in the Multiplexed Mode in the Multiplexed Mode
AULRCK AUDI AUMCLK AUPLLCLK — — — — Share Pin Share Pin Name1 AUI Share Pin Share Pin Name1 — Share Pin Share Pin Name1 — AUBICK AUDO — — — — — — — — — — — — PORT05 PORT06 PORT07
Rev.1.00
Pin
P07_04 P07_05 P07_00 P07_02 P05_00 P05_02 P05_03 P05_01 GPIO Share Pin Share Pin Name0 Share Pin Share Pin Name0 GPIO Share Name0 GPIO P07_03 P07_01 P06_09 P06_10 P06_11 P06_01 P06_02 P06_03 P06_04 P06_05 P06_06 P06_07 P06_08 P06_00 I/O Group Group I/O I/O Group Group I/O I/O Group Group I/O
10 9 8
2.2- 2.2- 2.2-
able able able AUPLLCLK AUDO AUMCLK AULRCK AUBICK AUDI External Pin Pin External Name P0609 P0610 P0611 P0606 P0607 P0608 P0604 P0605 P0601 P0602 P0603 External Pin Pin External Name P0600 I2SDA1 I2SCL1 Name I2SDA0 I2SCL0 External Pin Pin External
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Pins 123 of 35 — — — — — — — — — — — — — — — — Share Pin Share Pin Name7 — Share Pin Share Pin Name7 — Share Pin Name7 — — — — — — — — — — Section 2 Section Page Page — — — — — — — — — — — — — — — — Share Pin Share Pin Name6 — Share Pin Share Pin Name6 — Share Pin Name6 — — — — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name5 — Share Pin Share Pin Name5 — Share Pin Name5 — — — — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name4 — Share Pin Share Pin Name4 — Share Pin Name4 — — — — — — — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name3 — Share Pin Share Pin Name3 — Share Pin Name3 — — — — — — — — — —
— — INEXINT26 INEXINT27 — — — — — — — INEXINT24 — — — — Share Pin Share Pin Name2 interrupt Ex. Name2 interrupt Ex. Share Pin Share Pin Share Pin Share Pin Name2 — INEXINT25 — — — — — — — —
in the Multiplexed Mode in the Multiplexed Mode in the Multiplexed Mode
IM0SIG2 IM0SCLK IM0SIG0 IM0SIG1 SD1FDAT0 SD1FDAT1 SD1FDAT2 SD1FDAT3 SD1FWP SD0DAT3 SD0WP SD1FCMD SD0CMD SD0DAT0 SD0DAT1 SD0DAT2 Share Pin Share Pin Name1 STG0 Name1 SDI1 Share Pin Share Pin Share Pin Share Pin Name1 SDI0 IM0TXD SD1FCD IM0VS IM0HS IM0CS IM0RXD SD0CD SD1FCLK SD0CLK PORT09 PORT10 PORT08
Rev.1.00
P10_08 P10_05 P10_06 P10_07 P09_05 P09_02 P09_03 P09_04 P09_06 P09_00 P08_05 P08_06 P08_00 P08_02 P08_03 P08_04 GPIO Share Pin Share Pin Name0 Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO P10_03 P10_00 P10_01 P10_02 P10_04 P09_07 P08_07 P09_01 P08_01 I/O Group Group I/O I/O Group Group I/O I/O Group Group I/O
13 12 11
2.2- 2.2- 2.2-
able able able IM0SIG2 IM0SCLK IM0SIG0 IM0SIG1 IM0TXD IM0RXD IM0VS IM0HS IM0CS External Pin Pin External Name SD1FDAT3 SD1FWP SD1FCD SD1FDAT0 SD1FDAT1 SD1FDAT2 SD1FCMD SD1FCLK External Pin Pin External Name SD0CD SD0DAT3 SD0WP SD0DAT0 SD0DAT1 SD0DAT2 Name SD0CMD SD0CLK External Pin Pin External
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Pins 123 of 36 — — — — — — — — Share Pin Share Pin Name7 — — — — — — — — — Share Pin Share Pin Name7 — Share Pin Name7 — — — — — — — — — — Section 2 Section Page Page — — — — — — — — Share Pin Share Pin Name6 — — — — — — — — — Share Pin Share Pin Name6 — Share Pin Name6 — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name5 — — — — — — — — — Share Pin Share Pin Name5 — Share Pin Name5 — — — — — — — — — —
— — — — Share Pin Share Pin Name4 — Share Pin Name4 — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name4 — — — — —
— — — — Share Pin Share Pin Name3 — Share Pin Name3 — — — — — — — — — — MTDRV0 MTDRV1 MTDRV2 MTDRV3 MTDRV4 MTDRV5 MTDRV6 MTDRV7 Share Pin Share Pin Name3 MTR MTDCPLS0 MTDCPLS1 MTDCPLS2 MTDCPLS3
— INEXINT28 INEXINT29 — Share Pin Share Pin Name2 interrupt Ex. Share Pin Share Pin Name2 interrupt Ex. INEXINT31 INEXINT32 INEXINT33 — — INEXINT30 — — — — — — — — — — — Ex. interrupt Ex. Share Pin Share Pin Name2 — INEXINT34 INEXINT35 INEXINT36
in the Multiplexed Mode in the Multiplexed Mode in the Multiplexed Mode
IM1SCLK IM1SIG0 IM1SIG1 IM1SIG2 Share Pin Share Pin Name1 STG1 Share Pin Share Pin Name1 STG1 IMSHUT1 IMSHUT0 IMSTSIG0 IMSTSIG1 IM1VS IM1HS IM1CS IM1TXD IM1RXD — — — — — — — — — Share Pin Share Pin Name1 — — — — PORT12 PORT13 PORT11
Rev.1.00
P13_00 P13_01 P13_02 P13_03 P13_04 P13_05 P13_06 P13_07 P11_05 P11_06 P11_07 P11_08 Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO P13_08 P13_09 P13_10 P13_11 P12_01 P12_02 P12_03 P12_00 P11_02 P11_03 P11_00 P11_01 P11_04 I/O Group Group I/O I/O Group Group I/O I/O Group Group I/O
16 15 14
2.2- 2.2- 2.2-
able able able MTDCPLS3 MTDCPLS0 MTDCPLS1 MTDCPLS2 MTDRV6 MTDRV7 MTDRV3 MTDRV4 MTDRV5 MTDRV0 MTDRV1 MTDRV2 External Pin Pin External Name IMSHUT1 IMSTSIG0 IMSTSIG1 External Pin Pin External Name IMSHUT0 IM1SIG1 IM1SIG2 IM1SCLK IM1SIG0 IM1CS IM1TXD IM1RXD Name IM1VS IM1HS External Pin Pin External
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Pins 123
2 of
37 — — — — Share Pin Share Pin Name7 — — — — — — — — — — — — — Share Pin Share Pin Name7 — — — — — — — — — Section Page Page — — — — Share Pin Share Pin Name6 — — — — — — — — — — — — — Share Pin Share Pin Name6 — — — — — — — — — — — — — Share Pin Share Pin Name5 — — — — — — — — — — — — — Share Pin Share Pin Name5 — — — — — — — — —
TRDAT6 TRDAT7 TRCTL — TRCLK TRDAT3 TRDAT4 TRDAT5 Share Pin Share Pin Name4 TRACE — — — — — TRDAT0 TRDAT1 TRDAT2 — — — — Share Pin Share Pin Name4 — — — — —
— — — — — — — — Share Pin Share Pin Name3 — — — — — — — — — MTRXD0 MTRXD1 MTCS0 MTCS1 Share Pin Share Pin Name3 MTR MTTXD0 MTSCLK0 MTTXD1 MTSCLK1
— — — — — — — — Name2 — Share Pin Share Pin — — — — — — — — INEXINT37 INEXINT38 — — Share Pin Share Pin Name2 interrupt Ex. — — — —
in the Multiplexed Mode in the Multiplexed Mode
Pin
GERXC GERXDV GERXER GERXD0 GERXD1 GETXC GETXEN GETXER Name1 ETHER Share GETXD2 GETXD3 GETXD4 GETXD5 GETXD6 GETXD7 GETXD0 GETXD1 — — — — Share Pin Share Pin Name1 — — — — — PORT15 PORT14
Rev.1.00
P15_11 P15_12 P15_13 P15_14 P15_15 P15_00 P15_01 P15_02 P14_02 P14_06 P14_04 P14_00 Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO P15_10 P15_05 P15_06 P15_07 P15_08 P15_09 P15_03 P15_04 P14_07 P14_05 P14_01 P14_03 I/O Group Group I/O I/O Group Group I/O
18 17
2.2- 2.2- able able GERXER GERXD0 GERXD1 GETXD7 GERXC GERXDV GETXD5 GETXD6 GETXD2 GETXD3 GETXD4 GETXER GETXD0 GETXD1 GETXC GETXEN External Pin Pin External Name MTSCLK1 MTTXD1 MTRXD1 MTRXD0 MTSCLK0 MTCS1 Name MTCS0 MTTXD0 External Pin Pin External
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Pins 123 of 38 — — — — — — — — — — — — — Share Pin Share Pin Name7 — Share Pin Name7 — Share Pin Name7 — Share Pin Share Pin Name7 — — — — — — — Section 2 Section Page Page — — — — — — — — — — — — — Share Pin Share Pin Name6 — Share Pin Name6 — Share Pin Name6 — Share Pin Share Pin Name6 — — — — — — — — — — — — — — — — — — — — Share Pin Share Pin Name5 — Share Pin Name5 — Share Pin Name5 — Share Pin Share Pin Name5 — — — — — — —
TRDAT8 TRDAT9 TRDAT10 TRDAT11 TRDAT12 TRDAT13 — — TRDAT14 — — — — Share Pin Share Pin Name4 — Share Pin Name4 — Share Pin Name4 — Share Pin Share Pin Name4 TRACE — — TRDAT15 — — —
MTDRV10 MTDRV11 MTDRV12 MTDRV13 MTDRV8 MTDRV9 — — MTDRV14 — — — — Share Pin Share Pin Name3 — Share Pin Name3 — Share Pin Name3 — Share Pin Share Pin Name3 MTR — — MTDRV15 — — — — — — — — — — — — — — — — Share Pin Share Pin Name2 — Share Pin Name2 — Share Pin Share Pin Name2 — Share Pin Share Pin Name2 — — — — — — —
in the Multiplexed Mode in the Multiplexed Mode in the Multiplexed Mode in the Multiplexed Mode
HDHPD GECLK GEPPS GERXD4 GERXD5 GERXD6 GERXD7 GECRS GEMDC GEMDIO GEINT GERXD2 GERXD3 — Share Pin Share Pin Name1 HDMI Share Pin Name1 — Share Pin Share Pin Name1 ETHER Share Pin Share Pin Name1 ETHER HDSCL HDSDA GEGTXCLK GELINK GECOL PORT21 PORT17 PORT20 PORT16
Rev.1.00
P20_02 P16_13 P17_00 P16_02 P16_03 P16_04 P16_05 P16_06 P16_08 P16_09 P16_12 P16_00 P16_01 Share Pin Share Pin Name0 GPIO P21_00 Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO Share Pin Share Pin Name0 GPIO P20_01 P20_00 P16_10 P16_11 P16_07 I/O Group Group I/O I/O Group Group I/O I/O Group Group I/O I/O Group Group I/O
22 21 20 19
2.2- 2.2- 2.2- 2.2-
able able able able External Pin Pin External Name MD8 HDSDA HDHPD External Pin Pin External Name HDSCL Name GEPPS External Pin Pin External GECLK GEGTXCLK GELINK GEINT GECOL GEMDC GEMDIO GERXD7 GECRS GERXD4 GERXD5 GERXD6 Name GERXD2 GERXD3 External Pin Pin External
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Pins 123
of 39 Section 2 Section Page Page
circuit.
circuit. circuit. V power supply
1
kHzcrystal resonator kHzcrystal resonator
V power supply.*
NAND flash address latch enable Reserved, pulled up by a 1.8- System reset output. Connected to the RSTN pin to use the power control function of PWC. PWC SDI0 interface supply power selection PWC SDI1 interface supply power selection LSI test pin: leave this pin open- LSI test pin: fixed to the high level.(pulled up by the PWVDD) NAND flash command latch enable eMMC data [7:0] To connectTo a 32.768 - resetRTC input (active low) PWC reset input (active low) eMMC clock eMMC command Function External interrupt Enable signal pin output controlling for the LPVDD supply power on/off NAND flash read enable (active low) NAND flash write enable (active low) NAND flash ready/busy input NAND flash write protect To connectTo a 32.768 - isolationRTC input pin LSI test pin, fixed to the low level Battery voltage detection Input power key 2 to 0 (active low) Input power key 4, 3 Power enable 5 to 0 (active high) Reserved, leave these pins open- Reserved, leave this pin open- separationRTC output pin. Open drain output. Connected to the RTISO pin and pulled up (with 10kΩ to 100kΩ) to a 1.5- NAND flash chip enable (active low) PWM output NAND flash data I/O [7:0]
O I/O I O O O O I O I I I O I/O I/O I O O O I O O I I I I I O O O O O I/O O
)
7 / 1
, PWOUT0 , PWKY3N
to MMDAT0
Rev.1.00
INEXINT38 to INEXINT0 NAALE NARBN NAWPN MMDAT7 PWSD0SEL PWSD1SEL PWCTEST0 PWCTEST1 PWMEMSWIENA PWISO NAREN NAWEN NACLE PWKY2N to PWKY0N to PWKY2N PWKY4N PWDETRSTN PWEN5 to PWEN0 PWSYSRSTN PWOUT1 PWPWM RTXIN RTXOUT RTRSTN RTISO PWRSTN PWTEST PWVBAT MMCMD MMCLK NACEN Pin Name NADAT7 to NADAT0 PM15 to PM0
List of Pin Functions (
(RTC) PWC) (
Pin Functions of Functional Blocks 1
width 2.3-
able modulation timer (PWM) External interrupt Pulse- eMMC interface (eMMC)
NAND flash interface (NAND)
Power control
Classification Real time clock
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Pins 123 of 40 Section 2 Section Page Page
UART0 reception data UART0 transmission enable signal (active low) UART0 reception enable signal (active low) UART1 reception data UART1 transmission enable signal (active low) UART1 reception enable signal (active low) CSI2 serial data input CSI3 serial data output CSI3 serial data input CSI4 serial data output CSI4 serial data input CSI4 serial chip select CSI5 serial data output CSI5 serial data input CSI5 serial chip select IIC1 serial data IIC2 serial data IIC3 serial data IIC3 serial clock CSI0 serial data output CSI0 serial input data CSI0 serial chip select CSI1 serial data output CSI1 serial input data CSI1 serial chip select CSI2 serial data output CSI2 serial chip select CSI3 serial chip select IIC0 serial clock IIC1 serial clock IIC2 serial clock Function UART1 transmission data CSI4 serial clock CSI5 serial clock CSI0 serial clock CSI1 serial clock CSI2 serial clock CSI3 serial clock UART0 transmission data IIC0 serial data
I/O I/O I/O I/O I I O I I O I O I O I I O I I I/O I/O I/O O I I O I I O I I I/O I/O I/O O I/O I/O I/O I/O O I/O
) 7 / 2
Rev.1.00
I2SDA3 I2SDA1 I2SDA2 UACTS1N UARTS1N I2SCL3 UARX0 UACTS0N UARTS0N UATX1 UARX1 CSRXD4 CSSCLK4 CSCS4 CSRXD5 CSSCLK5 CSCS5 I2SCL0 I2SCL1 I2SCL2 CSRXD2 CSSCLK2 CSCS2 CSTXD3 CSRXD3 CSSCLK3 CSCS3 CSTXD4 CSTXD5 CSTXD0 CSRXD0 CSSCLK0 CSCS0 CSTXD1 CSRXD1 CSSCLK1 CSCS1 CSTXD2 UATX0 Pin Name I2SDA0
List of Pin Functions(
) ) ) ) )
UART1) 3) 1) 2)
( (UART0)
CSI3 CSI4 CSI5 CSI1 CSI2 1 IIC IIC IIC IIC0) h. 1 h. 0 c c 2.3- h. 4 ( h. 5 ( h. 3 ( h. 1 ( h. 2 (
h. 3 ( h. 1 ( h. 2 ( c c c c c h. 0 ( c c c able
UART UART IIC IIC IIC c IIC
CSI CSI
CSI CSI
CSI CSI ch. 0 (CSI0) Classification
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Pins 123 of
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Section 2 Section
Page Page
clock) data) clock) data)
or dedicatedor IIC dedicatedor IIC Image sensor 0 dedicated serial transmission data output Image sensor 1 dedicated serial transmission data output External flash control pin 0 External flash control pin 1 SDI0 write protect signal SDI1 card detection signal Audio channel clock Audio serial data output Audio master clock input SDI1 data line bits [3:0] Image sensor 0 vertical synchronization signal Image sensor 1 vertical synchronization signal Function Image sensor 0 dedicated serial clock output Image sensor 0 control pulse output Image sensor 1 dedicated serial reception data input Image sensor 1 dedicated serial clock output Image sensor 1 control pulse output Mechanical control pin shutter 0 Mechanical control pin shutter 1 Audio serial clock Audio serial data input Audio master clock output SDI0 card detection signal SDI1 write protect signal Image sensor 0 dedicated serial chip select output dedicated(or IIC Image sensor 0 dedicated serial reception data input ( Image sensor 1 dedicated serial chip select output dedicated(or IIC ( SDI0 command/response signal SDI0 data line bits [3:0] SDI1 command/response signal SDI1 clock Image sensor 0 clock supply port Image sensor 1 clock supply port SDI0 clock Image sensor 0 horizontal synchronization signal Image sensor 1 horizontal synchronization signal
O O O O I I/O I I/O I/O I O I I/O I/O I/O I/O O O I/O O O O O I I O I/O I/O I I/O I O I/O O I/O O O
) 7 / 3
Rev.1.00
IMSTSIG1 IM1TXD IM1RXD IM1SCLK IM1SIG2 to IM1SIG0 IMSHUT0 IMSHUT1 IMSTSIG0 IM0CS IM0TXD IM0RXD IM0SCLK IM0SIG2 to IM0SIG0 IM1VS IM1CS SD0CMD SD0DAT3 to SD0DAT0 SD0WP SD0CD SD1FCMD SD1FDAT3 to SD1FDAT0 SD1FWP SD1FCD IM0VS AULRCK AUBICK AUDI AUDO AUMCLK AUPLLCLK IM1HS IM1CLK SD1FCLK IM0HS IM0CLK SD0CLK Pin Name
List of Pin Functions( AUI)
1
2.3- able
Mechanical shutter
Image sensor timing generator ch. 1 (STG1)
Image sensor timing generator ch. 0 (STG0)
SD host interface ch. 1 (SDI1)
SD host interface ch. 0 (SDI0)
Audio interface ( Classification
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Pins 123 of 42 Section 2 Section
Page Page
Mbps mode
circuit.
(active low)
PHY LINK signal TRST JTAG Ethernet reception clock Carrier detection signal (active high) clock transmission GMII JTAG TDI Motor 0 serial 0 Motor transmission data serial 1 Motor transmission data PHY management data I/O Function Reception error signal (active high) Receive data [7:0] Transmission collision signal (active high) PHY management clock PHY signal interrupt Clock input AVTP PPS (pulse second) per signal JTAG TCK JTAG TDO System reset from debugger (active low) LSI test enable, fixed to the low level Motor driveMotor signal serial 0 Motor chip select serial 0 Motor reception data serial 0 Motor clock serial 1 Motor chip select serial 1 Motor reception data 1 serialMotor clock Transmission clock Ethernet 100 for - Transmission error signal (active high) Transmission data [7:0] Reception data valid signal (active high) JTAG TMS Reserved, leavethese pins open- Transmission enable signal (active high) LSI test enable, fixed to the low level
I I I I I/O O I O O I/O I I I O I I O I O I/O I I O O I O O I O I O O I I O I
) 7 / 4
Rev.1.00
DETMS DETRSTN DESRSTN RETEST1 GERXER GERXD7 to GERXD0 GECRS GECOL GEMDC GEMDIO GEGTXCLK GELINK GEINT GECLK GEPPS DETCK DETDI DETDO MTRXD1 MTSCLK1 GETXER GETXD7 to GETXD0 GERXC GERXDV MTDRV15 to MTDRV0 MTCS0 MTTXD0 MTRXD0 MTSCLK0 MTCS1 MTTXD1 GETXC GETXEN Pin Name MTDCPLS3 to MTDCPLS0 RETEST0
List of Pin Functions (
1
2.3- otor controllerotor MTR) able LSI testFor
Debugger interface
Gigabit Ethernet MAC interface (ETHER)
M ( Classification
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Pins 123 of
43
±1% Section 2 Section positive) negative) positive) negative) positive) positive) negative) negative) Page Page
B clock ( clock B A clock ( clock A A chip select Acommand/address input Bcommand/address input Aclock enable Bclock enable ( clock A ( clock B B chip select
A data mask inversion B data mask inversion A data input/output B data input/output A data strobe ( B data strobe ( B data strobe ( A data strobe (
------circuit. circuit.
down resistor. Resistance: 240Ω - 2 differential clocks 1, 0 (negative) 2 differential data 7 to 0 (negative) 2 differential clocks 1, 0 (positive) 2 differential data 7 to 0 (positive) To connect To a pull Connect the pin to GND via the capacitance. Resistance: 10kΩ ±2% External reference resistor connection pin use for in calibration. * * Recommended capacitance: 2.2 μF DRAM address and command bits: Ch- MIPI CSI- External capacitor connection pin internal for regulator LSI test pin, fixed to the low level LSI test pin, fixed to the low level LSI test pin, leave this pin- open DRAM address and command bits: Ch- DRAM address and command bits: Ch- DRAM data bits and strobes: Ch DRAM data bits and strobes: Ch DRAM data bits and strobes: Ch DRAM data bits and strobes: Ch Function DRAM reset. Note that this requires no external resistor. LSI test pin, leave this pin open- MIPI CSI - MIPI CSI - MIPI DSI differential data 3 to 0 (negative) MIPI DSI differential clock (positive) LSI test pin, fixed to the low level LSI test pin, fixed to the low level DRAM address and command bits: Ch- DRAM address and command bits: Ch- DRAM address and command bits: Ch- DRAM address and command bits: Ch- DRAM address and command bits: Ch- DRAM address and command bits: Ch- DRAM address and command bits: Ch- DRAM data bits and strobes: Ch DRAM data bits and strobes: Ch DRAM data bits and strobes: Ch MIPI DSI differential clock (negative) DRAM data bits and strobes: Ch MIPI DSI differential data 3 to 0 (positive) MIPI CSI - External reference resistor connection pin LVRXAVSS) (to *
O I/O I/O I/O O I/O I/O I/O I/O I O O O I/O I/O I/O I/O I/O I/O I/O I/O O O I I I/O O O O O O O O I/O I/O I I
) 7 / 5
to DSMDPDATA0
LPDQSBC0 LPDQSAC0
, LPDQSAT0 , LPDQSBT0
, LPCKEA0 , LPCKEB0
, LPCSA0 , LPCSB0 A1
Rev.1.00
DSSDNDATA0 DSMDNDATA3 to DSMDNDATA0 DSMDPCLK DSMDNCLK DSMVREG0P4V DSSDPCLK DSSDNCLK DSSDPDATA0 LPDQSAT1 LPDQSBC1, LPDQSBT1 LPMRESETL LPZN LPDTEST MPRXD7M to MPRXD0M MPRXCK0P MPRXCK1P, MPRXCK0M MPRXCK1M, DSMDPDATA3 LPCLKBT LPCS LPCSB1 LPDMDBIA1, LPDMDBIA0 LPDMDBIB1, LPDMDBIB0 LPDQA15 to LPDQA0 LPDQB15 to LPDQB0 LPDQSAC1, LPATEST LPCAA5 LPCAA0 to LPCAB5 LPCAB0 to LPCKEA1 LPCKEB1 LPCLKAC LPCLKAT LPCLKBC Pin Name LVRXREXT MPRXD7P to MPRXD0P List of Pin Functions (
interface
1 2 2 interface 2.3- able
MIPI DSI Tx MIPI CSI - MIPI CSI -
LPDDR4 interface Classification
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123
of
44
Section 2 Section
(negative) (positive) Page Page
(negative) (positive) 2 gap reference (BGR) -
party PCIe devices) (activelow) (negative) (positive) -
down resistor. Resistance: ±1% 200Ω down resistor. Resistance: 8.2kΩ ±1% down resistor. Resistance: 8.2kΩ ±1%
connection pin
- - - signal
speed differential transmission pair speed differential transmission pair speed differential reception pair speed differential reception pair - - - - V signal detection pin - 3.1 super 3.1 super 3.1 super 3.1 super serial transmission data serial chip select serial clock serial reception data To connect To a pull To connect To a pull Resistance partial pressure outside the chip* To connect To a pull ID detection (OTG ID input,0: Host, 1: Peripheral) ESI Rx serial data inputs 1, 0 (negative) Reference resistor * USB Overcurrent detection (active low) Data channel 0 TXPHY output (positive) Data channel 1 TXPHY output (positive) Data channel 2 TXPHY output (positive) Hot plug detection (active high) Rx serial inputs data 1, 0 (positive) Tx serial data outputs 1, 0 (positive) Differential reference clock (positive) Reference resistor connection pin band for and bias generator * USB2.0 USB D− TXPHY clock output (negative) Function ESI Analog input signal Analog input signal Reset output (for other * USB VBUS control signal (active high) TXPHY clock output (positive) Data channel 0 TXPHY output (negative) Data channel 1 TXPHY output (negative) Data channel 2 TXPHY output (negative) DDC IIC master SCL ESI Tx serial data outputs 1, 0 (negative) Differential reference clock (negative) 5 USB USB USB External reference resistor connection pin * DDC IIC master SDA USB2.0 USB D+ signal ESI
I I/O O I I/O I O I O O O I O I I O I/O I/O O I I O O O O O O O I/O I/O O O I I/O I I I I
/7) 6
Rev.1.00
SDTCS3 to SDTCS0 HDREXT HDSCL HDSDA HDHPD SDTTXD SDTSCLK AD0AIN11 to AD0AIN0 AD1AIN7 to AD1AIN0 USTX0M USTX0P USOTGID USPWEN USOVC HDTXCP HDTX0P HDTX0M HDTX1P HDTX1M HDTX2P HDTX2M PCRSTOUTB USDM USRESREF USVBUS USRX0M USRX0P PCRXD1P, PCRXD0P PCRXD1M, PCRXD0M PCTXD1P, PCTXD0P PCTXD1M, PCTXD0M PCREFCKP PCREFCKM PCREXT USDP SDTRXD HDTXCM Pin Name List of Pin Functions (
)
1 ESI
2.3- able ADC unit B ADC unit A (ADCA) (ADCB)
Environment sensor interface (
HDMI Tx interface (HDMI)
USB interface
PCI Express interface Classification
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123 of 45 Section 2 Section Page Page
MHz crystal resonator MHz crystal resonator - -
12[3:0]
GPIO GPIO 17[0]port GPIO 21[0]port Trace clockTrace Function Clock output 1 data [15:0]Trace controlTrace GPIO 09[7:0]port GPIO 10[8:0]port GPIO 11[8:0]port port GPIO GPIO 13[11:0]port GPIO 14[7:0]port GPIO 15[15:0]port GPIO 16[13:0]port GPIO 20[2:0]port Boot device select [2:0] Boot write device select Fix the pin to the low level. When the security function is make in use, sure that the signal level can switched be low between high and (pulled up with VDD18). Boot mode select [0] (reserved) Fix the pin to the low level. Boot mode select [2:1] Boot mode select [3] (reserved) Fix the pin to the low level. connectTo a 48 connectTo a 48 System reset (active low) Clock output 0 GPIO 03port [15:0] GPIO 04port [7:0] GPIO 05port [3:0] GPIO 06port [11:0] GPIO 07[5:0]port GPIO 08[7:0]port Timer pulse 0 I/O GPIO 00port [13:0] Boot GPIO (LED control when booted) Timer pulse 1 I/O GPIO 01port [15:0] GPIO 02port [7:0]
I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I/O I/O I/O I/O I/O I/O I I I I I I O I I/O O I/O I/O I/O I/O I/O
/7) 7
3
Rev.1.00
P17_00 P20_02 to P20_00 P21_00 P09_07 to P09_00 P10_08 to P10_00 P11_08 to P11_00 P12_03 to P12_00 P13_11 to P13_00 P14_07 to P14_00 P15_15 to P15_00 P16_13 to P16_00 GMCLK1 TRCTL P03_15 to P03_00 P04_07 to P04_00 P05_03 to P05_00 P06_11 to P06_00 P07_05 to P07_00 P08_07 to P08_00 MD8* XIN XOUT RSTN GFPLS0 GMCLK0 P00_13 to P00_00 MD2 to MD0 MD3 MD4 MD6, MD5 MD7 GFPLS1 TRCLK P01_15 to P01_00 P02_07 to P02_00 Pin Name TRDAT15 to TRDAT0 List of Pin Functions (
1
purpose ) -
2.3- able
input/output ports (GPIO) General interfaceTrace (TRACE Timer pulse/ clock output
Clock/reset
Boot Classification
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
Pins 123 kΩ of 46 Section 2 Section Page Page
) fixed ( efore, efore, do not use this pin any for other purpose. GND This LSI USVBUS Low level This LSI PWISO RTISO 30kΩ (±1%) ) 1 µF V OSC power supply RTVDD -
5 . Ω 1 k , 0 GND O
/ 10
to
Ω RTC I
pins connected are to this LSI, and these nodes should pulled be with up a 10kΩ to 100kΩ resistor. ( k
10 USB VBUS
Rev.1.00
The schematicThe diagram is shown below. This pin is to be used intended for LED control during boot sequence. Ther Since this LSI has a resistor mounted between the USVBUS pin and connect GND, the pin to the USVBUS pin via a 30- (±1%) resistor. The schematic is diagram shown below. The PWISOThe and SO RTI
Note 3. Note 2. Note 1. R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of theARM 47
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Functional Specifications Functional Section 3 Section coreconfiguration). -
s point Extension Technical Reference Manual pointTechnical Extension -
A53 MPCore (dual MPCore A53 -
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Functional Specification Functional
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ortex A53, . - C
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Arm 1
CPU 1 A53 MPCore Processor Advanced SIMD and Floating and SIMD Advanced Processor MPCore A53 - 3.1- Neon™/FPU
® able L2 cache L2 cache size ECC in the L2 cache L1 cache size (instruction) L1 cache size (data) ECC in the L1 cache Arm Cryptography unit Item of Number Cortex
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123 of 48 Page Page and theboot
Functional Specifications Functional
Section 3 Section
. A53 - Cortex
Mbyte RAM (RMAB) as working areas working as (RMAB) RAM Mbyte -
A53 as an area for booting and working. and booting for area an as A53 -
Kbyte SRAMs. Kbyte -
A53 mainly uses for booting and as a working area. working a as and booting for uses mainly A53 our256 - f
) ) Kbyte RAM (RAMA) and 1 and (RAMA) RAM Kbyte
detectionof ECCan error. - 200
RAMA RAMB
Rev.1.00 ( (
KB KB .
chip ROM which stores the boot program for the the for program boot the stores which ROM chip - 128 200
ROM RAM B RAM A Memory capacity: capacity: capacity: capacity:
ROM RAM capacity: 1 MB1 RAMcapacity: of MB consists 1 of capacity The Aninterrupt generatedis on RAMinitialization functionality is included. RAM Supports ECC
● ● ● ● ● ● ●
3.2.3 on an is ROM The 3.2.2 Cortex the by used mainly is which memory is RAMB 3.2.1 RAMAmemorywhich Cortex the is
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123
of 49
Page Page 2048. Functional Specifications Functional
Section 3 Section ) of thePWM waveforms are backup power supply. power backup
level orderlevel - the
) use of the RTC requires the external connection of a a of connection external the requires RTC the of use ( PWM level high and time clock core 0, CA53 core 1) in response to an overflow of the counter. the of overflow an to response in 1) core CA53 0, core - bitstartup timers (seconds counters). ower supply sequence controller (PWC) so that it can be used as the the as used be can it that so (PWC) controller sequence supply ower
)
WDT timers. - low of nversion
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match
- ck is selectable as the clock source (2 MHz) divided by 2, 4, 8, 16, 32, 64, 128, or 256. or 128, 64, 32, 16, 8, 4, 2, by divided MHz) (2 source clock the as selectable is ck
. Match Timer
timeclock (RTC) modulewhich runs with - Rev.1.00 bit counters and each can be used as an interval timer which generates an interrupt every time the the time every aninterrupt generates which intervaltimer an usedbeas can each bitcounters and bitcounters.
Width Modulation Timer( - - PWMs an oscillationan circuit for real a Time Clock (RTC) bitseconds counters and 23-
- -
atchdog Timer ( eal ompare-
imers R Pulse- C W T kHzresonator crystal -
Thehasinterfacean RTC with external the p startuptimer. available. is function clock The The chip includes includes chip The Thehas32 RTC Each counter operating clock is selectable as the clock source (48 MHz) divided by 1, 16, 256, or or 256, 16, 1, by divided MHz) (48 source clock the as selectable is clock operating counter Each ( level and cycle, duty period, The An interval can be set in the range of 32 bits (1 to 4, 294, 967, 296). 967, 294, 4, to (1 bits 32 of range the in set be can interval An operatingclo Each counter specifiable. The timers have32 The timers reached. counter set is value Aninterrupt requestis outputto (CA53the CPU Resetsthis chip, LSI the if does notsoftware process the interrupt untilnext the counter overflowoccurs after the request. interrupt The timers have32 The timers 32.768
● ● ● ● ● ● ● ● ● ● ● ●
3.3.4 real hasa Thischip LSI
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ons 123 of are 50
Page Page ,UART) I Functional Specificati Functional
units(CS externalmemory.
or
Section 3 Section link aremode, available.
, register, mode and
methods of transfer of methods
Rev.1.00 channel channel DMAcontroller. Selectable from single transfer mode ormode.blocktransfer Selectabletransfersingle from mode bytes. 128 to Selectable1 from Two the within registers control by specified destination and source the between transfer DMA controller. RAM internal the in allocated descriptors with transfer DMA Softwareactivation byhardwareCPU the and activation byinternal possible. -
Controller Controller
DMA request: DMA Registermode: mode: Link
− − Transfer mode: Transfer Transfersize: Transfer Transfer DMA mode:
● ● ● ●
3.4.1 16 hasa chip LSI This 3.4
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123 of from
51 Page Page Functional Specifications Functional
Section 3 Section generic interrupt controller. The version number of the IP module module IP the of number version The controller. interrupt generic
400 Generic Interrupt Controller Technical Reference Manual Reference Technical Controller Interrupt Generic 400 400 -
er
CoreLink GIC- CoreLink GIC CoreLink
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ARM Generic Interrupt Controller Architecture Controller Interrupt Generic .0of the ARM Arm’s Arm’s 2
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is R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of
Input
52 Page Page
irtual channel
Support for Dual Frame
V Functional Specifications Functional
. Section 3 Section
irtual channel
Support for WDR
Up to 2 frames V PHYVer.1.2 -
. D
/
1.2 2 .
CSI- Ver -
2 1 -
*
tate of Support MIPI S Support for 2 Sensor Inputs 4 + 4 lanes (CIF) CSI
Interface
ax. Speed M 2.5 Gbps/lanes
Output DataOutput Format
bit RAW bit RAW
bit RAW bit YUV 422
8- 10- 12- CIF 8-
CMOS image sensor receiver PHY & LINK & PHY receiver sensor image CMOS
-2 Ver1.2 Interfaces Rev.1.00 Image Sensor Interfaces Sensor Image
umber of of Number Lanes 4 lanes × 2
Input/Output Data Formats Supported by the CIF MIPI CSI PHY PHY -
CMOS Image Sensor
CMOS 2 1
2 & D When inputting data in this format, the functions of the LSI that can be used limited. are Contact our sales representative when using this format.
3.6- 3.6-
bit RAW bit RAW bit RAW bit 422 YUV able able 8- 8- 10- 12- Image Sensor Input Data Format MIPI CSI- Interface Ver1.2
Note 1. T Thebelowtable lists the input/output dataformats supported bythe CIF. T 3.6.1 the includes chip LSI This MIPI interfaces: handlefollowing Thethe re can ceiver 3.6 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of
53 Page Page sensor driving and for for and driving sensor -
Functional Specifications Functional synchronousserial -
Section 3 Section
wireclock -
robes, and other devices of the imaging system. imaging the of devices other and robes, (STG)
for CMOS image sensors. image CMOS for
(STG)
for image sensors image for
C communications are available. Both types of communications support the automatic sending sending automatic the support communications of types Both available. are communications C
I ensorTiming Generator utput Rev.1.00 S o
Image communications for controlling the image sensor (or sensors), 4 sensors), (or sensor image the controlling for communications f synchronization. With synchronous driving, both sensors operate with the same timing; with asynchronous asynchronous with timing; same the with operate sensors both driving, synchronous With synchronization. f
Forserial The STG also has functionality for issuing an interrupt with a desired timing in terms of image of terms in timing desired a with interrupt an issuing for functionality has also STG The communications and I and communications The sensor timing generator (STG) is connected to the CMOS image sensor or sensors to generate the timing for for timing the generate to sensors or sensor image CMOS the to connected is (STG) generator timing sensor The master in sensor image the to it supplies and signal synchronization a generates ally intern STG The synchronization. mode. One or two image sensors can be connected to the STG. When two image sensors are in use, there are two choices in in choices two are there use, in are sensors image two When STG. the to connected be can sensors image two or One termso other. the for that from separate completely is sensor each for timing the driving, the output of timing pulses to control mechanical shutters, st shutters, mechanical control to pulses timing of output the sferboth directionsin under tran CPU control. and DMAC dedicated a by setting for values of Generationof shutter triggers Serial interface dedicated for image sensors for dedicated image Serial interface VD/HD generation/ VD/HD Timing generation for image sensors image for generation Timing
● ● ● ●
3.6.2 generator timing sensor a includes chip LSI This
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 54 Page Page Functional Specifications Functional Section 3 Section
in digital in filter usedbereduce can to noise atspecific -
.
(AUI)
audio interface (AUI) interface audio
Rev.1.00 Interface
K frequency 64 fs (fs: sampling rate) sampling (fs: fs 64 Kfrequency udio Interface udio
Audio A Digital volume control (for both playback and recording) and playback both (for control volume Digital Digital filter (onlyfor recording) Slavemode MSBfirst AUBIC
− − − − − Audioprocessing Audioformat: Linear PCM8/16 bits, monaural/stereo kHz 48 kHz, 44.1 kHz, 32 rate: Sampling I2Sinterface
● ● ● ● The audio device is used as the master and the AUI is used asthe slave. used AUI is the master the and useddevice is as The audio Ashasthe processingAUI the audio listedbelow, builta The AUI supports DMA transfer and can send and receive data to and from audio devices that support the I2S interface. I2S the support that devices audio from and to data receive and send can and transfer DMA supports AUI The
frequencies in recording. in frequencies 3.7.1 one includes chip LSI This 3.7 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 55 oblique /
Page Page
detection. Functional Specifications Functional rocessor (DRP) technology. It It technology. (DRP) rocessor
P Section 3 Section low power consumption. power low
econfigurable econfigurable R with ynamic ynamic D
embedded AI AI embedded
es uses the the uses
.
that 270 degrees) 270 Up, down, left, and right are supported. are right and left, down, Up, 359 to (0 angle detection 9), to (0 value evaluation size, Position, degrees),direction and (front right oblique / right sideleft / / leftside) 35(max.) detection. for direction reference to the degreesrelative ±10 supported. are right and left, down, Up, and 180, 90, (0, angle detection 9), to (0 value evaluation size, Position, 35(max.) for direction reference to the degreesrelative ±45 unit
n and realiz and AI)
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alyzing
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AIaccelerator -
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Rev.1.00
Target Detectio ccelerator
A
ensing and An
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etectiondirection: etectiondirection: D detection: on information Incidental The number of simultaneous detections: simultaneous of number The Detectionangle: The number of simultaneous detections: simultaneous of number The Detectionangle: D detection: on information Incidental
− − − − − − − − Human Facedetection
● ● supports various types of neural network neural of types various supports 3.8.2 ThisLSI includes chip multi a 3.8.1 ThisLSI includes chip DRP the 3.8
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 56
Page Page ofsquares/
Functional Specifications Functional Sum
accelerator. Section 3 Section value for difference/ for value
Absolute
and numeric calculation
5filter)
× Accelerator 5
quivalence determination/ quivalence
purpose image processing purpose
- or
) purpose processing image 3
-
× oduct/E
Pr
Purpose - Rev.1.00
MAX/MINfilter
General
purposefiltering (3 conversion LUT purpose - - tions to assist in general in assist to tions Vectorcalculations Matrixoperations solver equation Simultaneous Datastring operations ( Alpha blending General (RGB/YUV/HSV) conversion space Color General Histogrammeasurements Labeling Morphology( Hammingdistance)
● ● ● ● ● ● ● ● ● ● ●
processing calculation numeric assist in to Functions Func 3.8.3 general a includes chip LSI This R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 57 Page Page Functional Specifications Functional Section 3 Section
/ 640 × 480 p × 800 fps p 800 × 480 × 640 /
resolutiontechnology
-
/ 1920/ × fps108030 2 ×p ×
Graphics ISP
Rev.1.00
estitching amera correction
C
supported(motion compensation)
Video & imag eye - - Detection of exposure, white balance, focus, and flicker and focus, balance, white exposure, of Detection Resizer Sensor scratchcorrection Rollingcorrection shutter Equirectangulardomemasterto conversion Two Fish super the by processing Sharpness Electronicimage stabilization distortion) shading, (color, correction aberration Lens Tonemapping WDR reduction noise 2D compensation) (motion reduction noise 3D 3840 × 2160 p × 30 fps × p 30 2160 × 3840
● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
3.9.1 ISP. camera includes Thisa chip LSI 3.9 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 58 Page Page onal Specifications onal Functi Section 3 Section
fps decoding fps
0 fps decoding fps 0 60 6 × 30 fps decoding fps 30 ×
p
c
supported 19201080× p ×
Multi Code Multi
encoding
fpsencoding, 1920 1080× ×p
0 fps encoding, fps 0 Rev.1.00 60 6
× 30 fps encoding, 3840 × 2160 × 3840 encoding, fps 30 × g and decoding performance decoding and g
p × 800 fps encoding fps 800 ×
× 800 fps 800 ×
p p
H.265/H.264 4/H.265 encode/decode I/P slice slice I/P 4/H.265 encode/decode 640480 × 1920 × 1080 p × × p 1080 × 1920 3840 ×2160 encodin H.264 Constrainedbaseline profilelevel 5.1,at Baselineprofile 5.1atlevel performance decoding and encoding H.265 Highprofile atlevel 5.1, Progressivehigh profile at level 5.1, Constrainedhigh profile 5.1,atlevel Mainprofile atlevel 5.1, 640480 × 1920 × 1080 p × × p 1080 × 1920
− − − − − − − − H.265/HEVC mainprofile atlevel 5 H.26 H.265/HEVC MP (main profile) supported profile) (main MP H.265/HEVC H.264/AVCbaseline/main/high profile supported
● ● ●
3.9.2 H.265. and H.264 to conforming codec video a includes chip LSI This
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 59 Page Page Functional Specifications Functional
Section 3 Section
Quadrangles, and Circles and Quadrangles,
graphicscore. -
JEPG codec unit. codec JEPG 2D
odec Rev.1.00 a a
C
turesize Graphics Engine
aliasing and sub pixel accurate rendering pixel sub accurate and aliasing -
JPEG 2D Color format:YUV 16cycle samples/clock Max. data rate: Image Handles the JPEG and baseline process.baseline HandlesJPEG and the Flexible colorizationusing multiple passes Dedicatedunitclearing clear to memory regions bandwidthatmaximum 40964096× tex Offers a wide range of graphical primitives, e.g. Lines, Triangles, Triangles, Lines, e.g. primitives, graphical of range wide a Offers anti Supports Generationof Bezier lines and segments Bezier
● ● ● ● ● ● ● ● ●
3.9.4 ThisLSI includes chip
3.9.3 ThisLSI includes chip R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 60 Page Page
4A. - Functional Specifications Functional Section 3 Section speed DDR and HS400 are not not are HS400 and DDR speed
supported:
)
- (high modes transfer HS200 and speed, -
eMMC
1
ce
*
: 4GB : 2GB,
interfaceusewith LPDDR4 for that is conformant 209with JEDEC
eMMC interface conforming to eMMC version 4.51. version eMMC to conforming interface eMMC memory
Interfa
bit MMC bus) MMC bit compatible,high
- - Rev.1.00
rank - purposecommand) is not supported except calibration ZQ - Gb (per channel) densities with byte mode byte with densities channel) (per Gb MMCdeviceaccess - - and2 backward
memory capacities memory
Interfaces Memory xternal
eMMC Interface ( LPDDR4 E Regarding 2-rank memory products, contact us in advance because restrictions may apply to the memory device you intend to use. refresh abortmode Since the pin functions this for shared are interface with those the for NAND flash interface, they cannot be used at the same time as the NAND flash interface. - and 16 and
-
12 MPC(multi derating) (for refresh Modified BL32functionality Self
Note: − − − − − Support for boot operation and alternative boot operation boot alternative and operation boot for Support Support for e for Support for Support (HPI) interrupt priority high the for Support MMCinterface (1/4/8 Datawidth:bus 32 bits Supported Supports 1- not are LPDDR4 with use for features following The Supporteddatarate: 3200 Mbps supported)
● ● ● ● ● ● ● ● ● ●
his LSI chip includes an an includes chip LSI This 3.10.2 Note 1. 3.10.1 ThisLSI includes chip DDR a 3.10
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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s. Page Page Functional Specifications Functional specification 1.0 Section 3 Section compliantwith ONFI the that are are that s
(NAND)
MB
Rev.1.00 Flash Interface
one, 4 bits, or 8 bits 8 or bits, 4 one, or 256
N MB
NAND compliant (8bits)
0 Since the pin functions this for shared are interface with those the for eMMC interface,they cannot be used at the same time as the eMMC interface.
notsupported
Note: EDO ONFI 1. ONFI Capacity:128 Errorcorrection:
● ● ● ●
3.10.3 device flash NAND with interface an has chip LSI This R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 62 party party - Page Page
Functional Specifications Functional Section 3 Section
) bit SD bus) SD bit pplies other than PWC and RTC of this LSI chip while the other the while chip LSI this of RTC and PWC than other pplies - I/SDR12, SDR25, SDR50, and SDR104 transfer modes (DDR50 not not (DDR50 modes transfer SDR104 and SDR50, SDR25, I/SDR12,
- SDI for SD, SDHC, and SDXC and SDHC, SD, for ( bit/4 -
speed, UHS speed, related products requires conclusion of SD Host/Ancillary Product License Agreement (SD HALA). -
Rev.1.00
eripheral Interfaces eripheral
SD Host InterfaceSD P Development of SD-
Note: device’s power is on. is power device’s Carddetection Write protection su power off turning of capable is SDI1 Support for SD memory card access memory SD Supportcard for high default, for Support (data) CRC16 (command/response), CRC7 checking: Error SD memory/ I/O card interface (1 interface card memory/I/O SD supported)
● ● ● ● ● ● ●
3.11.1 ThisLSI includes SDinterfaces host two are that compliant specificationwith SDthe version 3.01. 3.11 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123
of
63
Page Page speed (1.5 MHz) MHz) (1.5 speed
- and (interrupt) 3 and supported) Functional Specifications Functional
speed (1.5 Mbps) transfer Mbps) (1.5 speed -
) supported not is bandwidth transfernotis supported)
bandwidth is not supported) not is bandwidth Section 3 Section
large large
speed(12M bps) transfer (low - speed (12 Mbps), and low and Mbps), (12 speed - (theconfiguration follows.)as is
interrupt (*isochronous transfer is not not is transfer (*isochronous interrupt B
,and interrupt (*isochronous (*isochronous ,and interrupt
bulk bulk , , , , (480 Mbps), full Mbps), (480
; OUT:; K 16 B speed (480 Mbps), and full and Mbps), (480 speed speed specifications. - -
bulktransfer (isochronous transfer notis supported)
15 15 roledeviceis conformantthat with USB1 3.1the Genspecification.
- , and ,
to to al 64 bytes for pipe 0, up to 1024 bytes for others (* others for bytes 1024 to up 0, pipe for bytes 64 512bytes for pipe 0,up to1024 bytesfor others (* 1 between and (bulk) 16 1 and between (control), 0 pipe 1 for to Fixed Fixed to 31 0 0) pipe (only Control IN/OUT 0 0) pipe (only Control IN/OUT
ufferIN: 17size: K
control
Rev.1.00 , , eXtensibleHost Controller Interface (xHCI) Specification forUSB
6,B
speed (5 Gbps), high Gbps), (5 speed speed (5 Gbps), high Gbps), (5 speed
- - Interface
ransfer: ransfer:
USB ] Function ] Function
mpliantwith the irectionof t Transfer Type: Transfer D Max.packet size: Max. sequence number: sequence Max. number: Endpoint Transfer type: Transfer Direction of t Max.packet size: size: burst Max. Endpoint number: Endpoint Support for super for Support interrupt for Support 1 pipes: of Number Support for all transfer types: isochronous, interrupt, control, and bulk and control, interrupt, isochronous, types: transfer all for Support bandwidth. large a with transfer interrupt and isochronous for Support Co super for Support notsupported)
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● [USB3.1
[USB2.0 following the has controller function The Configurations provided below can be set for each pipe. each for be set can below provided Configurations
hostThecontroller has following the specifications. 3.11.2 du one includes chip LSI This Configurations provided below can be set for each pipe. each for be set can below provided Configurations R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of chip 64 LSI an Page Page defined in the PCI PCI the in defined Functional Specifications Functional as the MACtheand layer is up to to up Section 3 Section interface
rootport or endpoint
a asingle
conformant with the Media Access Control (MAC) layer layer (MAC) Control Access Media the with conformant ) erfacesupported
) duplex communications duplex size: up to 512 bytes 512 up to size: thatis - PCI
conformantwith Ethernet (IEEE 802.3) through connection with supported
Mbps half Mbps - PCI Express Gen2 (5GT/s) interface. (5GT/s) Gen2 Express PCI
Interface (ETHER) compatibleint
AER
thatare C ( lane
- complex and endpoint, and operation is as as is operation and endpoint, and complex Ethernetcontroller
two Rev.1.00 an a
logging
the physical layer.physical the Mbps and 100 and Mbps and
Ethernet MA PCI Express Interface ( to handle handle to LSI) LSI) able of transferring frames frames of transferring able Supportfor 1000 - PHYinterface: GMII MIIand - Error handling Error ECC andparity for internalmemory 8 channels: DMAC of Number supported not substates L1PM Data payload: up to 128 bytes; read request request read bytes; 128 to up payload: Data only) (VC0 channels Virtual 8 1 to outstanding: of Number supported) (ASPM Management Power One or two lanes can be implemented. be can lanes Oneor two
● ● ● ● ● ● ● ● ● ● ● Expressspecification.
3.11.4 ThisLSI includes chip specification for Ethernet (IEEE 802.3). The Ethernet controller has has controller Ethernet The 802.3). (IEEE Ethernet for specification here are two modes, root modes, two are There 3.11.3 ThisLSI includes chip cap (PHY-
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
s 123 of input 65
SPI master master SPI
”from Philips signal(CS) for
Page Page ed as an as ed itional Functional Specification Functional add
serialclock (SCL) serial dataand and onefor reception.
only mode, or slave slave or mode, only : it has it an -
, Section 3 Section
.
bitACK signal). s. slave select - a slave. It alsocan be us line. 1
to ) as the
n o
configurable signals
usingsignals:three clockserial(SCK), serial data CS
by ) followed by by followed
forthe are )
( s SPI (serial SPI(serial peripheralinterface) BUS SPECIFICATION VERSION 2.1 JANUARY 2000 2.1JANUARY VERSION SPECIFICATION BUS multiple devicesusingby lines two - CSI ( C MHz in slave mode.slave MHz in I2
bit value bit 24 -
as output as s
8
THE he t toand from (IIC) speed mode (3400 kbits/s) is not supported. not is kbits/s) (3400 mode speed operation as an an operationas
-
interfaces. stage FIFO buffers are included, one for transmission transmission for one included, are buffers FIFO stage
-
C I busformat (“
bit)16 C MHz). Interface - Rev.1.00
I2
level widthlevel ofthe serial clock (SCL) issignal only mode, master transmission/reception mode, slave reception slave mode, transmission/reception master mode, only
- - pins pins port output purpose clock synchronous serial communication communication serial synchronous clock bit+8 - -
IC Bus orlow
Clocked Serial Interface I
standardmode (transfer rate: 100up kbits/sto fastmode (transfer rate: up to 400kbits/s)
bit(8 - as a . slave handles handles
nterface handles data transfer nterfacedata handles transfer n o upports Theserial clock input frequency up to is selectable. is controller DMA external the by transfer DMA or interrupts to response in transfer Data 16 Two Thewaiting time betweenserial data is specifiable masterin mode. Theserial datalength 16is selectable orbits. 8 from Thefirst bit ofserial data isselectable fromMSB or LSB. master clock 32766(the 2 from to by values clockdivided master as the selectable is mode master clockin The serial 48 to up is frequency Masterreception transmission/reception mode is selectable. is transmission/receptionmode - high The Aorstop startcondition determinedis according statethe ofto bus the data. of transfer consecutive allows buffering Double Compliantwith the S Supports Thei (however, bits 8 is length data The Semiconductors). However, high However, Semiconductors). bus(SDA).
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● by using general using by The CSI can be used as a SPI slave as it has an input (CS) for selecti for (CS)an input has it slave as SPI a used be as Thecan CSI selecti (SI), and serial data output (SO). In (SO). output data serial and (SI),
TheCSI ThisLSI includes chip sixCSI interfaces. 3.11.6 3.11.5 ThisLSI chip includes four I
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 66
Page Page ble. la i
. ava Functional Specifications Functional 18) /
. (1
)
Section 3 Section
. UART (
pins
)
. programmable control are (except for some pins) some for (except s
GPIO Listof External Pins use use GPIO as , ,
1 - formsof setfor
s setting by only - UARTchip
able 2.2 able T rate generator allows selection of the desired bitrate. desired ofthe selection allows generator rate Parity error, FE: Framing error, BI: Break interrupt) error data data error interrupt) Break BI: error, Framing FE: error, Parity can be be can down”by setting
-
. . Thefollowing
bit(PE: - only, or output or only,
chip baud baud chip purpose16750
- - - CTS are supported. are CTS
- down column in in column down -
5, 6, 7, or 8 bits 8 or 7, 6, 5, parity no or odd, Even, bits 2 or 1 Theon Supports majorbaud rates (such 9600 as bps, 19200 bps, 38400 bps, 57600bps, and 115200 bps) up” or “with pull “with or up”
-
ived data ived rece
.
up/Pull ers are included, one for transmission and one for reception. One of the following operating operating following the of One reception. for one and transmission for one included, are ers -
Purpose Input/OutputPorts ( pported GPIO -
Rev.1.00
RTS auto and -
handled in in handled
eneral
G Universal Asynchronous Receiver/Transmitter compatible with the general the with compatible hanged to input/output, input input/output, to hanged bitlength control: byteFIFO buff - FIFO mode(16450 mode)
- - - byte FIFO mode (16550 mode) (16550 mode FIFO byte mode FIFO byte - - Character length control: length Character Paritybit control: Stop control: rate Baud Non 16 64 egister
rogrammable auto − − − − − − − Fordetails, the see Pull The output driving ability is changeable by settings. by changeable is ability driving output The pull “with to changed be Can he defaultThe setting is Canbe c register. su function Loopback signals. clock serial and clock bus the as input be can signals clock Asynchronous CTS and RTS are supported for the modem control interface. control modem the for supported are RTS and CTS DMA interfacesupported TheFIFOreception buffer 3 a includes P for data serial to appended be can bits control transfer asynchronous standard the as bits parity and stop, Start, and transmission R 64 Two modes isselectable bysettings.
● ● ● ● ● ● ● ● ● ● ● ● ●
3.11.8 CIF) for (except chip LSI this of pins Multiplexed
3.11.7 UARTs. hastwo chip LSI This
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Functional Specifications Functional D conversion to memory memory to conversion D / Section 3 Section 48))
to
1
=
(N
adjustment.
)
).
ESI ESI (
wire clock synchronous serial interface (SPI). interface synchronous serial clock wire -
MHz(24/N MHz
24
.
)
Eitheror first MSB firstLSB is selectable the for transmission receptionand of data. SPI(CS/SCLK/TXD/RXD) only mode Master Upto 4(CS0/CS1/CS2/CS3)
(MTR
Sensor Interface
Rev.1.00
includes a motor control circuit control motor a includes
Environment Motor Controller
is also connected to an A/D converter (ADC) and transfers the acquired results of A of results acquired the transfers and (ADC) converter A/D an to connected also is repeatedly communicates with external devices at desired set intervals and transfers the acquired data to to data acquired the transfers and intervals set desired at devices external with communicates repeatedly 4 via a devices external the connected is to
I ethodof communications: wire clock synchronous serial communications serial synchronous clock wire ES ESI erial clock: - S Chipselect lines: Selectionofactive the ofsense CS, data and CLK, timing and Datacommunications specification: M Operating mode: Driving pulse output for stepping motors stepping for output pulse Driving 4
● ● ● ● ● ● ● ● The memory (DRAM) in order by using the DMA function. DMA the using by order in (DRAM) memory The TheESI (DRAM). Specificationsof communications SPI
3.11.10 ThisLSI includes chip environmentan sensor interface ( 3.11.9 ThisLSI chip
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Page Page Functional Specifications Functional
Section 3 Section
mage and graphicsscreens. mage and
. imageand graphics screens.
ps
f
60
080 p × p 080 the display via HDMI and MIPI DSI interfaces. DSI MIPI and HDMI via display the
1
.
controls 1920 × 1080 p × 60 fps, 1080 × 1920 p × 60 fps p 60 × × 1920 1080 fps, × p 60 1080 × 1920 1920× Control Unit
Rev.1.00
Reductionby linear interpolation
frame:Expansion by simple interpolation
isplay Interface isplay
Display D DMI: Two display areas (DRAMs) are used for each of the of the each for used are (DRAMs) display areas Two outputwith is composite a which after specifieda level, at combined be frames image can Two the given alpha values alpha given the One display area (DRAM) is used for each of the of each for used is (DRAM) area display One A composite is output with the given alpha values alpha given the with output is composite A
MIPI DSI: MIPI H Color gain, and brightness offset brightness and gain, Color Brightnesschroma and conversion RGB to YUV and correction, gamma temperature, color gain, Color For simultaneous display via the MIPI DSI and HDMI and DSI MIPI the via display simultaneous For For a single MIPI DSI or HDMI display HDMI or DSI MIPI single a For Imageframe: Graphics foreground. the as assigned is frame graphics the and background the as assigned is frame image The
− − − − − − − − − −
Dedicated image adjustmentfor MIPI the DSI Dedicate d image adjustmentfor HDMI Imageframe adjustment Picturecompositing Maximumdisplay size conversion Resolution
● ● ● ● ● ●
3.12.1 unit. control display a includes chip LSI This unit control display The 3.12 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Page Page Functional Specifications Functional Section 3 Section liststhe image frameand sizes rates for the
2
- 3.12 able T and
conversion 22
)
HDMI
444, YUV4 HDMI
pecification S
2 32 kHz, 44.1 kHz, 48 kHz YUV BT601 to BT709 S 8 bits 2 ch. LPCM 16 bits, 24 bits 2.97 Gbps I supported.
Interface (
Rev.1.00
60.000 Frame Frame Rate (Hz) 60.000
Image Sizes and Frame Rates for the HDMI Specifications of the HDMI gives the specifications of the the of specifications the gives
1
HDMI Tx
-
CEC, HDCP, and HEAC are not 720 p 1080 p . 3.12-2 3.12-1
able able Image Size 1280 × 1920 × PHY operating frequency (Max.) Audio sampling frequency Audio channel status Audio length word Color space converter Audio I/F Audio channel Output formatOutput Color depth Item
HDMI
T Note: T able 3.12 Table 3.12.2 ThisLSI includes chip outputan interfaceis conformantthat with HDMIspecification, the HDMI1.4a. R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Page Page
Remark Burst mode is not supported. Functional Specifications Functional
Section 3 Section
blank period. - TX command packet in a
-
8 format 6 (loosely format packed) 6 format 5 format - - - - 8 6 6 6
burst mode with sync pulses burst mode with sync event TX: 1024 bytes RX: 128 bytes TX: 128 bytes 11 circuit for a MIPI Display Serial Interface (DSI). Interface Serial Display MIPI for a circuit bit RGB 8- bit RGB 6- bit RGB 6- bit RGB 5- - - - - pecification 24- 18- LP 18- LP LP Blanking Packet Non- HS S 16- Transmission of one HS single during frame the V Non-
MIPIDSI . PHYTx
Interface
Rev.1.00
Blank period Transfer packet sequence of Number bytes transfer for Item Video format Transmission of command packets in videomode Specifications of the MIPI DSI
gives the specifications of the the of specifications the gives CD Control
3
L
-
3.12-3
ode thers able O Command mode
Video mode M
able 3.12 Table
T 3.12.3 - D MIPI and link the includes chip LSI This R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 71 Page Page Functional Specifications Functional Section 3 Section
which handles security functions. security handles which
IP
ecurity
trustedsecure IP S
Rev.1.00 a
ecurity Engine ecurity
Trusted S 224/256 tamper proofing algorithms proofing tamper 224/256 -
RSA2048signature verification algorithm SHA AES and ARC4 encryption and decryption algorithms decryption and encryption ARC4 and AES
● ● ●
3.13.1 ThisLSI includes chip 3.13 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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72 Page Page s repeated at at srepeated Functional Specifications Functional
Section 3 Section
. B
) B
approximation A/D converter units. Up to 12 channels of analog input input analog of channels 12 to Up units. converter A/D approximation -
TSU)
), 8 channels (unit (unit channels 8 ), DC)
A bitsuccessive A -
).
and up to eight channels are selectable for unit unit selectablefor are channels eight upto and
Rev.1.00 ESI
A
2
Converter ( of A/D conversion is stored in memory (DRAM) by using the DMA function of the environmental environmental the of function DMA the using by (DRAM) memory in stored is conversion A/D of
12bits emperature Sensor (
nalog
T A/D A continuousscan
sensor interface ( sensorinterface aset interval. aset interval. Each resultEachof A/D conversion is stored register.in a Eachresult The selected channels are scanned and converted in the specified order, and the conversion is repeated at at repeated is andthe conversion order, specified in the scannedand converted are channels selected The The selected channels are scanned and converted in the specified order, and the conversion i andthe conversion order, specified in the scannedand converted are channels selected The Scan conversion only proceeds once for the selected channels in the specified order. specified the in channels selected the for once proceeds only conversion Scan resultEachof A/D conversion is stored register.in a ESI Continuous scan Continuous Single scan
− − −
Samplingrate: 600 kS/s Operatingmodes Number of units: units: of Number (unit channels 12 channel: Input Resolution:
● ● ● ● ●
3.14.2 chip. internal of the thetemperature measuring for sensors of channels temperature includes Thistwo chip LSI The temperature within this LSI chip can be obtained by reading the digital values to which the temperature sensor sensor temperature the which to values digital the reading by obtained be can chip LSI this within temperature The converters. A/D the by converted were outputs 3.14.1 12 two incorporates chip LSI This independently. operates converter A/D The 3.14 are selectable for unit unit for areselectable R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123
of 73 al Specifications al Page Page
Function
)function). G lockedloop (PLL) circuits, - Section 3 Section (SSC phase , , generator generator
MHzcrystaloscillator required.)LSIthis is to chip -
48
. (CPG)
(CPG)
ator
. The frequency is changed by software through the setting of the frequency control control frequency the of setting the through software by changed is frequency The .
CPG
Rev.1.00
ion: circuits have spread spectrum clock generator (SSCG) function. The output frequency of an SSCG SSCG an of frequency output The function. (SSCG) generator clock spectrum spread have circuits lock Pulse Generator : function change Generator Pulse lock -
C
C function:
Thishasmodule a sequencer that automatically controls clocks the required boot theto CPU after resetsystem the is released. registers. Mostof the PLL electromagnetic the in peaks the of levels the suppresses which frequency, the vary slightly to modulated is noise. (EMI) interference circuits PLL the using by independently changed be can clocks various other and clock CPU the of frequencies The the within dividers and Controls clock supply to the internal units according to their states (the power state, etc.). state, power (the states their to according units internal the to supply clock Controls Clock gating funct gating Clock Sequencer function: Frequency SSCG Anoscillation circuit is included (External connection ofa operations internal LSI for signals clock various of Generation spreadspectrumclock a include ofthese (five included Six are PLLs
● ● ● ● ● ● ●
Theoscillationof CPG consists an circuit for connection a crystal to resonator
3.15.1 gener pulse clock a includes chip LSI This frequencydividers, selector circuits, gatingclock and circuits. 3.15 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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74
Page Page Functional Specifications Functional
Section 3 Section
(PWC)
trol the various external power supplies (regulators and and (regulators supplies power external various the trol
Rev.1.00 Control
shows an example of a system configuration for external power supplies. power external for configuration system a of example an shows
1 - xternal Power Controller Sequence ower
E P
power supply switches) required by this LSI chip and a system reset signal (PWSYSRSTN) for this chip. this for (PWSYSRSTN) signal reset system a and chip LSI this by required switches) supply power ThePWCoutputs enable signals (PWENn 0 (n: 5))to to con 3.16 Figure External power supply on/off sequence on/off supply power External
●
3.16.1 switches). supply power and (regulators supplies power external for (PWC) controller a includes chip LSI This 3.16 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123
of ) V) 75 Voltage Voltage detection detection VCCPWC (1.8 V) VCCPWC (1.8V) VCCPWC (1.8 V) VCCPWC (1.8 V) VCCRTC (1.5 V VCCPWC (1.8 VCCPWC (1.8 V) Page Page ) RTRSTN PWKY4N PWKY3N PWKY1N PWKY0N PWKY2N PWRSTN Functional Specifications Functional ) ) , USVD330, USVPH) , USVPTX) RTC PWC , USVP Clock for the PWC Section 3 Section (DSMVDD12) (for various IP modules (USDVDD (for internal cells and various IP modules (various IPs modules (LPVDD) (LPVDDQ) (for various I/O cells (for various I/O cells and various IP This LSI )
V power supply V power supply V power supply V power supply 1- RTXIN RTXOUT PWMEMSWIENA 1.2-V power supply 0.8-V power supply (PWVDD08) 1.5-V power supply (RTVDD) 1.8-V power supply 0.8-V power supply PWISO RTISO 0.8-V power supply 0.8- 0.8- 1. 3.3- 0.8-V power supply (RTVDD08) 1.8-V power supply modules 1.8-V power supply (PWVDD) PWVBAT PWEN0 RSTN PWSYSRSTN PWEN5 PWEN4 PWEN3 PWEN2 PWEN1 pplies ) V) SW SW SW SW LDO LDO (0.8 V) (0.8 V) VCCPWC (1.8 V) VCCRTC (1.5 V) 32.768 kHz . VCCRTC (1.5 VCCPWC (1.8 V V REG REG REG REG REG 1.2 V 3.3 1.1 V 0.8 V 1.8 V LDO LDO EN EN EN EN EN (1.5 V) (1.8 V) detection Voltage state Rechargeable battery for backup
On/Off Procedures - V) V
LDO (3.3 5.0 Boosting
DC to DC EN
4.3, Power
Rev.1.00
Example System Configuration for External Power Su
This figure is an example and does not guarantee the operation of the external circuitry it shows. Follow the procedures described in Section
3.16-1 AC adapter Note: igure
F R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123
of 76
Page Page
Functional Specifications Functional 15.63 ms
e output pins control the rising rising the control pins output e
Section 3 Section 7.81 ms
7.81 ms
4.3.2. 4.3.2. 4.3.2. 4.3.2. 4.3.2.
15.63 ms
39.06 ms described in Section Used to control the on/off status of the external power supply (regulator) for timing 5 Used to control the on/off state of the main external supply power (regulator) Used to control the on/off status of the external power supply (regulator) for timing 1 described in Section Used to control the on/off status of the external power supply (regulator) for timing 2 described in Section Used to control the on/off status of the external power supply (regulator) for timing 3 described in Section Used to control the on/off status of the external power supply (regulator) for timing 4 described in Section Function
Rev.1.00
shows the timing of the outputs from the PWENn (n: 0 to 5) and PWSYSRSTN pins. PWSYSRSTN and 5) to 0 (n: PWENn the from outputs the of timing the shows
2 - Timing of the Outputs from PWENn the (n: 0 to 5) and PWSYSRSTN Pins
PWEN5 PWEN2 PWEN3 PWEN4 Output PinOutput PWEN0 PWEN1 3.16-2 PWSYSRSTN output pin: output PWSYSRSTN of control reset allows chip LSI this of pin) input RSTN (the pin control reset system the to output this Connecting chip. the PWENn (n: 0 to 5) output pin: output 5) 0 to (n: PWENn thes (regulators), supplies power external the of pins control the to connected Being and falling of the various power supply voltages. supply power various the of falling and PWEN0 (Main power supply) PWEN1 PWEN2 PWEN3 PWEN4 PWEN5 PWSYSRSTN
− − igure 3.16 Figure igure F
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V - 123 of 77
Page Page
.
Functional Specifications Functional 4.3.2 ace SDI0 ace similar usingwithout the
Section Section 3 Section
(PMC)
offstate. - ontroller power switch. Connect the PWMEMSWIENA pin to the enable pin of of pin enable the to pin PWMEMSWIENA the Connect switch. power power
chip LPDDR memory controller unit (power supply domain PD_MEM (0.8 PD_MEM domain supply (power unit controller memory LPDDR chip -
theon
output pin: Enable signal output pin for controlling the LPVDD power supply on/off supply power LPVDD the controlling for pin output signal Enable pin: output
Rev.1.00
output regulator for these IO power supplies, the IO voltages can be switched from 3.3 V to 1.8 V or or V 1.8 V to 3.3 from switched be can voltages IO the supplies, power IO these for regulator output - V power to LPVDD through the the through LPVDD to power V SEL output pin: For switching the IO power supply voltage of SD host interf host SD of voltage supply power IO the switching For pin: output SEL SDI1 interface host SD of voltage supply power IO the switching For pin: output SEL on sequence of the PWC from a from PWC the of sequence on
Internal Domain Power C 0 1 - power supply control supply power multi
is equipped with a power switch that divides the internal power supplies into multiple power supply domains domains supply power multiple into supplies power internal the divides that switch power a with equipped is PWSD PWSD PWMEMSWIENA
− − − this powerswitch. - 0.8 Supply LPVDD is the power supply for supply power the is LPVDD of FW System the by controlled individually is supply power LPVDD the on/off turning and system)), supply power thisLSIbooting. after Witha pins. 1) 0, (n: PWSDnSEL the on signals using by V 3.3 V to 1.8 from Control signals PWSDnSEL (n: 0, 1) are output for switching of the IO power supply voltages (between 1.8 V and and V 1.8 (between voltages supply power IO the of switching for output are 1) 0, (n: PWSDnSEL signals Control V). 3.3 Changes in the input levels on the PWKYnN (n: 0 to 4) pins can be detected and used as the sources of triggers for for triggers of sources the as used and detected be can pins 4) to 0 (n: PWKYnN the on levels input the in Changes thepower Switching the external IO power supply voltages for the SD host interfaces (SDI0 and SDI1) and (SDI0 interfaces host SD the for voltages supply power IO external the Switching Key input function input Key LPVDD
● ● ●
This LSI chip includes a controller (PMC) that controls switching of the internal power domains on and off. and on domains power internal the of switching controls that (PMC) controller a includes chip LSI This 3.16.2 This LSI LSI This that domains power to power the off turning by standby on power the reducing allows Thus supplied. is power which to arenot required to operate. Control of the external power supplies by an external PMIC (power management IC) or IC) management (power PMIC external an by supplies power external the of Control PWENn (n: 0 to 5) outputs of the PWC is also possible. For details on the specifications for the relative timing of rising rising of timing relative the for specifications the on details For possible. also is PWC the of outputs 5) to 0 (n: PWENn in description the see chip, LSI this of pins supply power the on voltages falling and
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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. Functional Specifications Functional website
Arm Section 3 Section
. on the the on
tosupport emulator
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Section 4 Section 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 − − − − − − − Min. − − − − − − − − − − − − − − − −
DD DD
DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD
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able PORT15, PORT16 , PORT17 PORT15, PORT16 , PORT17 I/O PORT09 pre PORT09 I/O PORT00 I/O PORT08 pre PORT08 I/O PORT11 pre PORT11 I/O PORT00 pre PORT10 pre PORT10 I/O PORT01(B), PORT04, PORT07, PORT21 I/O power supply PORT06 pre PORT06 I/O power supply PORT01(A), PORT03 I/O power supply PORT01(B), PORT04, PORT07, PORT21 pre supply PWC core power supply PWC power I/O supply PORT01(A), PORT03 pre- RTC core power supply RTC I/O,RTC 1.5 Item VDD08 core power supply
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6, 7)
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V power supply V power supply V power supply V power supply V power supply Rev.1.00
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PORT13 I/O, PORT13 I/O, PORT05 I/O, PORT14 I/O, PORT14 I/O, PORT20 I/O. PCIe I/O, RSTN I/O, PCIe I/O, 1.8- USB I/O, LSI test I/O) debugger I/O, USB I/O, LSI test I/O) MD0- (PORT12 I/O, (PORT12 I/O, (PORT02 I/O,
able USB PHY HS section 1.8- USB PHY HS section 0.8- PCIe PHY 0.8- PCIe PHY 1.8- USB PHY HS section 3.3- MIPI DSI Tx PHY 1.2- MIPI DSI Tx PHY 0.8- HDMI PHY 1.8 HDMI PHY 0.8 MIPI DSI Tx PHY 1.8- LPDDR4 core 0.8- LPDDR4 PLL 1.8 LPDDR4 I/O CIF PHYCIF 0.8 PHYCIF 1.8 TSU ch. 1 1.8 ADC unit A ADC unit B TSU ch. 0 0.8 TSU ch.1 0.8 TSU ch.0 1.8 OTP 0.8 OTP 1.8 OTP PLL ch. 1, 2, 3, 4, 7 0.8- 6, PLL ch. 1, 2, 3, 4, 7 1.8- 6, VDD33 group
VDD33 group
VDD18 group Item
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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5 6 Page Page +0.3* CCA CCA + 0.3* DD DDQ 0AV + 0.3* + 0.3* 18 33 Electrical Characteristics Electrical 121 3.6 LPV RTV V V Max. 3.8 AD AD1AV 1.2 1.2 150 125 Section 4 Section 40 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 40 40
− − − − − − Min. − 0 0 − − − −
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V I/O (PORT02 and I/O PORT05 I/O) V I/O (except PORT02 for I/O and PORT05 I/O) V I/O pins. V I/O pins.
1 1.8- 1.8- The voltageThe to be applied must be within the absolute maximum V). rating (1.5 The voltageThe to be applied must be within the absolute maximum V). rating (2.5 The voltageThe to be applied must be within the absolute maximum V). V18 rating (2.5 indicates the power supply voltage for 1.8- The voltageThe to be applied must be within the absolute maximum V). V33 rating (3.8 indicates the power supply voltage for 3.3-
4.1-
able Case temperature Storage temperature Analog input voltage (ADC unit A Analog input voltage (ADC unit B Junction temperature Input voltage (1.8- Input voltage (3.3- Input voltage (1.1- Input voltage (1.5- Input voltage (1.8- USB PHY SS section 0.8- USB PHY SS section3.3- USB3.0 transmitter power supply Item Note 2.
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V V V V V V V V V of
V/1.8- V/1.8- V/1.8- V/1.8- V/1.8- V/1.8- V/1.8- V/1.8- V/1.8- 82 3.3- selectable 3.3- selectable 3.3- selectable 3.3- selectable 3.3- 3.3- selectable selectable 3.3- selectable 3.3- selectable 3.3- selectable
Note
Page Page
V V V V V V V V V V V V V V Unit V V V V V V V V V V V
Electrical Characteristics Electrical
3.465/1.89 3.465/1.89 3.465/1.89 3.465/1.89 3.465/1.89 3.465/1.89 3.465/1.89 3.465/1.89 3.465/1.89 1.89 0.84 1.89 Max. 1.89 1.89 1.89 1.89 1.89 0.84 1.89 1.89 0.84 1.89 1.89 1.89 1.575 Section 4 Section
1.8 0.8 3.3/1.8 1.8 3.3/1.8 1.8 3.3/1.8 3.3/1.8 Typ. 1.8 3.3/1.8 3.3/1.8 1.8 1.8 1.8 0.8 3.3/1.8 1.8 1.8 0.8 1.8 3.3/1.8 1.8 1.8 1.5 3.3/1.8
1.71 0.76 3.135/1.71 1.71 3.135/1.71 1.71 3.135/1.71 3.135/1.71 1.71 3.135/1.71 3.135/1.71 1.71 1.71 1.71 0.76 Min. 3.135/1.71 1.71 1.71 0.76 1.71 3.135/1.71 1.71 1.71 1.425 3.135/1.71
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V OSC, 4.2-
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able VDD33 group
VDD18 group PORT15, PORT16, PORT17 I/O supplypower PORT09 I/O PORT15, PORT16, PORT17 pre- PORT08 I/O PORT09 pre PORT00 I/O PORT08 pre supply PORT1 PORT00 pre PORT10 I/O PORT11 pre PORT06 I/O power supply PORT10 pre PORT01(B), PORT04, PORT07, PORT21 I/O supplypower PORT06 pre PORT01(B), PORT04, PORT07, PORT21 pre PWC power I/O supply PORT01(A), PORT03 pre- PORT01(A), PORT03 I/O power supply RTC core power supply RTC I/O,RTC 1.5 PWC core power supply Item VDD08 core power supply
4.2 T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Note
Page Page
V V V V V V V V V V V V V V Unit V V V V V V V V V V V V V V V Electrical Characteristics Electrical
1.89 3.465 0.84 1.89 0.84 1.89 0.84 1.89 Max. 0.84 0.84 1.89 1.89 1.89 1.89 3.465 3.465 1.89 1.26 0.84 0.84 0.84 0.84 0.84 1.89 1.89 1.89 0.84 0.84 1.17 Section 4 Section
1.8 3.3 0.8 1.8 0.8 1.8 0.8 1.8 0.8 0.8 1.8 1.8 1.8 1.8 3.3 Typ. 3.3 1.8 1.2 0.8 0.8 0.8 0.8 0.8 1.8 1.8 1.8 0.8 0.8 1.1
1.71 3.135 0.76 1.71 0.76 1.71 0.76 1.71 0.76 0.76 1.71 1.71 1.71 1.71 3.135 3.135 1.71 1.14 0.76 0.76 Min. 0.76 0.76 0.76 1.71 1.71 1.71 0.76 0.76 1.06
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power supply power supply power supply power supply Vpower supply Vpower supply V V V V power supply V Rev.1.00
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able USB PHY SS section PHY USB 3.3- section HS PHY USB 0.8- USB PHY SS section transmitter power supply USB PHY SS section 0.8- section HS PHY USB 1.8- section HS PHY USB 3.3- PCIe PHY 0.8- PCIe PHY 1.8- MIPI DSI Tx PHY 0.8- MIPI DSI Tx PHY 1.8- MIPI DSI Tx PHY 1.2- LPDDR4 PHY 1.1- HDMI PHY 0.8 HDMI PHY 1.8 LPDDR4 core 0.8- LPDDR4 PLL 1.8 ADC unit B PHYCIF 0.8 PHYCIF 1.8 TSU ch.0 1.8 TSU ADC unit A TSU ch. 0 0.8 TSU ch.1 0.8 OTP 0.8 OTP 1.8 OTP PLL ch. 1, 2, 3, 4, 6, 7 0.8- PLL ch. 1, 2, 3, 4, 6, 7 1.8- VDD33 group Item
T R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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of 84 Page Page VDD PW
× 4 . 0 Electrical Characteristics Electrical µs None 10 rising .: .: 08 Min Max % Section 4 Section 90 Timing of both PWVDD and PWVDD % rising
10 08 No restriction on relative timing None .:
PWVDD Max , s m VDD 1 .: RT
Timing of either PWVDD or × Min 4
. 0
µs kHz OSC oscillation stabilization time - None 10 rising 32 .: .: .: 08
Min Max % Min 90
Timing of both RTVDD and RTVDD
% 10 Rev.1.00 On/Off (RTC/PWC) Sequence On/Off Procedures
-On Sequence (RTC/PWC) - No restriction on relative timing - Power
Power
08 1 Power 08 4.3-
RTVDD PWVDD RTRSTN PWRSTN PWVDD RTVDD igure F 4.3.1 4.3 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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of 85 Page Page % 10 Electrical Characteristics Electrical % 90 Section 4 Section µs No restriction on relative timing No restriction on None VDD 0 .: .: RT
×
Max Min 4 . 0 VDD RT
µs × None 0 6 . .: .: 0 falling Min Max 08 % 10 Timing of both PWVDD and PWVDD
% 90
No restriction on relative timing µs None 0 .: .:
Max Min
VDD
PW Rev.1.00
×
-Off Sequence (RTC/PWC) 4 . 0 Power
08 2 08 4.3- RTVDD PWVDD RTRSTN PWVDD PWRSTN RTVDD igure
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on - of 86 power
Page Page
Timing Timing.5 Timing.1 Timing.2 Timing.4 Timing.3 ) 18 Electrical Characteristics Electrical VDD USVPH
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: : :
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Table 4.3-2 2
, 1 Rev.1.00 On Sequence (other than for RTC/PWC) for than On (other Sequence f Sequence (other Sequence thanf for RTC/PWC)On/Of -
-On Sequence (other than for RTC/PWC) - Power Supply Name DSMSVDD18, PCVDD18, HDAVDD18, OTVDD18, LVRXAVCC, USVDDH VDD33, USVD330, USVPH DSMVDD12 USDVDD, USVP, USVPTX VDD08 LPVDDQ VDD18, LPVAA DSMSVDD0P8, V V V V V V V V V
) 8 3 2 8 1 8 8 8 8 ...... Various Power Supplies and Power On/Off Timings Power 0 3 1 0 1 1 1 0 0 - 4.3 Table Power
Table 4.3- , ,
Power Input
( 1
e 5 1 2 3 4 3 . . . . . 1 When controlled not by the System FW, the power is at Timing.5. on (off) When controlled by the System FW, connect the 0.8- addition, connect the PWMEMSWIENA pin of this LSI to an enable pin of this power switch. Se 4.3-
4.3-
RSTN LPVDD
Timing Timing Timing Timing Timing igure 0.8 V 1.8 V 3.3 V 1.2 V 1.8 V 0.8 V Power Voltage 0.8 V 1.1 V (off)timings.
Note 1. Table - 4.3 Table F Note: 4.3.2 4.3.2.1 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Page Page Timing.4 Timing.4 Timing.3 Timing Timing.1 Timing.1 Timing.3 Timing.1 Timing.3 Timing Timing.1 Timing.3 or Timing.1 Timing.2 or Electrical Characteristics Electrical
Section 4 Section 1), 0, 1), =
1 2 3 4 5 Case
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2 2 2 2 2 driver power supply and the I/O power supply are turned on at the same same the at on turned are supply power I/O the and supply power driver supply”. power I/O the then and first on turned is supply power driver - -
driver power supply and the I/O power supply must be turned on or off in case 1, 2, 2, 1, case in off or on turned be must supply power I/O the and supply power driver -
hepre 7), 1, 2, 3, 4, 6, TSnDVDD08A
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V switchingI/O. (n
1, - I/O powerI/O supply* Pre powerI/O supply* Pre powerI/O supply* Pre powerI/O supply* Pre powerI/O supply* Power Supply Name Pre = V I/O, they must be turned on on turned be must they I/O, V V I/O, “the pre “the I/O, V “t VI/O,
V/3.3 - Rev.1.00 driver power supply is turned on first and then the I/O power supply”. power I/O the then and first on turned is supply power driver V I/O, the pre the VI/O,
Power Supply Name PLDVDD08n PLVDDn (n PREDVDD33 Various Power Supplies and Power On/Off Timings(1.8 I/O) -V/3.3 Switching -V Various Power Supplies and Power On/Off Timings (PLL, TSU, ADC, etc.) V IO VI/O
3 2 NAPREDVDD, PAPREDVDD,PBPREDVDD, PCPREDVDD, SD0PREDVDD, SD1FVDD, IM0PREDVDD, IM1PREDVDD, GEPREDVDD NAMODVDD, PAMODVDD, PBMODVDD, PCMODVDD, SD0MODVDD, SD1FMODVDD, IM0MODVDD, IM1MODVDD, GEMODVDD
4.3- 4.3-
time” or “the pre- or “thetime” - 3.3 the as used When - 1.8 the as used When
● ● able
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Used as the 1.8- I/O VoltageI/O 0.8 V 1.8 V Power Voltage e1.8 th of supply power pre the on turning of order to the apply restrictions following The Note 1. Table T Note 2. - 1.8 the as used When - 3.3 the as used When 3. or
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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88 Page Page Min.: 0 µs Max.: None lectrical Characteristics lectrical 90% 90% 90% 1 E µs* Min.: 0 Max.: None 90% Section 4 Section 1 2 µs* 0 µs* 10% Min.: 0 Max.: None Min.: Max.: None
, GEPREDVDD) 90% 90% 90% 4 10% 10% 10% = 0, 1)) ), ADnAVCCA (n = 0, 1)) ) 18, LVRXAVCC,USVDDH 18)
.3-V IO)*
90% 90% 90% OTVDD08, LVRXAVDD)
1 µs µs* 0 µs Min.: 0 µs Max.: None Min.: 0 Max.: None Min.: 0 µs Max.: None Min.: Max.: None Min.: 0 µs Max.: None V (LPVAA, VDD Min.: 0 Max.: None µs , TSnAVDD18 (n = 0, 1 90% 4, 6, 7), TSnDVDD08A (n Min.: 0 Max.: None 3, 4, 6, 7)
PCVDD08, HDAVDD08, LPVDDQ), 1.8 = 1, 2, 3, 3
0.4 × VDD18 1.1 V (
33, USVD330, USVPH) USDVDD, USVP, USVPTX, LPVDD) (PREDVDD33)
V (VDD08), Rev.1.00 Off Sequence (other than for RTC/PWC) for than (other Off Sequence -
0.8 V (PLDVDD08n (n 1.8 V (PLVDDn (n = 1, 2, Pre-driver power supply (NAPREDVDD, PAPREDVDD, PBPREDVDD, PCPREDVDD, SD0PREDVDD, SD1FVDD, IM0PREDVDD, IM1PREDVDD 0.8 V ( 0.8 1.2 V (DSMVDD12) 3.3 V (VDD 0.8 V (DSMSVDD0P8, 18, HDAVDD18, OTVDD 1.8 V (DSMSVDD18, PCVDD 1.8 V IO power supply (NAMODVDD, PAMODVDD, PBMODVDD, PCMODVDD, SD0MODVDD, SD1FMODVDD, IM0MODVDD, IM1MODVDD, GEMODVDD) Power
RSTN (Input) Timing.3 Timing.5 Timing.2 Timing.4 Timing.4 Timing.1 Timing.1 Timing.3 Timing.1 Timing.4 Timing.3 PLL, ADC, TSU power supply* 1.8-V/3.3-V switching I/O power supply (when used as the 3 Timing.3 V) is (1.8 off and turned the power supply in the case of Timing.3 V) must (1.8 off be turned no less than 0 ns after the power supply in the case of Timin V) isg.4 (1.2 off. turned The powerThe supply in the case of Timing.2 V) must (0.8 off be turned no less than 0 ns the power after supply in the case of The power off time difference must be minimized.
ote:
Note 1. N 4.3.2.2 R01DS0372EJ0100 Apr 28, 2021 28, Apr RZ/VSeries, VisionAI_ASSP RZ/V2M
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Electrical Characteristics Electrical Section 4 Section driver supply power and the I/O power V supply. power power supply indicated are in the case of Timing.1 ning on the pre-
Vpower supplyand the 1.8- driverpower supply and the I/O - Vpower supply indicated are in the case of Timing.1 and Timing.3, respectively.
)
VI/O, and the pre VI/O, no restrictions apply the order of tur to
Rev.1.00
-Off Sequence (other than for RTC/PWC) driverpower supply must be turned off no less0 ns than the I/O after power supply is off. turned Vpower supply 1.8 and the - - - Power
4 and Timing.4, respectively. pre The When used as the- 1.8 supply. Timing.4 V) is (3.3 off. turned No restrictions apply to the order of turning off the 0.8- The 0.8 The This is used 3.3- as the The powerThe supply in the case of Timing.3 V) must (1.8 off be turned no less than 0 ns the power after supply in the case of 4.3-
Continuationof the previous page igure (
F Note 4. Note 3. Note 2. R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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90 Page Page V power supply - Electrical Characteristics Electrical Stable clock signals Analog input signals 90%
Section 4 Section 10% Min.: 0 µs, Max.: None 90% V power supplies have risen. 10% Unstable clock 100 mV
90% V power supply voltages (AD0AVCCA, AD1AVCCA) have risen. 10% Min.: 0 µs Max.: None On/PCI Reference Clock Input Timing - : Don’t Care timing limitationsfor power being turned on.
Rev.1.00 2
1 ADC Analog Inputs at Power 0.8 V (PCI) 1.8 V (PCI) 0.8 V (VDD08) 1.8 V (IO, AD)
Timing Limitationswhen Power is Turned being On
5 (PCVDD18) is risen. Analog input voltages should be kept below 100 mV the ADC before 1.8- Only apply analog input voltages the ADC after 1.8- the PCIeFor reference clock, the clock input signal the oscillationafter stabilizationthe PCI before 1.8 4.3-
Timing 2 Timing 3
s 123
of 91 2 2 -up* Page Page : Unknown value Electrical Characteristics Electrical -down, or pull Hi-Z, pull-down, or pull-up* Hi-Z, pull Section 4 Section 90% Max.: 10 µs 10%
90% Max.: 10 µs
10%
-On
)
Rev.1.00 O)
1 1 GPIOTiming at Power 3.3 V (I/O) 08 0.8 V (VDD 1.8 V (I/
6 external pins. (max.) have elapsed and the pin states stable. are pinThe states are not guaranteed between the supply voltages rising and the reset becoming effective. The stateThe depends on the pin. For the initial states of the respective pins, to refer “Initial Value in POR” the after list of After both the internal power and powerI/O supply voltages V 3.3 V) (1.8 or have risen, the reset is effective by 10 µ the time RSTN (Input) 4.3-
Timing 4 1.8 V GPIO (I/O)* 3.3 V GPIO (I/O)* Timing 1 igure
F Note 2. Note 1. R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123
15 15 of 6, AUI 6, AUI 92 TRDAT6 -
Page Page
7, CSI0, 15, TRACE0 - 11 7, CSI0, TRDAT6 - 15, TRACE0 - 11 - - Electrical Characteristics Electrical : SDR10SDIO 4 : SDIO SDR104
: SDIO SDR104
: P0600 - : eMMC HS200 : PWM0 - : PWM8 -
DD
DD
: P0600 - : eMMC HS200 1, DEBUG : PWM0: PWM8: DD DD DD DD DD DD DD DD DD DD DD DD DD
DD DD : SDIO SDR104 1
* 2 DD
* Section 4 Section DD08 DD : IIC0 -
DD08 DD DD18 RTV Note PCPREDV NAPREDV PAPREDV PBPREDV PAMODV PBMODV SD1FV GEPREDV GEMODV PCMODV IM0PREDV IM1PREDV NAMODV PWV IM0MODV IM1MODV SD0PREDV V The currentThe must within be the maximum supply current. SD0MODV SD1FMODV RTV PWV
A A µ mA mA Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA µ mA
3
1 2 300* 2 1 23 16 Max. 1 1 17 11 1 1 10 3 4 4 1 3 4770 16 16 700 1 ) /2 (1
DD18 DDIM1PRE DDIM1MOD DDNAPRE DDNAMOD DDSD0PRE DDSD0MOD DDSD1F DDSD1MOD DDGEPRE DDGEMOD DDPAPRE DDPAMOD DDPBPRE DDPBMOD DDPCPRE DDPCMOD DDIM0PRE DDIM0MOD DD08 DDRTVDD08 DDRTVDD DDPWVDD08 DDPWVDD Symbol I I I I I I I I I I I I I I I I I I I I I I I I
-
driver power power supplypower PORT21 pre PORT21 I/O current current current current current current -
pre
driver supplypower - Rev.1.00 power supply current
haracteristics power supply power current current C power supply current
Max. Supply Currents during Operation
Maximum Current Supply
I/O
Supply Current driver power supply driver power supply driver power supply driver power supply driver power supply driver power supply V OSC ------power supply current power supply current power supply current power supply current power supply current power supply current
DC 1 7 I/O) 8 I/O 0 I/O
current V OSC, 4.4-
PORT05 I/O, PORT20 I/O. 1.8- RSTN I/O, debugger I/O, MD0- (PORT02 I/O,
PORT15, PORT16, PORT17 I/O current VDD18 group PORT09 I/O PORT15, PORT16 , PORT17 PORT08 pre PORT0 PORT09 pre PORT00 pre PORT00 I/O driver power supply PORT1 PORT11 pre PORT11 I/O supply PORT06 pre PORT06 I/O PORT10 pre PORT01(B), PORT04, PORT07, PORT01(A), PORT03 I/O PORT01(B), PORT04, PORT07, PWC core power supply current PWC power I/O supply current PORT01(A), PORT03 pre supplypower current RTC core RTC power supply current I/O,RTC 1.5 Item VDD08 core power supply current current
Conditions for the supply current: Power supply voltage = Max. value, Tj = −40 to 125ºC to −40 = Tj value, Max. = voltage supply Power current: supply the for Conditions Table 4.4.1 4.4.1.1 4.4 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 , of , DD4 DD083 93 DV
, PLV , PL PTX DD3 DD087 Page Page
DV DD082
, PLV , USV P PH , PL DD2
Electrical Characteristics Electrical
, PLDV DD086
, USV , USV V
, PLV DD DD081 D330 DD7
DD1
DV
DV
, PLD
DD CC
DD0P8 DD18 DD33
CCA CCA : 3200 Mbps DD08A DD08A DD18 DD18 , PLV DD12 : 3200 Mbps DD08 DD18 : 3200 Mbps DD084 Section 4 Section
DD08 DD18 DDH DD08 DD18 DD AA DDQ DD6 DV DD33 Note PREDV LPV TS0DV TS1DV TS0AV TS1AV PLV PL AD0AV AD1AV LPV HDAV HDAV OTV OTV PCV PCV Total of US USV Total of USV V LVRXAV LVRXAV LPV DSMSV DSMSV DSMV Total of PL Total of PLV
mA mA Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2 314 1 1 4 4 1 1 6 Max. 24 10 188 132 88 21 57 9 60 20 127 81 465 2 30 8 16 14 ) /2 (2
DDPC08 DDPC18 DDUS08 DDUS18 DDUS33 DDLVVDD DDLVVCC DDLPVDD DDLPVAA DDLPVDDQ DDHD08 DDHD18 DDDSM08 DDDSM18 DDDSM12 DDPL08 DDPL18 DDOT08 DDOT18 DDTS08 DDTS08 DDTS18 DDTS18 DDAD0 DDAD1 DD33 DDPRE33 I I I I I Symbol I I I I I I I I I I I I I I I I I I I I I I
V OSC power supply (at current normal temperature at 1.5 V): 10 µA
current current
current
current current current up resistance 10kΩ, is 1.5 V/10kΩ = 150 µA
-
current current current
current current current up resistor, so this amount of mustcurrent be taken into account when the currentis drawn estimated. current current - current current current current current current current current current current current
V power supply V power supply Rev.1.00 current current
power supply power supply power supply V V V driver power supply V power supply V power supply - V power supply - power supply power supply power power supplypower supplypower Max. Supply Currentsduring Operation
power supplypower power supplypower supplypower
V supply power V supply power V V I/O power supply pre - - V V
V supplypower V supplypower V supplypower V supplypower V V V - - - -
V power supply V power supply
- -
[Example] When pull the
1.8- 1.8-
1 Reference value the RTCfor core supplypower current (at normal temperature at 0.8 V): 35 µA
Reference value the RTCfor I/O, 1.5- In normal operation (when the power supplies than for other the RTC power domain turned are on), flowscurrent to the PWISO pin via a pull V power supply V power supply - -
4.4-
PORT13 I/O, PORT13 I/O, PORT14 I/O, PORT14 I/O, PCIe I/O, PCIe I/O, USB I/O, LSI test I/O) USB I/O, LSI test I/O) (PORT12 I/O, (PORT12 I/O,
USB PHY 3.3- USB PHY 0.8- USB PHY 1.8- MIPI DSI Tx PHY 1.2- PCIe PHY 0.8- PCIe PHY 1.8- HDMI PHY 1.8 MIPI DSI Tx PHY 0.8- MIPI DSI Tx PHY 1.8- LPDDR4 PHY 1.1- HDMI PHY 0.8 CIF PHYCIF 1.8 LPDDR4 core 0.8- LPDDR4 PLL 1.8 ADC unit A ADC unit B PHYCIF 0.8 TSU ch. 0 1.8 TSU ch. 1 1.8 OTP 1.8 OTP TSU ch. 0 0.8 TSU ch. 1 0.8 PLL ch. 1, 2, 3, 4, 7 1.8- 6, 0.8 OTP PLL ch. 1, 2, 3, 4, 7 0.8- 6, VDD33 group VDD33 group Item
Note 1. Table Note 2. Note 3. R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123
=
of DD
& V
max & 94
max & 4),
max max max max & DD SS
-on -on -off & on -on -on roup)
DD SS DD DD SS SS SS SS DD DD = V = V
and = V
= V = = V = V = V = V = V = V = = V = V =
_tol power power power power power Page Page
33 3,
in33 DD in18_tol DD in18 in33 in15 in18 in33 in18 in18 DD in15 DD in18 DD V I/O g -V V V V V V V
Vin V V V — V Condition — — V V V V V V 2,
1,
Electrical Characteristics Electrical V (3.3 A A A A A A A A A A A A A A A A A A A A A µ µ µ µ V V V V Unit µ µ µ µ µ V V V V V µ µ µ µ µ µ µ µ µ µ µ µ roups
g DD
+ 0.3
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=
V (1.8
DD V
— — — — — — — — — — — — — — Typ. — — — — — — — — — — — — — — — — 2), to 1.95
DD DD DD V DD DD DD DD and V
× 1
1.65 0.3 12 12 12 12 12 25 35 25 12 12 18 18 12 18 18 9 25
− − − − 25 25 35 25 — − − 0.1 × V 0.1 × V × 0.08 0.08 × V × 0.08 0.1 × V 0.1 × Min. 0.08 × V × 0.08 0.1 − − − − − − − − − − − − 0.7 × V 0.7 × =
roups DD g
V V TOL IH IL
IL IL IL IH IH IH IH IH IH IH IL IL IL IL IL IL IL IL IL IH IH I/O I I I I I I V ΔV ΔV I I I I ΔV I I I ΔV V V I I I I I I Δ Δ I Symbol I
6 7 6 7 6 7 7 6 7 6 switching V I/O group ), V I/O -V
4 3 4 5 4 5 2 3 5 2 3 5 4 4 2 3 4
8 8 8 1 8 8 1 V (I.5 1
group* group 1* group
V (3.3/1.8-V V switching I/O Vswitching group 1* I/O Vswitching group 2* I/O Vswitching group 1* I/O Vswitching group 2* V switching I/O Vswitching group 2* V switching I/O Vswitching group 1* I/O Vswitching group 2* I/O Vswitching group 1* V switching I/O Vswitching group 1* V switching I/O Vswitching group 2* ------V to 1.65 -V I/O group 3* -V I/O group 3* -V I/O group 2* -V I/O -V I/O group 2* -V I/O group 2* -V I/O group 2* -V I/O group* -V I/O group* -V I/O group 3* -V I/O group* -V I/O group 4* -V I/O group* -V I/O group 1* -V I/O group* -V I/O group 3* -V I/O group* -V I/O group 1* -V I/O group 3* -V I/O group 3* -V I/O group 4* -V I/O group 4* -V I/O -V I/O group 4*
1.8 1.8 1.8 1.5 1.8 1.8 1.8 3.3/1.8 3.3/1.8 3.3 3.3/1.8 3.3/1.8 3.3 1.8 3.3/1.8 3.3 1.8 — — 3.3/1.8 3.3/1.8 3.3 1.8 3.3/1.8 3.3 1.8 1.5 1.8 1.8 group* I/O 1.5V 1.8 1.8 1.8 3.3/1.8 1.8 1.8 3.3/1.8
Rev.1.00
1.35
V to 3.60 =
Characteristics
DD down -down -down buffer) DC V 1.65
tandard I/O Characteristics
S
2
4.4- tolerant tolerant buffer) input tolerant input input tolerant - - level current input -level current input -level level current input -level level voltage input -level
level current input -level current input -level level current input -level level voltage input -level (Input buffer with pull with buffer (Input resistor) buffer) input (Tolerant pull with buffer (Input resistor) (Non
Low Low
Low
High buffer) input (Tolerant High
High (Non
High Low voltage Hysteresis Item External tolerance voltage
Table 4.4.2 pins. external of list the in numbers group pin multiplexed the to refer groups, I/O the For R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 11 9.6 9.6 − − − mA mA rive rive rive rive
mA
18mA of (d (d (d −
7.8/ 6.4/ 6.4/ 12mA 10mA 12mA − − − − − −
13/ mA mA
95
8/ 7/ 8/ −
3.8/ 3.2/ 3.2/ − − − − − − haracteristics 4/ 6/ 11/ 4/
mA mA X1/X2/X4/X6) X1/X2/X4/X6) X1/X2/X4/X6) − − − −
1.8mA - 3.8mA 1.8/ 1.6/ 1.6/ 2/ 5/ 9/ 2/ − − − − − − − − − 1.8 3.8 1.8/3.8/7.8/11 1.6/3.2/6.4/9.6 1.6/3.2/6.4/9.6 2/4/8/12 2/4/8/12
Page Page rive strength strength (drive strength (drive strength (drive ======5/6/7/10= mA mA 9/11/13/18 = =
OL OL OL OL OL OL OL OL OL OH OH OH OH OH OH OH OH OH rive strength strength (drive X1/X2/X4/X6) strength (drive X1/X2/X4/X6) strength (drive X1/X2/X4/X6) I I I I I I I I I I I I I I I I I I Condition strength strength strength (drive X1/X2/X4/X6) strength — — — — — — — mA X1/X2/X4/X6) mA X1/X2/X4/X6) mA X1/X2/X4/X6) rive strength strength (drive X1/X2/X4/X6) strength (drive X1/X2/X4/X6) strength (drive X1/X2/X4/X6) rive strength strength (drive X1/X2/X4/X6)
ElectricalC
V V V V V V V V V V Unit V V V V V V V V kΩ kΩ kΩ kΩ kΩ kΩ kΩ
DD DD DD DD DD DD DD DD DD V V V V V V V
× × × × × × ×
DD DD DD DD DD DD DD DD DD Section 4 Section 0.2 0.2 0.2 0.2 0.2 0.2 V 0.2 × 0.2×V 0.2 V Max. V V V V V V V V 92 72 83 47 49 49 83
— — — — — — — — — — Typ. — — — — — — — — — — — — — — —
DD DD DD DD DD DD DD DD DD V V V
× × ×
0 0 0 0 0 0 0 0 0 Min. 0.8 × V 0.8× V 0.8× V 0.8 × V 0.8 × 0.8 0.8 0.8 0.8×V V 0.8 × 12 18 15 11 11 11 15
PU PU PU PU PU PU PU OL OL OL OL OL OL OL OL OL OH OH OH OH OH OH OH OH OH R R V V V V V V R V V V V V V V V R R R R V V V V Symbol
3 4 5 2 3 4 4 2 3
8 8 8 1 1
switching I/O group 1 1 I/O group switching
V I/O Vswitching group 1 I/O Vswitching group 2 I/O Vswitching group 2 V switching I/O Vswitching group 1 I/O Vswitching group 1 I/O Vswitching group 2 I/O Vswitching group 2 V switching I/O Vswitching group 2 V switching I/O Vswitching group 1 I/O Vswitching group 1 I/O Vswitching group 2 6 6 7 7 6 6 7 7 7 6 6 7 ------V I/O group* -V I/O group* -V I/O group 2* -V I/O group 3* -V I/O group* -V I/O group* -V I/O group* -V I/O group 1* -V I/O group 2* -V I/O group 3* -V I/O group 3* -V I/O group 1* -V I/O group 2* -V I/O group 4*
1.5 3.3 1.8 1.8 3.3/1.8 V)* (1.8 3.3/1.8 V)* (3.3 3.3/1.8 V)* (1.8 3.3/1.8 V)* (3.3 3.3 1.5 3.3/1.8 V)* (1.8 3.3/1.8 V)* (3.3 3.3/1.8 V)* (1.8 3.3/1.8 V)* (3.3 3.3/1.8 V)* (3.3 3.3 1.8 1.8 1.8 1.8 3.3/1.8 V)* (1.8 3.3/1.8 V)* (3.3 3.3/1.8 V)* (1.8 1.8 1.8 1.8
Rev.1.00
output voltage output
level voltage output -level
-level
-upPull resistance
Low
Item High
R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Page Page Condition — — — — — —
PORT10 I/O,
Electrical Characteristics Electrical
Unit pF kΩ kΩ kΩ kΩ kΩ kΩ
Section 4 Section Max. 10 45 45 75 92 87 75
Typ. — — — — — — — , PORT17 I/O
— Min. 12 12 20 13 24 20
PD PD PD PD PD PD in R R R R R C Symbol R V OSC
4 5
8 4*
, debugger I/O
group group
V switching I/O Vswitching group 2 I/O Vswitching group 2 V switching I/O Vswitching group 1 I/O Vswitching group 1 6 7 7 6 7 I/O - - - - V OSC, RTC I/O -V I/O group* -V I/O group 3*
— 3.3/1.8 V)* (1.8 3.3/1.8 V)* (3.3 3.3 1.8 3.3/1.8 V)* (1.8 3.3/1.8 V)* (3.3 1.8V I/O 1.8V
Rev.1.00
Target I/OTarget group: 1.5- Target I/OTarget group: PWC I/O I/OTarget group: PORT20 I/O, RSTN I/O, 1.8- Target I/OTarget group: PORT02 I/O, PORT05 I/O I/OTarget group: MD0- Target I/OTarget group: PORT01(A) I/O, PORT03 I/O, PORT01(B) I/O, PORT04I/O, PORT07 PORT21 I/O, PORT06I/O, I/O, PORT11 I/O Target I/OTarget group: PORT00 I/O, PORT08 I/O, PORT09 PORT15 I/O, PORT16I/O, I/O Target I/OTarget group: PORT12 I/O, PORT13 I/O, PORT14 PCIe I/O, I/O, USB LSI test I/O, I/O
Inputcapacitance
Item resistance -down Pull
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of 97
Page Page /2, (max.)
DD OL Electrical Characteristics Electrical , V , IL Section 4 Section /2,SD0MODV (min.), V
DD OH , V , IH /2,V DD /2,PCMODV DD /2,IM1MODV
/2,PBMODV DD
DD
nditions
/2, GEMODV /2, /2,PAMODC
DD DD
Rev.1.00
= 20pF not if otherwisestated
/2,IM0MODV L /2, NAMODV /2, Characteristics DD DD33
AC /2,V
DD18 (Refer to the corresponding timing charts.) timing corresponding the to (Refer ad:C lo Output I/O signal referenceI/Olevels: signal V SD1FMODV
● ●
4.5 co measurement ACcharacteristics R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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98 P
Page Page Note
SSTO t Electrical Characteristics Electrical
HIGH Unit ns ns ns ns ns ns ns ns ns t SDAT t Section 4 Section Max. — — — — — — 900 — —
Sr Typ. — — — — — — — — —
SSTA t 600 100 600 Min. 600 2500 600 0 1300 1300
HDAT t
cyc LOW HIGH BUF HSTA SSTA SSTO SDAT HDAT Symbol t t t t t t t t t
cyc t
LOW t
BUF
HSTA t t S
Rev.1.00
P condition Timing Timing
C C I I I I
epeated START condition
IIC Bus Interface
R
START STOP condition 1
1 S: P: Sr: SCL SDA n = 0 to 3 2 2 4.5- I I 4.5-
igure I2SDAn setup time I2SDAn hold time Start condition hold time Restart condition setup time Stop condition setup time I2SCLn high level width Bus time free (time start from to stop condition) Item I2SCLn cycle time I2SCLn low level width F Note: Note: 4.5.1 Table R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
1 1 123
of 99
Page Page
1 Note *
Falling edge mode*
Risingmode edge * Electrical Characteristics Electrical
Unit ns ns ns ns ns ns Section 4 Section Max. 7.5 — — — — — . HIGH LOW t t
(Min.) — Typ. — — — — — DTXD t
cyc t 9
− 5.0 LOW − 18 Min. 5.0 t 41.66 18 HRXD t LOW HIGH t t
cyc LOW t HIGH DTXD SRXD HRXD t t t t t Symbol (CSI)
SRXD t
= 20 pF (Max.) L
DTXD ) ) ) t
@C
Rev.1.00
= X4 15 pF, L aster Mode aster @C Master Mode Timing Master Mode Timing
wire serial interface (CSI) should be used with a driving ability of at least X2 M
Clocked Serial Interface
2 2 Select one of the driving abilities listed below according to the load capacitance. X2 The 3- The (Input) (Output) (Output) CSTXDn (Output) CSRXDn CSSCLKn CSSCLKn n = 0 to 5 4.5-
4.5- Inverted clock
igure CSRXDn hold time (CSSCLKn rising and falling edges CSTXDn output delay time (CSSCLKn rising and falling edges CSSCLKn output high level width CSRXDn setup time (CSSCLKn rising and falling edges CSSCLKn cycle time CSSCLKn output low level width Item F Note 1.
Note: Table 4.5.2 4.5.2.1 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123 of
100
1 Page Page Note Risingmode edge
*
Falling edge mode
HCS t Electrical Characteristics Electrical
Unit ns ns ns ns ns ns ns ns Section 4 Section Max. — — 10.5 — — — — — . HIGH LOW t .) t
Min (
Typ. — — — — — — — — DTXD t cyc t
5.0 HRXD t 18 41.66 − 84 Min. 18 5.0 7.5 21 LOW HIGH t t
cyc LOW HIGH SRXD HRXD SCS HCS DTXD t t t t t t Symbol t t .)
SRXD t Max
(
DTXD t
= 20 pF
L
SCS
t ) ) )
@C
Rev.1.00
Mode Timing = X4 15 pF, L
) @C Slave Slave Mode Timing ) ) ) )
wire serial interface (CSI) should be used with a driving ability of at least X2 Slave Mode
3 Input Input Input Input ( ( 3 ( ( Output
Select one of the driving abilities listed below according to the load capacitance. X2 The 3- The ( CSCSn
CSTXDn CSRXDn CSSCLKn CSSCLKn n＝0 to 5 4.5- Inverted clock
n setup time n hold time 4.5-
CS CS igure CSTXDn output delay time (CSSCLKn rising and falling edges CS (CSSCLKn rising and falling edges) CS (CSSCLKn rising and falling edges) CSRXDn hold time (CSSCLKn rising and falling edges CSSCLKn input high level width CSRXDn setup time (CSSCLKn rising and falling edges Item CSSCLKn cycle time CSSCLKn input low level width F Note 1.
Note: 4.5.2.2 Table R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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of 101 HRXV
t Page Page Note
Electrical Characteristics Electrical
Unit ns ns ns ns ns ns ns ns ns ns CRC CRC Section 4 Section Max. — — — — — 40.5 25 40.5 25 —
— — Typ. — — — 40 — 40 — — DATA DATA 10 10 10 10 10 39.5 0 Min. 39.5 0 10
HRER Tcyc DTXE DTXD Rcyc SRXV HRXV SRXD HRXD SRER Symbol t t t t t t t t t t
HRXD t
SFD DTXD t
SFD
SRXD
t cyc R t
SRXV t Preamble Preamble Rev.1.00 Tcyc t
DTXE t 100-Mbps Ethernet Mode Timing Reception Timing (Normal) Transmission Timing Transmission Mbps Ethernet Mode 100-Mbps Ethernet
Ethernet MAC interface (ETHER)
5 4 4 4.5- 4.5- 4.5- GERXD GERXC GETXC GETXD GECOL GECRS
GERXER GERXDV GETXER GETXEN igure igure GERXER setup time GERXER hold time GERXDV hold time GERXD setup time GERXD hold time GETXD outputGETXD delay time GERXC cycle time GERXDV setup time GETXC cycleGETXC time GETXEN output delay time Item F
F Table 4.5.3 4.5.3.1 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
ics 123
of 102 Page Page Electrical Characterist Electrical Section 4 Section XXX HRER t
SRER t DATA
SFD
Preamble Rev.1.00
Reception Timing (in Cases of Error)
6 4.5- GERXC GERXD GERXDV GERXER igure
F R01DS0372EJ0100 Apr 28, 2021 28, Apr RZ/VSeries, VisionAI_ASSP RZ/V2M
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of 103 HGRXV
t Page Page
Note
Electrical Characteristics Electrical
CRC ns ns ns ns ns MHz ns ns ns Unit ns % ns CRC
Section 4 Section — — — 5.5 — 125 + 100 ppm — — 8.5 Max. 5.5 55 8.5
— — — — — — — — Typ. 8 — 50 8
DATA DATA 100 ppm 0.5 2.5 2.5 0.5 2.5 125 − 0.5 0.5 Min. 7.5 0.5 45 7.5
HGRXD t
SFD DGTXD t HGRER REF125CK DUTY GTcyc DGTXE DGTXD GRcyc SGRXV HGRXV SGRXD HGRXD SGRER f t t t t t I t t t t t Symbol
SFD
SGRXD t GRcyc t cyc Preamble
SGRXV t GT Preamble t DGTXE Rev.1.00 t
-GbpsEthernet Mode Timing Gbps Ethernet Mode -Gbps 1 Reception Timing (Normal) Transmission Timing Transmission 1
8 7 5 4.5- 4.5- GETXD GECOL 4.5- GECRS GETXER GETXEN GERXD GERXC
GERXER GERXDV GEGTXCLK igure igure GERXER setup time GERXER hold time GERCDV hold time GERXD setup time GERXD hold time GETXD outputGETXD delay time GERXC cycle time GERXDV setup time GEGTXCLK cycle time GETXEN output delay time Item GECLK input frequency GECLK input duty ratio F
F 4.5.3.2 Table R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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of 104 Page Page Electrical Characteristics Electrical Section 4 Section XXX HGRER t
SGRER t DATA
SFD
Preamble Rev.1.00
Reception Timing (in Cases of Error)
9 4.5- GERXC GERXD GERXDV GERXER igure
F R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
123
) ) ) ) ) ) of DD DD DD DD DD DD
105
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C C
. Electrical Characteristics Electrical
ns ns Unit Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Section 4 Section Max. Max. 1 3 — — — 1 3 — — 10 — 0.9 2.5 — — — —
. — — Typ. Typ. — — — — — — — — — — — — — — — X2 6.5 1.5 — — 4.0 — 2.88 Min. Min. — — 6.5 1.5 20 5 − 2.0 − — 6.5 1.5
LOW HIGH r f DDAT SDAT HDAT f DDAT SDAT HDAT WDAT cyc cyc LOW HIGH r t t Symbol Symbol t t t t t t t t t t t t t t t
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C Electrical Characteristics Electrical
ns ns ns Unit ns ns ns HRXD t
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F Note: Table 4.5.6 4.5.6.1 R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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ns ns Unit ns ns
Section 4 Section × 0.55 × 0.55 × LOW HIGH t t cyc cyc t t Max. — 3 cyc t
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F Note: Table R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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SSTO t Page Page Note
HIGH t SDAT t Electrical Characteristics Electrical
Unit ns ns ns ns ns ns ns ns ns Section 4 Section Max. — — — — — — 900 — — Sr
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C Electrical Characteristics Electrical
ns ns ns Unit ns ns ns 4 HRXD t
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ns ns ns Unit ns ns ns HRXD t
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F 4.5.9 Table R01DS0372EJ0100 RZ/VSeries, VisionAI_ASSP RZ/V2M Apr 28, 2021 28, Apr
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Page Page
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Electrical Characteristics Electrical
Unit ns ns ns ns DTDO t Section 4 Section Max. 8 — — —
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121 Page Page REVISIONHISTORY Datasheet
Summary Description RZ/V Series, VisionAI_ASSP RZ/V2M
First Edition issued
Page Rev.1.00
Date Apr 28, 2021
REVISION HISTORY 1.00 Rev.
REVISIONHISTORY RZ/VSeries, VisionAI_ASSP RZ/V2M R01DS0372EJ0100 Apr 28, 2021 28, Apr
General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.
Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples. 3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export, manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, if required. 5. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering. 6. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document. 7. No semiconductor product is absolutely secure. Notwithstanding any security measures or features that may be implemented in Renesas Electronics hardware or software products, Renesas Electronics shall have absolutely no liability arising out of any vulnerability or security breach, including but not limited to any unauthorized access to or use of a Renesas Electronics product or a system that uses a Renesas Electronics product. RENESAS ELECTRONICS DOES NOT WARRANT OR GUARANTEE THAT RENESAS ELECTRONICS PRODUCTS, OR ANY SYSTEMS CREATED USING RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (“Vulnerability Issues”). RENESAS ELECTRONICS DISCLAIMS ANY AND ALL RESPONSIBILITY OR LIABILITY ARISING FROM OR RELATED TO ANY VULNERABILITY ISSUES. FURTHERMORE, TO THE EXTENT PERMITTED BY APPLICABLE LAW, RENESAS ELECTRONICS DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, WITH RESPECT TO THIS DOCUMENT AND ANY RELATED OR ACCOMPANYING SOFTWARE OR HARDWARE, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. 8. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 12. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 13. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 14. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.5.0-1 October 2020)
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