DOCSLIB.ORG

Intel® Quark™ Soc X1000 Core Hardware Reference Manual April 2014 2 Order Number: 329678-002US Revision History—Intel® Quark™ Core

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Intel® Quark™ Soc X1000 Core Hardware Reference Manual April 2014 2 Order Number: 329678-002US Revision History—Intel® Quark™ Core Intel® Quark™ SoC X1000 Core Hardware Reference Manual April 2014 Order Number: 329678-002US INFORMATIONLegal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725, or go to: http://www.intel.com/design/literature.htm Any software source code reprinted in this document is furnished for informational purposes only and may only be used or copied and no license, express or implied, by estoppel or otherwise, to any of the reprinted source code is granted by this document. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to: http://www.intel.com/products/processor_number/ Code Names are only for use by Intel to identify products, platforms, programs, services, etc. (“products”) in development by Intel that have not been made commercially available to the public, i.e., announced, launched or shipped. They are never to be used as “commercial” names for products. Also, they are not intended to function as trademarks. Intel, Quark, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2014, Intel Corporation. All rights reserved. Intel® Quark™ SoC X1000 Core Hardware Reference Manual April 2014 2 Order Number: 329678-002US Revision History—Intel® Quark™ Core Revision History Date Revision Description Removed non-relevant Clocking Considerations (formerly Section 9.1). April 2014 002 Updated with trademarked term: Intel® Quark™ Core. September 2013 001 First external release of document. Intel® Quark™ SoC X1000 Core April 2014 Hardware Reference Manual Order Number: 329678-002US 3 Intel® Quark™ Core—Contents Contents 1.0 About this Manual ..................................................................................................... 9 1.1 Manual Contents................................................................................................. 9 1.2 Notational Conventions.......................................................................................10 1.3 Special Terminology ...........................................................................................11 1.4 Related Documents ............................................................................................11 2.0 Introduction ............................................................................................................12 2.1 Intel® Quark™ Core Features ..............................................................................12 2.2 Intel® Quark™ Core Product ...............................................................................14 2.2.1 Operating Modes and Compatibility ...........................................................14 2.2.2 Memory Management..............................................................................14 2.2.3 On-chip Cache........................................................................................14 2.2.4 Floating-Point Unit ..................................................................................15 2.3 System Components ..........................................................................................15 2.4 System Architecture...........................................................................................15 2.5 Systems Applications .........................................................................................16 2.5.1 Embedded Personal Computers.................................................................16 2.5.2 Embedded Controllers .............................................................................17 3.0 Internal Architecture ...............................................................................................18 3.1 Instruction Pipelining..........................................................................................21 3.2 Bus Interface Unit..............................................................................................21 3.2.1 Data Transfers .......................................................................................22 3.2.2 Write Buffers..........................................................................................22 3.2.3 Locked Cycles ........................................................................................23 3.2.4 I/O Transfers .........................................................................................23 3.3 Cache Unit........................................................................................................24 3.3.1 Cache Structure .....................................................................................24 3.3.2 Cache Updating ......................................................................................25 3.3.3 Cache Replacement.................................................................................26 3.3.4 Cache Configuration................................................................................26 3.4 Instruction Prefetch Unit .....................................................................................27 3.5 Instruction Decode Unit ......................................................................................27 3.6 Control Unit ......................................................................................................28 3.7 Integer (Datapath) Unit ......................................................................................28 3.8 Floating-Point Unit .............................................................................................28 3.8.1 Intel® Quark™ Core Floating-Point Unit .....................................................28 3.9 Segmentation Unit .............................................................................................28 3.10 Paging Unit .......................................................................................................29 4.0 Bus Operation ..........................................................................................................31 4.1 Data Transfer Mechanism ...................................................................................31 4.1.1 Memory and I/O Spaces ..........................................................................31 4.1.1.1 Memory and I/O Space Organization............................................32 4.1.2 Dynamic Data Bus Sizing .........................................................................33 4.1.3 Interfacing with 8-, 16-, and 32-Bit Memories.............................................34 4.1.4 Dynamic Bus Sizing During Cache Line Fills ................................................38 4.1.5 Operand Alignment .................................................................................39 4.2 Bus Arbitration Logic ..........................................................................................40 4.3 Bus Functional Description ..................................................................................43 4.3.1 Non-Cacheable Non-Burst Single Cycle ......................................................43 4.3.1.1 No Wait States..........................................................................43 4.3.1.2 Inserting
Load more

Recommended publications
  • Fog Gateways:The Cornerstone of Iot Security
    WHITE PAPER Fog Gateways: The Cornerstone of IoT Security Fog Gateways: The Cornerstone of IoT Security By Nicholas Cravotta The IoT offers tremendous value, safety. Utilities can dynamically change rates and shift loads—thus preventing overinvestment in power but also introduces major security generation. IoT-based medical devices can monitor challenges. Connecting previously offline patients continuously to identify trends and alert systems increases the attack surface for hackers— caregivers before an emergency arises. and the diversity of these systems makes it difficult to But all these benefits depend on secure data flow. deploy and manage consistent security. If the network is compromised, the result can be The nature of internal networks—such as the automation disastrous. For industrial applications, the cost could be networks that connect factory machinery—add to the the shutdown of operations or equipment damage. In a problem. Legacy networks provide minimal authorization, utilities environment, invalid data could result in black- little authentication, and not enough encryption. There outs and lost revenue. For retail applications, security is often no protection against intrusion, unauthorized breaches could halt sales and expose customer data. reconfiguration of edge equipment, or DDoS attacks. If an attacker gains access to these unsecure networks, the What Makes IoT Security Different entire organization can be at risk. In some ways, security concerns are nothing new. Most Fog computing can address these security issues today organizations already have security precautions in place and help you prepare for new challenges on the horizon. to protect sensitive IT systems and physical assets. But Fog gateways provide secure connectivity to local equip- the IoT introduces new threats that can catch businesses ment, intelligent data processing, and end-to-end off guard.
    [Show full text]
  • INTEL CORPORATION (Exact Name of Registrant As Specified in Its Charter) Delaware 94-1672743 State Or Other Jurisdiction of (I.R.S
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-K (Mark One) x ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2016. or ¨ TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to . Commission File Number 000-06217 INTEL CORPORATION (Exact name of registrant as specified in its charter) Delaware 94-1672743 State or other jurisdiction of (I.R.S. Employer incorporation or organization Identification No.) 2200 Mission College Boulevard, Santa Clara, California 95054-1549 (Address of principal executive offices) (Zip Code) Registrant’s telephone number, including area code (408) 765-8080 Securities registered pursuant to Section 12(b) of the Act: Title of each class Name of each exchange on which registered Common stock, $0.001 par value The NASDAQ Global Select Market* Securities registered pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes x No ¨ Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes ¨ No x Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.
    [Show full text]
  • Wind River Linux 5.X and Intel Gateway Solutions for Iot
    Subject to Wind River Terms of Use - Do Not Copy – Do Not Distribute EDUCATION SERVICES Wind River Linux 5.x and Intel Gateway Solutions for IoT Version 1.0 A LECTURE GUIDE Volume 1 of 2 Subject to Wind River Terms of Use - Do Not Copy – Do Not Distribute LECTURE GUIDE Wind River Linux 5.x and Intel Gateway Solutions for IoT, Version 1.0 A Education Services Production Date: October 2014 Copyright c 2014 Wind River Systems, Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means without the prior written permission of Wind River Systems, Inc. Wind River, Tornado, and VxWorks are registered trademarks of Wind River Systems, Inc. The Wind River logo is a trademark of Wind River Systems, Inc. Any third-party trademarks refer- enced are the property of their respective owners. For further information regarding Wind River trademarks, please see: http://www.windriver.com/company/terms/trademark.html Wind River may refer to third-party documentation by listing publications or providing links to third-party Web sites for informational purposes. Wind River accepts no responsibility for the information provided in such third-party documentation. This document is designed to support the Wind River Linux 5.x and Intel Gateway Solutions for IoT course. It is not designed as a stand-alone document, nor is it intended as a substitute for documentation that accompanies Tornado, VxWorks, or Wind River Workbench or any other Wind River Systems, Inc. software or hardware product. http://education.windriver.com Education Services Department Wind River Systems, Inc.
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
    Case 2:16-cv-02026-DMF Document 1 Filed 06/22/16 Page 1 of 25 1 AIKEN SCHENK HAWKINS & RICCIARDI P.C. 2390 East Camelback Road, Suite 400 2 Phoenix, Arizona 85016 Telephone: (602) 248-8203 3 Facsimile: (602) 248-8840 E-Mail: [email protected] 4 E-Mail: [email protected] 5 Joseph A. Schenk – 009260 6 Bradley W. Caldwell (pro hac vice to be filed) Jason D. Cassady (pro hac vice to be filed) 7 J. Austin Curry (pro hac vice to be filed) Warren J. McCarty (pro hac vice to be filed) 8 Jason S. McManis (pro hac vice to be filed) CALDWELL CASSADY CURRY P.C. 9 2101 Cedar Springs Rd., Suite 1000 Dallas, Texas 75201 10 Telephone: (214) 888-4848 Facsimile: (214) 888-4849 11 Email: [email protected] Email: [email protected] 12 Email: [email protected] Email: [email protected] 13 Email: [email protected] 14 ATTORNEYS FOR PLAINTIFF CONTINENTAL CIRCUITS, LLC 15 IN THE UNITED STATES DISTRICT COURT 16 FOR THE DISTRICT OF ARIZONA 17 CONTINENTAL CIRCUITS, LLC, CASE NO. 18 Plaintiff, 19 COMPLAINT FOR PATENT v. INFRINGEMENT 20 INTEL CORP.; IBIDEN U.S.A. CORP.; 21 IBIDEN CO., LTD., JURY TRIAL DEMANDED 22 Defendants. 23 24 Plaintiff Continental Circuits LLC files this Complaint against Defendants Intel 25 Corporation, Ibiden U.S.A. Corporation, and Ibiden Co., Ltd. (collectively, “Defendants”) 26 for patent infringement under 35 U.S.C. § 271 and alleges, based on its own personal 27 knowledge with respect to its own actions and based upon information and belief with 28 respect to all others’ actions, as follows: 582424.1 Case 2:16-cv-02026-DMF Document 1 Filed 06/22/16 Page 2 of 25 1 THE PARTIES 2 1.
    [Show full text]
  • Intel® Quark™ SE Microcontroller
    Bringing intelligence to the internet of things Introducing the Intel® Quark™ SE Microcontroller John Moore Intel IoT Application Engineer 2nd Nov 2016 Legal Disclaimers You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty- free license to any patent claim thereafter drafted which includes subject matter disclosed herein No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting: http://www.intel.com/design/literature.htm Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit http://www.intel.com/performance. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com.
    [Show full text]
  • Lightweight Smart Glass System with Audio Aid for Visually Impaired People
    Lightweight Smart Glass System with Audio Aid for Visually Impaired People Feng Lan, Guangtao Zhai and Wei Lin Institute of Image Communication and Information Processing, Shanghai Jiao Tong University, Shanghai, China Email: fdeanlan, zhaiguangtao,linwei181491g @sjtu.edu.cn Abstract—In this paper, we present a new smart glass system for people who are blind or have low vision. Individuals with visual disability are difficult to communicate effectively with their environment. The blind or visually impaired rely largely on their other senses such as hearing, touch, and smell in order to understand their surroundings. It is pretty hard for them to go out alone, not to mention finding toilets, subway stations, restaurants and so on. Giving blind people the great accessibility to their environment is the objective of the smart glass system. This smart glass system can see the world for them and give voice instructions and hints through wireless bone conduction headphones. This smart glass system will help visually impaired people gain increased independence and freedom in city life. And Fig. 1: Snapshot of the prototype smart glass. we have implemented an application of public signs recognition on the smart glass system. This application can detect and recognize the public signs in cities, and give corresponding voice hints to the blindness. The proposed prototype system is based on Intel by Intel as a development system for wearable devices. Its Edison, and the application in the system is written in C++ with dimensions are 35:5 × 25 × 3:9mm, with components on both libraries of OpenCV. Extended demonstration of the system will sides.
    [Show full text]
  • Intel® Quark™ SE Microcontroller C1000 Development Platform
    Intel® Quark™ SE Microcontroller C1000 Development Platform User Guide December 2016 Document Number: 335278-002EN You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800- 548-4725 or by visiting: http://www.intel.com/design/literature.htm Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at http://www.intel.com/ or from the OEM or retailer. No computer system can be absolutely secure. Intel, Intel Quark, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2016, Intel Corporation. All rights reserved. Intel® Quark™ SE Microcontroller C1000 Development Platform User Guide December 2016 2 Document Number: 335278-002EN Contents 1.0 Introduction ................................................................................................................................................
    [Show full text]
  • Intel® Quark™ SE Microcontroller
    PRODUCT BRIEF Intel® Quark™ SE microcontroller The newest Intel Quark SE microcontrollers bring always-sensing intelligence and powerful peripheral support to the next generation of intelligent connected devices. Internet of Things Product Overview allows the main CPU to sleep, until the Intel is proud to announce the Intel® sensor controller wakes it up based on Quark™ SE microcontroller, bringing programmable cues, resulting in very intelligent power to the edge by low energy consumption. combining a microcontroller with an onboard sensor subsystem to Intel-Class Security Features manage power consumption through The Intel Quark SE microcontroller programmable wake cues. The Intel extends rock-solid Intel security down Quark SE microcontroller also features to the device level with software- and pattern matching technology that hardware-based features to help allows it to learn and differentiate. The protect data at every endpoint. result is always-sensing intelligence, Intelligence at the Edge bringing real-time response down The Intel Quark SE microcontroller to the next generation of intelligent brings intelligence to the edge devices. THE INTEL® Quark™ SE for real-world applications. It is MICROCONTROLLER IS IDEAL FOR: Pattern Matching Technology interoperable with other Intel®-based The Intel Quark SE microcontroller systems, simplifying integration of includes sophisticated pattern edge products in end-to-end IoT matching technology that allows it to architectures. More can be handled learn through pattern recognition and at the device level, reducing the need differentiate appropriate response for larger gateways. events. Having decision-making Faster Time to Market ability at the edge can provide a more The Intel Quark SE microcontroller real-time response, such as in an Smart Display simplifies design and reduces bill of tags/readers controllers industrial setting, monitoring energy for industrial for retail materials (BOM) by minimizing external consumption and triggering an applications components required on the platform.
    [Show full text]
  • Ilore: Discovering a Lineage of Microprocessors
    iLORE: Discovering a Lineage of Microprocessors Samuel Lewis Furman Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science in Computer Science & Applications Kirk Cameron, Chair Godmar Back Margaret Ellis May 24, 2021 Blacksburg, Virginia Keywords: Computer history, systems, computer architecture, microprocessors Copyright 2021, Samuel Lewis Furman iLORE: Discovering a Lineage of Microprocessors Samuel Lewis Furman (ABSTRACT) Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing. We propose iLORE, a data model designed to represent intricate relationships between computer system benchmarks and computer components. We detail the methods we used to implement and populate the iLORE data model using data harvested from publicly available sources. Finally, we demonstrate the validity and utility of our iLORE implementation through an analysis of the characteristics and lineage of commercial microprocessors. We encourage the research community to interact with our data and visualizations at csgenome.org. iLORE: Discovering a Lineage of Microprocessors Samuel Lewis Furman (GENERAL AUDIENCE ABSTRACT) Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing.
    [Show full text]
  • W60X Openocd Debugging Guide
    Beijing Winner Microelectronics Co., Ltd. W60X OpenOCD Debugging Guide V0.1 Beijing Winner Microelectronics Co., Ltd. Address: 18th Floor, Yindu Building, No.67, Fucheng Road, Haidian District, Beijing ,China Tel: +86-10-62161900 Website: www.winnermicro.com 1 Beijing Winner Microelectronics Co., Ltd. Document History Version Completion Date Revision Record Author Auditor V0.1 2018-11-16 Initial release LiLm 1 Beijing Winner Microelectronics Co., Ltd. Content Document History ................................................................................................................................................ 1 Content ................................................................................................................................................................. 2 1 Introduction .................................................................................................................................................. 4 1.1 Purpose ......................................................................................................................................... 4 1.2 Readers ......................................................................................................................................... 4 1.3 Term Definition ............................................................................................................................ 4 2 Quick Start: How to use Eclipse+OpenOCD to debug W60X. .................................................................... 5 2.1 How to Connect
    [Show full text]
  • Intel® Xeon® Scalable Processor Overview • Skylake-SP CPU Architecture • Lewisburg PCH Architecture
    Akhilesh Kumar, Skylake-SP CPU Architect Malay Trivedi, Lewisburg PCH Architect June 12th, 2017 Notices and Disclaimers This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit http://www.intel.com/performance. Cost reduction scenarios described are intended as examples of how a given Intel-based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. Statements in this document that refer to Intel’s plans and expectations for the quarter, the year, and the future, are forward-looking statements that involve a number of risks and uncertainties. A detailed discussion of the factors that could affect Intel’s results and plans is included in Intel’s SEC filings, including the annual report on Form 10-K. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
    [Show full text]