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The CPU and Memory

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The CPU and Memory The CPU and Memory How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram: ITEC 1000 Introduction to Information Technologies 1 Sunday, November 1, 2009 Registers A register is a permanent storage location within the CPU. Registers may contain: • a memory address for communication with memory • an input or output address • data is stored for an arithmetic or logic operation • an instruction in process of execution • codes for special purposes - e.g. keeping track of status • conditions for conditional branch instructions The Little Man Computer had a single register - the accumulator ITEC 1000 Introduction to Information Technologies 2 Sunday, November 1, 2009 Register Characteristics: • directly wired within CPU • not addressed as memory locations for which access time is slow • manipulated by CPU during execution • may be of different sizes depending on function Register names and functions: • program counter register (PC) - holds address of current instruction • instruction register (IR) - holds actual instruction being executed together with parameters • memory address register (MAR) - holds address of a memory location • memory data register (MDR) - holds data being stored or retrieved from memory location addressed by MAR • status registers - indicate such as: arithmetic/logic conditions, memory overflow, power failure, internal error, etc. ITEC 1000 Introduction to Information Technologies 3 Sunday, November 1, 2009 Memory- operation - capacity - implementations Operations on memory - role of the MAR and MDR MAR holds an address of a sequence of adjacent bytes - usually 8 A decoder interprets address - opens up circuits (lines) to location Each bit of MDR may be connected to each bit of memory - so when MAR opens circuits to addressed location : • a connection is made from each of the data bits at addressed location to corresponding bit in MDR • condition of memory bit is transfered to corresponding MDR bit • conversely condition of MDR bit can be transfered to corresponding memory bit ITEC 1000 Introduction to Information Technologies 4 Sunday, November 1, 2009 Relation between MAR and MDR For the case when addresses are expressed in 32 bits and memory locations are addressed as large 8 byte chunks = 64 bits --- A given 32 bit memory address is “decoded” by Address Decoder to effectively open circuits (lines) between bits of the memory data register and bits of the 8 byte addressed memory location. Data in memory location can be transferred to MDR by turning on bits in MDR that correspond to bits turned on in memory. Conversely data can be transfered from MDR to an addressed memory location. ITEC 1000 Introduction to Information Technologies 5 Sunday, November 1, 2009 Memory capacity The addressable capacity of a computer is related to the size of the Memory Address Register. • A 32 bit registrar allows 232 = 4,294,967,296 addresses • Each address indicates position of a byte • A 32 bit register allows possibility of addressing 4 GB (gigabytes) - 4 billion bytes. • Notice we round to the nearest billion • For full capacity to be realized computer must contain at least 4GB of physical memory ITEC 1000 Introduction to Information Technologies 6 Sunday, November 1, 2009 Memory implementations Magnetic core memory - small bit of magnetic material for each bit of memory. Small wires connect to magnetic bits that allow to electrical current that will change polarity. Expensive - but non-volatile - military & space applications RAM (random access memory) dynamic RAM = DRAM • network of electrically-charged points • quickly accessible • any portion can be directly accessed - thus “random access” • charge must be renewed every few milliseconds - thus volatile • inexpensive ITEC 1000 Introduction to Information Technologies 7 Sunday, November 1, 2009 static RAM = SRAM faster, more expensive, most computers have small amount for high speed access - also called cache memory - also volatile ROM - read only memory • fixed part of computer circuits - called mask ROM used in older computers • more recent types allow for in frequent and slow re-writing - EEPROM or Flash Rom - used in electronic devices - cameras, cell- phones, automobiles, .... ITEC 1000 Introduction to Information Technologies 8 Sunday, November 1, 2009 Fetch-Execute Instruction Cycle Computer designed to execute instructions sequentially. The program counter register (PC) contains the address in memory of location containing next instruction to execute. Program counter was set by previous instruction Following steps occur automatically - hardwired - part of control unit Step 1: address of instruction moved from PC to MAR - this automatically transfers content of addressed location to MDR - thus MDR contains the instruction and its parameters Step 2: contents of MDR is transfered to instruction register (IR) Step 3: address part of instruction (if there is one) moved to MAR Step 4: the instruction in IR is executed Step 5: the program counter register is updated to address of next instruction ITEC 1000 Introduction to Information Technologies 9 Sunday, November 1, 2009 Example: (Little Man Computer syntax) Given information: PC contains number 65 - the address of 65th box Box 65 contains the instruction 590 - that is: load contents of box 90 to accumulator (A). Box 90 contains number 111 The cycle: Step 1: address 65 transfers to MAR - the contents of box 65 transfered automatically to MDR - thus MDR contains 590 Step 2: contents of MDR transfered to IR - thus IR contains 590 Step 3: the address part of the instruction - that is 90 - is transfered to MAR and the contents of address 90 automatically transfered to MDR Step 4: contents of 90 added to accumulator (A) - thus A contains 111 Step 5: PC updated ITEC 1000 Introduction to Information Technologies 10 Sunday, November 1, 2009 Fetch-Execute Example: Load Accumulator Assume: Simple Eight bit system. • Thirty-two memory locations (0 to 31). • “Load” instruction is 0101 binary or 5 decimal. • Value in location 15 is ten (ie: binary 00001010) • PC (program counter) is at 5 and is about to be incremented. • The instruction, 101 01111, is in location 6 - instructions are considered to consists of 2 parts - 3 bits at high end for operation code followed to right by 5 bits for address Then ... ITEC 1000 Introduction to Information Technologies 11 Sunday, November 1, 2009 CPU Before PC increments Location 31 PC: 00101 = 05 IR: (previous) MAR: (previous) 15: 00001010 MDR: (previous) A: (previous) 06: 101 01111 = 5 15 Location 0 ITEC 1000 Introduction to Information Technologies 12 Sunday, November 1, 2009 Increment PC: PC = PC + 1 Using instruction in location 6 load contents of location 15 to accumulator Location 31 PC: 00110 = 06 IR: (previous) MAR: (previous) 15: 00001010 MDR: (previous) A: (previous) 06: 101 01111 = 5 15 Location 0 ITEC 1000 Introduction to Information Technologies 13 Sunday, November 1, 2009 MAR loaded with PC: PC -> MAR Location 31 PC: 00110 = 06 IR: (previous) MAR: 00110 = 06 15: 00001010 MDR: (previous) A: (previous) 06: 101 01111 = 5 15 Location 0 ITEC 1000 Introduction to Information Technologies 14 Sunday, November 1, 2009 Memory Location 00110 Accessed and Contents to be Placed in MDR: Location 31 PC: 00110 = 06 IR: (previous) = 06 MAR: 00110 15: 00001010 MDR: (previous) A: (previous) 06: 101 01111 = 5 15 ITEC 1000 Introduction to Information Technologies 15 Sunday, November 1, 2009 Memory Location 00110 Accessed and Contents Placed in MDR: Location 31 PC: 00110 = 06 IR: (previous) MAR: 00110 = 06 15: 00001010 MDR: 101 01111 = 5 15 A: (previous) 06: 101 01111 Location 0 ITEC 1000 Introduction to Information Technologies 16 Sunday, November 1, 2009 MDR copied to IR: MDR -> IR Location 31 PC: 00110 = 06 IR: 101 01111 = 05 15 MAR: 00110 = 06 15: 00001010 MDR: 101 01111 = 05 15 A: (previous) 06: 101 01111 Location 0 ITEC 1000 Introduction to Information Technologies 17 Sunday, November 1, 2009 IR [ address part ] -> MAR Location 31 PC: 00110 = 06 IR: 101 01111 = 5 15 Address portion 15: 00001010 MAR: 1111 =15 transfered to MAR MDR: 101 01111 = 5 15 A: (previous) 06: 101 01111 Location 0 ITEC 1000 Introduction to Information Technologies 18 Sunday, November 1, 2009 Location in MAR (01111) Accessed Location 31 PC: 00110 = 06 IR: 101 01111 = 05 15 connection to memory established 15: 00001010 MAR: 1111 =15 MDR: 101 01111 A: (previous) 06: 101 01111 Location 0 ITEC 1000 Introduction to Information Technologies 19 Sunday, November 1, 2009 Contents of 01111 loaded into MDR Location 31 PC: 00110 = 06 IR: 101 01111 MAR: 1111 15: 00001010 MDR: 00001010 data in memory transfered A: (previous) 06: 101 01111 Location 0 ITEC 1000 Introduction to Information Technologies 20 Sunday, November 1, 2009 IR [op code] executed: MDR -> A Location 31 PC: 00110 = 06 IR: 101 01111 MAR: 1111 15: 00001010 op code 5 loads contents MDR: 00001010 of MDR A: 00001010 06: 101 01111 Location 0 ITEC 1000 Introduction to Information Technologies 21 Sunday, November 1, 2009 Finished ! Location 31 PC: 00110 = 06 IR: 101 01111 MAR: 1111 15: 00001010 MDR: 00001010 A: 00001010 06: 101 01111 Location 0 ITEC 1000 Introduction to Information Technologies 22 Sunday, November 1, 2009 Now the next instruction: Assume: • Value in location 7 is 001 10010. • “Add” instruction is 001. • Value in location 18 is seventy-one (i.e.: binary 01000111) • Everything else is as we left it! Then ... ITEC 1000 Introduction to Information Technologies 23 Sunday, November 1, 2009 PC =
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