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Special Address Generation Arrangement Patentamt 0 034 1 80 ® êJEuropâischesy))} European Patent Office ® Publication number: Office européen des brevets B1 ® EUROPEAN PATENT SPECIFICATION (§) Dateof publication of patent spécification: 31.10.84 ® Int. Cl.3: G 06 F 9/32 ® Application number: 80901823.7 (22) Date offiling: 11.08.80 (88) International application number: PCT/US80/01017 (87) International publication number: WO 81/00633 05.03.81 Gazette 81/06 @ SPECIAL ADDRESS GENERATION ARRANGEMENT. (§) Priority: 31.08.79 US 71717 (73) Proprietor: Western Electric Company, Incorporated 222 Broadway (43) Date of publication of application: New York, NY 10038 (US) 26.08.81 Bulletin 81/34 (72) Inventor: HUANG, Victor Kuo-Liang (45) Publication of the grant of the patent: 2246 Jersey Avenue 31.10.84 Bulletin 84/44 Scotch Plains, NJ 07090 (US) © Designated Contracting States: (74) Représentative: Weitzel, David Stanley et al DE FR GB NL Western Electric Company Limited 5, Mornington Road Woodford Green Essex IG8 0TU (GB) Références cited: FR-A-1 564 476 US-A-3 297 998 Références cited: US-A-3 343134 IBM TECHNICAL DISCLOSURE BULLETIN, vol. US-A-3 394 350 17, no. 7, december 1974 New York (US) T.G. CÛ US-A-3 533 076 ARTHUR et ai.: "Direct access for text US-A-3 593 313 memory move", pages 1852-1853 o US-A-3 739 345 IBM TECHNICAL DISCLOSURE BULLETIN, vol. US-A-4 00 065 810 19, no. 1,june1976 New York (US) T.J. US-A-4 080 650 DVORAK et al.: "Hardware assist for microcode "An Introduction to IVlicrocomputers Volume I", exécution of storage-to-storage move issued 1976 A. Osborne, pp. 5-34 to 5-41 instructions", pages 67-70 co "An Introduction to Microcomputers Volume o II", issued 1976, A. Osborne, pp. 4-133 to 4-143 o Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall CL be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been LU paid. (Art. 99(1 ) European patent convention). Courier Press, Leamington Spa, England. initial address. The invention as claimed is characterized by the capability of the address Technical Field decoder to distinguish on the basis of the This invention relates generally to an address addresses, the capability of the control counter generation arrangement and, more particularly, for special registers and general store to an arrangement for generating a sequence of addresses, the capacility of the control counter addresses in response to an initial address. to count an operation for each addressed data unit, the disablement of the periodic incre- Background of the Invention mentation of the address stored in the address In the prior art, there are microprocessors, register by decoding, the storage of a portion of microcomputers and other data processors and an initial special address into a binary repre- computers which have addressable special sentation of the predetermined number of se- registers. Typically such registers have a uni- quential addresses for comparison with the con- form length that is compatible with the width of tents of the control counter and the production a data bus included in the particular system. in the case of equality of a termination signal for There are reasons, such as for increasing the the periodic incrementation of the address facility for manipulating address information stored in the address register. contained in special registers, that the uniform length constraint should be removed. Then Brief Description of the Drawing arithmetic and logic manipulation of address The invention will be more fully understood information may be accomplished on data from the following detailed description of an words which are longer than the width of the illustrative embodiment thereof when that data bus. To accomplish such manipulation of description is read in conjunction with the longer data words, plural consecutive addresses attached drawing wherein are used to define the location of the special FIGS. 1, 2 and 3, when positioned in accord- registers. ance with FIG. 4, form a block diagram of a There are arrangements, such as direct microcomputer; memory access circuits, in the prior art for FIG. 5 is a logic schematic of data bus cir- generating plural consecutive addresses from cuits; an initial address. A general description of a FIG. 6 is a logic schematic of an instruction direct memory access arrangement is pre- register decoder and latches; sented by A. Osborne in An Introduction to FIG. 7 shows the positioning of FIGS. 8 and 9 Microcomputers Vol. 1, 1976, pages 5-34 to which form a state diagram showing sequences 5-41. The initial address is loaded into an of operations for instructions performed by the address register and is automatically incre- microcomputer of FIGS. 1-3; mented a number of times. Each time it is incre- FIG. 10 is a logic schematic of a state mented it is used to address another part of the counter and multiplexer; data. The number of times that the address is FIG. 11 is a logic schematic of a decoder; incremented is determined by reference to FIG. 12 is a logic schematic of a trans- another piece of information which represents mission gate multiplexer; the number. This number is decremented each FIGS. 13 and 14, when arranged in accord- time the address is incremented. When the ance with FIG. 15, form a logic schematic of an number is decremented to zero, the process of address arithmetic unit with latches, buses and sequential address generation is terminated. gates; The foregoing requires the attention of the FIG. 16 is a timing diagram for the micro- programmer to insert the appropriate number of computer of FIGS. 1-3; times to increment the address in his program in FIGS. 17 and 18, when positioned in accord- association with every occurrence of the ance with FIG. 19, show a logic schematic of a address of a special register. special address circuit and a special latch For applications wherein access to such arrangement; and special registers occurs often during pro- FIG. 20 is a logic schematic of a comparator. gramming, it is convenient to relieve the pro- grammer of this task. Detailed Description Referring now to FIGS. 1, 2 and 3, there is Brief Description of the Invention shown a block diagram of a microcomputer that The foregoing problem is avoided by the is fabricated on a single complementary metal invention as claimed which automatically pro- oxide semiconductor/large scale integration duces in an address register a succession of (CMOS/LSI) chip. Included on the chip are a sequential addresses in addressable memory read only memory 20 and a random access space in response to an initial address stored memory 22 which are coupled through a 4-bit therein and periodically increments the stored on-chip data bus 24 and a group of temporary address until terminated by a control counter registers (TA, TB and AB) 26, 27 and 28 to a 4- after counting a predetermined number of bit parallel arithmetic logic unit (ALU) 30. sequential addresses,. the predetermined Several other on-chip registers are coupled to number being decoded from a portion of the the on-chip data bus 24 so that they are addressable by the user. Extensive input/out- Addressable Registers put circuitry and direct memory access circuitry The microcomputer includes many registers are provided on the chip for increasing the ver- arranged in different ways to accomplish a satility and efficiency of the microcomputer. The variety of convenient functions. Some of those memory and registers are to be described in registers have been mentioned previously and more detail hereinafter. some have not. All of the registers are to be A controller section, shown mostly in FIG. 2, described in more detail hereinafter. The micro- coordinates and executes sequential opera- computer shown in FIGS. 1, 2 and 3 includes tions of the microcomputer while it accom- ten (10) user addressable registers but unlike plishes whatever functions are required in most microcomputers there is no preassigned accordance with instructions applied thereto accumulator. from the read only memory 20 or the random access memory 22. The contents of a condition User Addressable Special Registers register (CR) 31 are modified as a result of The user addressable registers include the operations occurring in the arithmetic logic following registers. unit 30. The condition register 31 is a 4-bit set of bi- Although the arithmetic logic unit 30 is a 4- stable latch circuits which store signals indicat- bit parallel circuit arrangement, it is capable of ing the status, or condition, of data resulting performing arithmetic and logic operations on from arithmetic or logic operations except when either single or multiple nibble operands in the condition register is a destination. The con- response to a single program instruction. In dition register and the condition steering circuit response to information stored in an instruction 54 are interposed between the arithmetic logic register (IR) 32 and a processor control register unit 30 and the internal data bus 24. Both the (PCR) 33, the controller section of FIG. 2 deter- arithmetic logic unit and the internal data bus mines the mode and the type of operation per- are arranged to process 4-bit data in parallel. formed on single and multiple nibble operands. The condition register is addressable so that it Basically an opcode word, stored in the instruc- can be accessed for loading and reading by way tion register 32, determines a processing se- of the data bus.
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