Transmission Line Basics

Prof. Tzong-Lin Wu

NTUEE

1 Outlines

Transmission Lines in Planar structure. Key Parameters for Transmission Lines. Transmission Line Equations.

Analysis Approach for Z0 and Td

Intuitive concept to determine Z0 and Td Loss of Transmission Lines Example: Rambus and RIMM Module design

2 Transmission Lines in Planar structure

Homogeneous Inhomogeneous



Microstrip line Coaxial Cable

 

Embedded Microstrip line Stripline

3

Key Parameters for Transmission Lines

1. Relation of V / I : Characteristic Impedance Z0 2. Velocity of Signal: Effective dielectric constant e 3. Attenuation: Conductor loss ac Dielectric loss ad

Lossless case 1 L Td Z0 C V p C C

1 c0 1

V p LC  e Td

4

Transmission Line Equations

Quasi-TEM assumption

5

Transmission Line Equations

R0  resistance per unit length(Ohm / cm)

G0  conductance per unit length (mOhm / cm)

L0  inductance per unit length (H / cm)

C0  capacitance per unit length (F / cm) dV KVL :  (R0  jwL0 )I dz Solve 2nd order D.E. for dI V and I KCL :  (G0  jwC0 )V dz

6

Transmission Line Equations Two wave components with amplitudes V+ and V- traveling in the direction of +z and -z

rz rz V  V e V e

1 rz rz I  (V e V e )  I   I  Z0 Where propagation constant and characteristic impedance are

r  (R0  jwL0 )(G0  jwC0 )  a  j

V V R0  jwL0 Z0    I  I  G0  jwC0

7

Transmission Line Equations a and  can be expressed in terms of (R0 , L0 ,G0 ,C0 )

2 2 2 a    R0G0   L0C0

2a  (R0C0  G0 L0 )

The actual voltage and current on transmission line: az  jz az jz jwt V (z,t)  Re[(V e e V e e )e ]

1 az  jz az jz jwt I(z,t)  Re[ (V e e V e e )e ] Z0

8 Analysis approach for Z0 and Td (Wires in air)

C = ? (by Q=C V)

L = ? (by Ψ=L I)

9 Analysis approach for Z0 and Td (Wires in air): Ampere’s Law for H field

II H(r)=  d 2r c

R2 IIR 2)  B ds 00 dr  ln(1 ) (in Wb) eTS r R 1 2 r 2 R2

10 Analysis approach for Z0 and Td (Wires in air): Ampere’s Law for H field

0 I R2  e  ln( ) 2 R1

LI e /

11 The per-unit-length Parameters (E): Gauss’s Law

1) from gauss law D   E d s  Q S T total q1m E T  ds 0 S q  2 0r

R1 q 2) V= E d dr C T rR 2 2 0r q R  ln 2 2R 01

12 The per-unit-length Parameters (E)

qR V  ln(2 ) 201R CQV /

13 c. For example Determine the L.C.G.R of the two-wire line.

(note：homogeneous medium) S Inductance：

 r rw2 L=  e w1 I e I I  where

0I s-r w2 0 I s-r w1   e  ln( )+ ln( ) e 2 rw1 2 r w2 (,)  I (s-r )(s-r ) 00 =0 ln( w2 w1 ) 2 rw1 r w2

assume s rw1 , r w2  s2  L=0 ln( ) 2 rw1 r w2 14 Capacitance： S 1) e c  00 - - + + r rw2 2 0 w1 - C - 2 + + V s + - - ln ( ) q C/m -q C/m rrw1 w2 qqs-r s-r 2) V= ln(w2 )+ ln( w1 ) 20 r w1 2  0 r w2 q (s-r )(s-r ) = ln(w2 w1 ) 2 0 r w1 r w2 q s2  ln( ) if s rw1 , r w2 2 0 r w1 r w2 q 2 C= 0  the same with 1) approach V s2 ln ( ) rr w1 w2 15 The per-unit-length Parameters Homogeneous structure

TEM wave structure is like the DC (static) field structure

LG   LC  

So, if you can derive how to get the L, G and C can be obtained by the above two relations.

16 The per-unit-length Parameters (Above GND )

2C Why? L/2

17 , d. How to determine L,C for microstrip-line. 00 , 1) This is inhomogeneous medium. 11 2) Nunerical method should be used to solve the C of this structure, such as Finite element, Finite Difference...

3) But e can be obtained by

00 eC0  0 0  e C0

where C01 is the capacitance when  medium

is replaced by  0 medium.

18 Analysis approach for Z0 and Td (Strip line)

Approximate electrostatic solution y

1.   b x -a/2 a/2

2. The fields in TEM mode must satisfy Laplace equation 2 t (x, y)  0 where  is the electric potential The boundary conditions are (x, y)  0 at x  a / 2 (x, y)  0 at y  0,b

19 Analysis approach for Z0 and Td

3. Since the center conductor will contain the surface charge, so   n x n y  An cos sinh for 0 y b / 2 n1 aa  odd (,)xy    n x n  Bn cos sinh ( b y ) for b / 2  y  b  n1 aa  odd Why?

4. The unknowns An and Bn can be solved by two known conditions: RThe potential at y  b / 2 must continuous S| R1 for x  W / 2 The surface charge distribution for the strip:  s  S T| T0 for x  W / 2

20 Analysis approach for Z0 and Td

5. R b/2 b/2 V   E (x  0, y)dy   (x, y) / y(x  0, y)dy | z y z | 0 0 S w/2 |Q   (x)dx  W(C / m) z s T| w/2

Q W 6. C   V  2a sin(nW / 2a) sinh(nb / 2a)  2 n1 (n)  0 r cosh(nb / 2a) odd

1  r Answers!! Z0   v pC cC

7. Td   r / c 21 Analysis approach for Z0 and Td (Microstrip Line) y 1. PEC PEC

d W   x

-a/2 a/2 2. The fields in Quasi - TEM mode must satisfy Laplace equation 2 t (x, y)  0 where  is the electric potential The boundary conditions are (x, y)  0 at x  a / 2 (x, y)  0 at y  0,

22 Analysis approach for Z0 and Td (Microstrip Line)

3. Since the center conductor will contain the surface charge, so  nx ny R A cos sinh for 0  y  d | n n1 a a |odd (x, y)  S  nx ny/a | Bn cos e for d  y   |n1 a Todd

4. The unknowns An and Bn can be solved by two known conditions and the orthogonality of cos function : RThe potential at y  d must continuous S| R1 for x  W / 2 The surface charge distribution for the strip:  s  S T| T0 for x  W / 2

23 Analysis approach for Z0 and Td (Microstrip Line)

5. R b/2 b/2  nd V   E (x  0, y)dy   (x, y) / y(x  0, y)dy  A sinh | z y z  n 0 0 n1 a | odd S w/2 |Q   (x)dx  W(C / m) | z s T w/2 6. Q W C   V  4a sin(nW / 2a) sinh(nd / 2a)  2 n1 (n) W 0[sinh(nd / a)   r cosh(nd / a)] odd

24 Analysis approach for Z0 and Td (Microstrip Line) 7. To find the effective dielectric constant  e ,we consider two cases of capacitance

1. C = capacitance per unit length of the microstrip line with the dielectric substrate  r  1

2. C0 = capacitance per unit length of the microstrip line with the dielectric substrate  r  1 C  e  C0

8.

1  e Z0   v pC cC

Td   e / c

25 Tables for Z0 and Td (Microstrip Line)

20 28 40 50 75 90 100 Z0 ()

3.8 3.68 3.51 3.39 3.21 3.13 3.09  eff

L0 0.119 0.183 0.246 0.320 0.468 0.538 0.591 (nH / mm)

C0 0.299 0.233 0.154 0.128 0.083 0.067 0.059 (pF / mm)

T0 6.54 6.41 6.25 6.17 5.99 5.92 5.88 (ps / mm)

Fr4 : dielectric constant = 4.5 Frequency: 1GHz

26 Tables for Z0 and Td (Strip Line)

20 28 40 50 75 90 100 Z0 ()

4.5 4.5 4.5 4.5 4.5 4.5 4.5  eff

L0 0.141 0.198 0.282 0.353 0.53 0.636 0.707 (nH / mm)

C0 0.354 0.252 0.171 0.141 0.094 0.078 0.071 (pF / mm)

T0 7.09 7.09 7.09 7.09 7.09 7.09 7.09 (ps / mm)

Fr4 : dielectric constant = 4.5 Frequency: 1GHz

27 Analysis approach for Z0 and Td (EDA/Simulation Tool)

1. HP Touch Stone (HP ADS)

2. Microwave Office

3. Software shop on Web:

4. APPCAD

(http://softwareshop.edtn.com/netsim/si/termination/term_article.html)

(http://www.agilent.com/view/rf or http://www.hp.woodshot.com )

28 Concept Test for Planar Transmission Lines

• Please compare their Z0 and Vp (a) (b)

 





29 (a) (b) (c)

  

 

30 (a) (b) (c)



  



 

31 32 Loss of Transmission Lines

Typically, dielectric loss is quite small -> G0 = 0. Thus

R0  jwL0 L0 1/2 Z0   (1 jx) jwC0 C0 R r  (R  jwL )( jwC )  a  j w  0 0 0 0 L0 R Highly Lossy Near Lossless where x  0 wL0  w

• Lossless case : x = 0 • Near Lossless: x << 1  w • Highly Lossy: x >> 1

33 Loss of Transmission Lines

•For Lossless case: • For Near Lossless case:

R a  0 a  0 2 L0 / C0    L0C0 x 2 L    L C L1 O Z  0 0 0 M P 0 N 8 Q C0 L F R I L 1 Time delay T  L C Z  0 1 j 0  0  where C  2T / R 0 0 0 0 G J 0 0 C0 H 2wL0 K C0 jwC

Time delay T0  L0C0

34 Loss of Transmission Lines

• For highly loss case: (RC transmission line)

wR C 1 a  0 0 [1 ] 2 2x Nonlinear phase relationship with f introduces signal distortion wR C 1   0 0 [1 ] 2 2x Example of RC transmission line: AWG 24 telephone line in home R0 1 1/2 Z0  [1 ] F R  iwLI 2wC 2x Z (w)   648(1 j) 0 0 HG jwC KJ where R  0.0042 / in L  10nH / in C  1pF / in That’s why telephone company terminate w  10,000rad / s(1600Hz) : voice band the lines with 600 ohm

35 Loss of Transmission Lines ( Dielectric Loss)

The loss of dielectric loss is described by the loss tangent G tan  FR4 PCB tan  0.035 D wC D

GZ a  0  (wC tan Z ) / 2  f tan LC D 2 D 0 D

36 Loss of Transmission Lines (Skin Effect)

• Skin Effect DC resistance AC resistance

37 Loss of Transmission Lines (Skin Effect)

1 2    s a w

1 length w Rw() area

NOTE: In the near lossless region (R / wL  1),

the characteristic impedance Z0 is not much affected by the skin effect

 R(w)  w  R(w) / wL  (1/ w)  1

38 Loss of Transmission Lines (Skin Effect)

f (MHz) 100 200 400 800 1200 1600 2000

1 6.6um 4.7um 3.3um 2.4um 1.9um 1.7um 1.5um   s f 2.6m 3.7m 5.2m 7.4m 9.0m 10.8m 11.6m R () s ohm ohm ohm ohm ohm ohm ohm Trace 1.56 2.22 3.12 4.44 5.4 6.48 7.0 resistance ohm ohm ohm ohm ohm ohm ohm

f Skin depth resistance R = () s  6mil  = 4  10-7 H / m Cu 17um  (Cu) = 5.8  107 S / m Length of trace = 20cm

39 Loss Example: Gigabit differential transmission lines

For comparison: (Set Conditions)

1. Differential impedance = 100 2. Trace width fixed to 8mil 3. Coupling coefficient = 5% 4. Metal : 1 oz Copper

Question:

1. Which one has larger loss by skin effect? 2. Which one has larger loss of dielectric?

40 Loss Example: Gigabit differential transmission lines

Skin effect loss

41 Loss Example: Gigabit differential transmission lines

Skin effect loss

Why?

42 Loss Example: Gigabit differential transmission lines

Look at the field distribution of the common-mode coupling

Coplanar structure has more surface for current flowing

43 Loss Example: Gigabit differential transmission lines

How about the dielectric loss ? Which one is larger?

44 Loss Example: Gigabit differential transmission lines

The answer is dual stripline has larger loss. Why ?

The field density in the dielectric between the trace and GND is higher for dual stripline.

45 Loss Example: Gigabit differential transmission lines

Which one has higher ability of rejecting common-mode noise ?

46 Loss Example: Gigabit differential transmission lines

The answer is coplanar stripline. Why ?

47 48 49 50 51 Intuitive concept to determine Z0 and Td •How physical dimensions affect impedance and delay Sensitivity is defined as percent change in impedance per percent change in line width, log-log plot shows sensitivity directly.

Z0 is mostly influenced by w / h, the sensitivity is about 100%. It means 10% change in w / h will

cause 10% change of Z0

The sensitivity of Z0 to changes in  r is about 40%

52 Intuitive concept to determine Z0 and Td

•Striplines Delay impedance

53 Ground Perforation: BGA via and impedance

54 Ground Perforation: Cross-talk (near end)

55 Ground Perforation : Cross-talk (far end)

56 Example(II): Transmission line on non-ideal GND

Reasons for splits or slits on GND planes

57 Example(II): Transmission line on non-ideal GND

58 Example(II): Transmission line on non-ideal GND

59 Example(II): Transmission line on non-ideal GND

60 Example(II): Transmission line on non-ideal GND

61 Example(II): Transmission line on non-ideal GND

62 Example(II): Transmission line on non-ideal GND

63 Input side

64 Output side

65 66 67 68 Example: Rambus RDRAM and RIMM Design RDRAM Signal Routing

69 Example: Rambus RDRAM and RIMM Design

•Power: VDD = 2.5V, Vterm = 1.8V, Vref = 1.4V

•Signal: 0.8V Swing: Logic 0 -> 1.8V, Logic 1 -> 1.0V 2x400MHz CLK: 1.25ns timing window, 200ps rise/fall time Timing Skew: only allow 150ps - 200ps

•Rambus channel architecture: (30 controlled impedance and matched transmission lines)

.Two 9-bit data buses (DQA and DQB) .A 3-bit ROW bus .A 5-bit COL bus .CTM and CFM differential clock buses

70 Example: Rambus RDRAM and RIMM Design

.RDRAM Channel is designed for 28 +/- 10% .Impedance mismatch causes signal reflections .Reflections reduce voltage and timing margins

.PCB process variation -> Z0 variation -> Channel error

71 Example: Rambus RDRAM and RIMM Design

• Intel suggested coplanar structure

Ground flood & Stitch

• Intel suggested strip structure

Ground flood & Stitch

72 Example: Rambus RDRAM and RIMM Design PCB Parameter sensitivity: • H tolerance is hardest to control

• W & T have less impact on Z0

73 Example: Rambus RDRAM and RIMM Design

• How to design Rambus channel in RIMM Module

with uniform Z0 = 28 ohm ?? • How to design Rambus channel in RIMM Module with propagation delay variation in +/- 20ps ??

74 Example: Rambus RDRAM and RIMM Design Impedance Control: (Why?) Loaded trace

Unloaded trace

Connector

75 Example: Rambus RDRAM and RIMM Design Multi-drop Buses

Unloaded Z0

Stub Device input

Capacitance Cd

Electric pitch L A Multidrop Bus Equivalent loaded ZL

L0 L0 Z L    28 (for Rambus design) CT CL L0  2 L Z0

where CT is the per - unit - length equivalent capacitance at length L, including the loading capacitance and the unloaded trace capacitance

C L is the loading capacitance including the device input capacitance Cd , the stub trace capacitance, and the via effect. 76 Example: Rambus RDRAM and RIMM Design

In typical RIMM module design

Device input capacitance stub via

If CL  0.2pF + 0.1pF + 2.2pF, and

If you design unloaded trace Z0  56

the electric pitch L = 7.06mm to reach loaded ZL  28

 L0  Z0  56  6.77 psec / mm = 379 pH / mm = 9.5 pH / mil

CL L0 2.5pF 379 pH / mm CT   2   2  0.475 pF / mm L Z0 7.06mm 56

L0  Z L   28.3 CT

77 Example: Rambus RDRAM and RIMM Design

• Modulation trace Device pitch = Device height + Device space

Electrical pitch L is designed as C Z 2 L  L L  2 2 (Z0  Z L ) Z0

If device pitch > electric pitch, modulation trace of 28ohm should be used.

Modulation trace length = Device pitch – Electric pitch

78 Example: Rambus RDRAM and RIMM Design

• Effect of PCB parameter variations on three key module electric characteristics

79 Example: Rambus RDRAM and RIMM Design

• Controlling propagation delay: •Bend compensation •Via Compensation •Connector compensation

Bend Compensation

• Rule of thumb: 0.3ps faster delay of every bend • Solving strategies: 1. Using same numbers of bends for those critical traces(difficult) 2. Compensate each bend by a 0.3ps delay line.

80 Example: Rambus RDRAM and RIMM Design

Via Compensation (delay)

For a 8 layers PCB, a via with 50mil length can be modeled as (L, C) = (0.485nH, 0.385pF).

 Delay T0  LC  13.7 psec 1 Impedance Z =  38 Inductive 0 LC Rule of thumb: delay of a specific via depth can be calculated by scaling the inductance value which is proportional to via length.

30mil 30mil via has delay  13.7   10.6psec 50mil This delay difference can be compensated by adding a 1.566mm to the unloaded trace (56)

81 Example: Rambus RDRAM and RIMM Design

Via Compensation (impedance)

82 Example: Rambus RDRAM and RIMM Design

Connector Compensation

83 Example: EMI resulting from a trace near a PCB edge

Experiment setup and trace design

84 Example: EMI resulting from a trace near a PCB edge

Measurement Setup

85 Example: EMI resulting from a trace near a PCB edge

EMI caused by Common-mode current : magnetic coupling Measured by current probe

86 Example: EMI resulting from a trace near a PCB edge

EMI measured by the monopole : E field

Low effect at high frequency

87 Example: EMI resulting from a trace near a PCB edge

Trace height effect on EMI

88 Reference

1. Howard W. Johnson, “High-speed digital design”, Prentice-Hall, 1993 2. Ron K. Poon, “Computer Circuits Electrical Design”, Prentice-Hall, 1995 3. David M. Pozar, “Microwave Engineering”, John Wiley & Sons, 1998 4. William J. Dally, “Digital System Engineering”, Cambridge, 1998 5. Rambus, “Direct Rambus RIMM Module Design Guide, V. 0.9”, 1999

89