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(8) Abstract This report summarizes the result of Leading Research "Super-compiler technology" executed in 1999 fiscal year. In this research, we made the leading investigation for the key fundamental technologies aiming at the next generation high performance computing. Concretely, the investigations on both (1) the compiler technology for the next generation parallel computers and (2) the global computing technology were done. Then, we extracted and materialized the technological problems, and also examined the R&D system. We set up two working groups - “Parallel Compiler WG” and “Global Computing WG” to investigate in each technological field. In parallel compiler WG, three investigations were made - (1) summarizing the technological trends and problems, (2) materializing the R&D contents to initiate a project, and (3) planning the project formation. In global computing WG, two investigations were also made - (1) summarizing the latest global computing technology trends, and (2) investigating the application area of the global computing technology. The outline is sown below.
Parallelizing Compiler Technology: The difference between the peak performance (theoretical performance) of the parallel computer and the effective performance (sustained performance when a software runs) increases in recent years. This phenomenon shows that the progress of parallel software R&D is relatively delayed compared with the parallel processing hardware R&D. Especially, a parallelism extraction in the parts of a program other than in loops is insufficient. Thus, (1) the extraction of the parallelism at various levels of a program such as multi-grain parallelization, (2) the new execution methods beyond the control-dependence such as speculation and data prediction, and (3) the tuning technology interacted with the user, become keys in a technological reformation in the near future. In this research, the trends of the automatic parallelizing compiler, which is main technology of parallel software, was investigated related to the eight important technologies - (l)multi-grain parallelization, (2) inter procedure analysis, (3) extension of OpenMP, (4) dynamic compilation, (5) instruction level parallelization, (6) speculative execution, (7) tuning tools, and (8) compiler performance evaluation. Moreover, professor Okukotun involved in the R&D of on-chip multiprocessor called Hydra in Stanford University was invited, and the opinion exchange was made. As a result, five research topics are listed to be researched and developed as a project - (1) multi-grain parallelization which divides a program into suitable grains to maximize the performance, (2) speculative execution scheme including task-level speculation, (3) automatic data distribution without a user assistance, (4) scheduling scheme for multi-grain parallelization, (5) tuning scheme with dynamic program information. Moreover, technological development concerning the performance evaluation is necessary to evaluate the parallelizing compiler because the conventional benchmark test programs are designed to evaluate hardware performance. Besides that, the project formation is investigated to adopt the center management scheme directed by a project leader. In this scheme, all the researchers in industries, universities, and
(9) national laboratories are concentrated to execute the research.
Global Computing Technology: Global computing is an advanced technology that is rapidly researched and developed recently in the United States. The ability of high-performance computing resulted from the fusion of the wide area network and the computer system is focused. In this research, the technological trends on global computing in the United States were emphatically investigated to make clear the high-performance computing and global computing infrastructure (Grid). Four major international conferences in the field of global computing are reported : (1) Supercomputing '99, (2) Grid Forum, (3) JavaGrande Portals Group meeting, and (4) International Symposium on Computing with Objects in Parallel Environments. Three major projects are also reported : (1) “Millennium project ” of UC Berkley, (2) "Globus" by which the role of the toolkit is played in global computing, and (3) "The Alliance project" which is the joint project among industries, universities, and national laboratories where NASA takes its management. We conclude that the high-performance computing has made a paradigm shift, and as a result, the organization to spread the Grid called “Grid Forum ” has already been formed, and it has turned out to circulate its information, make the standalization, etc. Moreover, clusters constructed with commodity components are connected with super-wideband wide area network. The terminals including the efficient graphics terminal and PDAs are served by using the infrastructure such as Web. By using these infrastructures, many applications such as a super-large-scale numeric calculation and commercial services are on experimentation. It has turned out that the R&D of our country takes a very big delay compared with these movements. As for the global computing application, we pick up SDP (Semi-Define Programming) problem that does not rely on the experience rule but rely on non-experience rule to solve the optimization of a structural design, etc. The problem is focused on its importance because of the effective use of resources. However, the calculation performance that exceeds a single super computer is necessary to solve SDP problem. In the speed-up of the SDP problem, the method, in which selecting the best solution among many solutions with different parameters, is used. Therefore, SDP problem is suitable for global computing because the long data communication delay, that is a disadvantage of global computing, is able to be suppressed to low.
We conclude that we should initiate the project called "Advanced parallelizing Compiler ” in 2000 fiscal year. Moreover, we should continue the current R&D on Global Computing in cooperation with universities and national laboratories. Then, we should aim at the new joint R&D among industries, universities, and national laboratories by clarifying the possibility of industrial use of global computing.
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SMP +t-yi±-e©tt*g k CTH- ±IB©7"n7'7A&HVt;£ IBM RS6000 SP 604e High Node ±T©ffl*66 #%©%* Fortran 7D^7ii>^ OpenMP 7 11/^x174 IH'/fc Fortran T IBxb £ to £ *1*6 6 367!lfb 71 n 7" 7 A # OSCAR 3 >yi Y 7 C (3) $kto OSCAR Fortran vyi/7-7 W >367iJIb3 >71Y 7 ©®56*ie87 X 7 36 9Uffia^a&*-C>tcji4^fco OSCAR-771/^7'W >36?iJfb3 >ylY 7©tt(ig£- 8PE 6 jgSSLfc IBM RS6000 SP 604e High Node SMP _h®36^'JYb3 >y!Y 7T$>S IBM XL Fortran Version 5.1 k tblit LXilSSE- OSCAR 3 >71 Y 7 IC - 15 - gOSCAR ■XL o CD DC CL T3 8 Q. 0) Processors 0 1.2.1-10 RS6000±T?@ ARC2D ©j$Slq|±* [♦#**] [1] auttt, isoi. [2] U.Banerjee, Loop Transformations for Restructuring Compilers -- The Foundations, Kluwer Academic Pub., 1993. [3] U.Banerjee, Loop Parallelization, Kluwer Academic Pub., 1994 [4] W.Blume, R.Eigenmann, J.Hoeflinger, P.Petersen, L.Rauchwerger and Peng Tu, "Automatic Detection of Parallelism, IEEE Parallel & Distributed Technology, Vol.2, No. 3, pp. 37-47, Fall 1994. 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[11] H.Kasahara, H.Honda, S.Narita, "A Multi-Grain Parallelizing compilation scheme for OSCAR," Proc.4th Workshop on Languages and Compilers for Parallel - 16 - Computing, 1991 [12] P.Tu and D.Padua, "Automatic Array Privatization," 6th Annual Workshop on Languages and Compilers for Parallel Computing, 1993 [13] Zhiyuan Li, "Array Privatization for Parallel Execution of Loops," Proc. of the 1992 ACM Int'l Conf. on Supercomputing, pp. 313-322, 1992. [14] M.Gupta and P.Banerjee, "Demonstration of Automatic Data Partitioning Techiniques for Parallelizing Compilers on Multicomputers," IEEE Trans.on Parallel and Ditributed System, Vol.3, No. 2, pp. 179-193, 1992. [15] J.M.Anderson amd M.S.Lam, "Global Optimizations for Parallelism and Locality on Scalable Parallel Machines," Proc. of the SIGPLAN '93 Conference on Programming Language Design and Implementation, pp. 112-125,1993. [16] B.KUHN, R. MENON, T.MATTSON, R. EIGENMANN, “OpenMP Parallel Programming ”, IEEE ACM Supercomputing ’98 Tutorial Notes, Nov. 1998. U7]IB* be, mm, mm, ma mzm FORTRAN 3 Vol.40, No.12, pp. 4296-4308, Dec. 1999. [18] H. Kasahara, M. Okamoto, A. Yoshida, W. Ogata, K. Kimura,G. Matsui, H. Matsuzaki, K.Aida, H.Honda, ’’OSCAR Multi-grain Architecture and Its Evaluation ”, Proc. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IEEE Press, 1998. [19] ^# m-au ## mm, /b# ## ##^L@#^ARC#^^ /HPC#^^, Mar. 2000. [20] mm mm, ## ^m, d# am, sb to, mm: ARCl36-8#^^, pp.43-48, Jan. 2000. [21] SB to, mm m-, be, mu: ^ mu f^uv - 7°{h^'- ^ n - * ^ y u - a > voi. 40. No. 5, pp. 2054-2063, May 1999. [22] H. Kasahara and A. Yoshida, “A Data-Localization Compilation Scheme Using Partial Static Task Assignment for Fortran Coarse Grain Parallel Processing ”, Journal of Parallel Computing, Special Issue on Languages and Compilers for parallel Computers, May 1998.. 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Larus, Whole Program Paths, Proceedings of the ACM SIGPLAN’99 Conference on Programming Language Design and Implementation (PLDI), pp. 259-269, 1999. [4] Radu Rugina and Martin Rinard, Pointer Analysis for Multithreaded Programs, Proceedings of the ACM SIGPLAN’99 Conference on Programming Language and Design and Implementation (PLDI), pp. 77-90, 1999. [5] Sungdo Moon, Mary W. Hall, and Brian R. Murphy. Predicated array data-flow analysis for run-time parallelization. In proceedings of the 1998 ACM International Conference on Supercomputing, PP. 204-211, Melbourne, Australia, July 1998. [6] Joel H. Saltz, Ravi Mirchandaney, and Kay Crowley. Run-time parallelization and scheduling of loops. IEEE Transaction on Computers, 40(5):603-612, May 1991. [7] Lawrence Rauchwerger and David Padua. The LPRD test: Speculative run-time parallelization of loops with privatization and reduction parallelization. In Proceedings of the ACM SIGPLAN ’95 Conference on Programming Language Design and Implementation, pp. 218-232, June 1995. [8] T. Ball and J. R. Larus, Efficient Path Profiling, Proceedings of the 29 th Annual IEEE/ACM International Symposium on Microarchitecture. Paris, France, pp.46- 57, 1996. [9] C. G. Nevill-Manning and I. H. Witten, Compression and explanation using hierachical grammers, The Computer journal, vol. 40, pp. 103-116, 1997 [10] C. G. nevill-Manning and I. H. Witten, Linear-time, incremental hierarchy inference for compression, in Proceedings of the Data Compression Conference (DCC’97). Snowbird, UT: IEEE Computer Society, pp. 3-11, 1997. [11] R. Wilson and M. Lam, Efficient context-sensitive pointer analysis for C programs, In Proceedings of the SIGPLAN ’95 Conference on Program Language Design and Implementation, La Jolla, CA, June 1995. [12] M. Frigo, C. Leiserson, and K. Randall. The implementation of the Cilk-5 multithreaded language. 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Index distribution Index distribution IdL IS^U0 4 ^ 7 7 7 §fs/R 1“ £ fe £ 0 HI 1.2.3-12 777 o HI 1.2.3-12 -CU\ mf, P Index distribution IX ^WTO - 34 - 1.2.4 gjfitjn yn-i v—i/ a (l) litfel: bSi-5 C k A^ sj|gt> L < !2Bi6T, SH$tcro ^7 A&SIfr UT t©-Cf WW L-7a > ft»!2, S -39- tz DAISY DAISY (Dynamically Architected Instruction Set from Yorktown) (iN 3 t v it (C b A LT PowerPC ihcday Y- V t°d ^y y —jpy y Y-v±cD^### A#%3 Y D-^/3 b ^o:y^#(:icTs >^f>yyAY7-% il/3 — b& A'CDSttoTlEB&yD-t: yitx ;xl/-'>3 > CD E >i< $ tl ^ y ,Dy ,Y'A&&'a ^$m<^<3_D-i/3>^ef6CA^B#ALX: VLIW yotvit^i^^ fr^^:#v7 c^yo^o:^ bcg#f ^ S&8*to&yY 7s>r T/bWI^^tiru^Siy:y$>^y:E[i]^-ou-riiSLtco C0# YcT^Bf^^^Y > b(i : 1. at)^o^^^^cD#ijm^#mD^ vLiw n- 2. t-u7D/f7A&#maL/=3>bD — ;i/7 d -^7 7©^^^M©x b LyA 3. yvitY%^mD^^^^mET^^AcDyot Jt Ltc VLIW3- p/\CD^#& Linux i A0H^f i: btf Linus Toravards tby>A — A LTtDt)oT^£ C ATr&ftl^n^ifcH Transmeta *±(i, E^fY^OSSfaS^'O 2000 ^ 1 D 19 B /:o ^It©vY £ nyD-feyit Crusoe Intel % CD 4: AY iV Pentium III A (i(^B)^CD##b&^(^tCD 1 (D'MWMXlX'MMLfz^ AY ib^tsroKt 7°n -fe v it*T? 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VLIW 3- h ;^ > taa-s c yi-rssi', 9->f"j h VLIW »s*a^x> h IJ k UTV-X Silt ia &A>o £«£■«: rftEJixv h u^j F©B*ft*5fr*fcix-2>o c©#*td: vliw 7T+)--f hvv^vr (ITLB) IFSfflvTISBItcfi&do L%x >x®^7 4?-e V, X> V IJ ntl'iSLl^CB, frt> b l: VLIW 3— H^fjSUV — ^>© r K V XSSglTJ) < 5>h,-Bo g. xr-=Vx^^ve©«^1-ilHf%^©^$ VLIW 3- a kx VMM liia»fflIlt«:of;^-Xr-^ x7^-v*^kx ^©^^&Efft"-6ilm)ffl vyx j'tu; W "E V ©ttffi&fSsS L&ttft «& 5>&l/> = C©fe©C SmArchktmrtC^it VUWCo*t VLIW1 c#i cr0*r3 r0 ■““ load r5'*0|r3) b vLj«a 0x0 a*i er0«*r?,0 nm 0x4 be erO.eq,Li A be erO.eq 0x8 load r5*6(rS> copy r5*r5'A\ l>2t b L2 b LI Figure 3: Finding the base mhiteciw instruction responsible for as exception m 1.2.4-3 (XEUU D) & ?-o<7X ^!J&7 ^ -;v b^T--7>£fflV& V737£"CkU VLIW i^(D7>-7B b U4W > b #\ VMM kL IWJMBh&ofc ji> b V TtW > - 44 - t%o b v ;tw > b izmMLtz^, ftfot b vx^st* ^)o VLIW 3— K4:T(Z)7 —bT(±. ^ —73—pf#'r#ftA/#ll#/;%byk#JGbfa#'%\ — o t 7 ^ -5 o h. RS/6000 Vy>4Vl/3>/W 1/ —S/s L. RS/6000 Jt© VLIW i/Ul/-^J3? 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D—P01/-r7>i>(t4itd'^;bo - H± SPARC ^:$#o /:/:L, 1/^7^ #Lo ^>f7-^7U^7AHTIt Mediabench 0 — gP 0 7 D 7 z? A £ ffl ^ fz [9] 0 Mediabench(t, UCLA!?##, 7^07077 7T&^oJpeg, mpeg, ##{b^^07D77A^A^Tt3^,4'#Ctl607D7 7 A0#^#^!#f/:6o a#o##r0t L^co a. ILP0mO ^f, VLIW^^p#!:a'0<^ cfua, vLiw ^^^0^0^ ft©7 >r — ;b F^LlzM LT, NOP !?&D, ^e^0VLIW^^P#0#!l^^#^L/:#R!:(d:^^o C0*§#&I3 1.2.5-9 to ##^^>7-7 — ^, $%#^##^#^0#AO$ (%) c 0@ 40 35 30 25 20 1 5 1 0 5 0 m 1.2.5-9 ILP ®mm -58- nnt- 0 gp CTtT E d MI M M M 4 cn o 4 & 3* m Ml % 1—* N: FE E d -1N3C0^UIO)nJC0(OO 4 * » S w nt E h-* 41 gp io 5$ rt gp st- ooooooooooo O' MI S* 0 0 S4 d w % 4 # io VP Cn n rT[~ gp 4 0 4: 4 Or d % cn E E h # CD % d adpcm.encode ^ ^ fX M aw t—' 1—1 aw O aw e>i 4 d # r a E 5 0 o' O n M » % < S? d H d adpcm.decode | ^ 4 r Or 4 <4 =t! 2fi Stl 0 S or e>^ gp 4: n E d St VP X d n X gp gp 3t id b> d bt Or gp 4 S 1C gsm.decode j—...... ■■■■■...... —j su i» ft d B> rT X. B> 0 C" ? 0 E 9 S r f< * gp 9-t Si jpeg.encode j d E e d SI & rv V m % O' n ! i ■d> Ml St I jpeg.decode j...... j (d A 0 E SF «P % E d 4 m to Sfc m E d X r cE mesa.mipmap |------1 & Cn bi S> St- j | id m 1—i 0 0 9S St gp o 1—‘ n§ Intel HP% IA64 T —/:/: L, IA64 TL^l^ (ko'T&^o i^ly^Ul/^iJtM, tSWUift&a ^c/:L, IA64 O'T&aZak:, ^3>;w ^,c ^(±m#-r(±^^o 1.9 1.71.8 1.61.5 1.4 1.3 1.2 1.1 1.0 e e ® e ® e ® e ® e ® a 0 c ® e e ® "O *o ■o TJ T3 ■o ■o ■o ■O ■o T3 <0 E e ■o ■o « -a ■o o o o 0 O o o 0 o 0 0 E M o o "g 0 o o o o 0 O o o o o o O % o o o o c ® c e c e ® c e c ® ® c ® c e ® ■o ® ■q ® ■q ■o V ■o ® ■o ® *o ® ® "O E 0 ® E E d d & E E bO m 1.2.5-n [##*$] [1] J.L.Hennessy, P.A.Patterson: Computer Architecture A Quantitative Approach, Second Edition, Morgan Kaufmann, 1995. [2] R. P. Colwell, R. P. Nix, J. J. O'Donnell, D. B. Papworth, and P.K.Rodman: A VLIW -60- Architecture for a Trace Scheduling Compiler. Proceedings of . Second Int'l Conf. on Architectural Support for Programming Languages andOperating Systems, PP.180--192, March, 1987. [3] M. Johnson: Superscalar Microprocessor Design. Prentice Hall Series in Innovative Technology, Prentice Hall, 1991. [4] J. A. Fisher: Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transaction on Computers, Vol.30, No. 7, pp. 478-490, 1981. [5] M.Lam:Software Pipelining: An Effective Scheduling Technique for VLIW Processors, SIGPLAN Conference on Programming Languages Design and Implementation, pp. 318-328, June, 1988. [6] M.Lam, E.E.Rothberg, and M E.Wolf: The cache performance and optimizations of blocked algorithms, Fourth Int’l Conference on Architectural Support for Programming Languages and Operating Systems, pp. 63-74, April, 1991. [7] S.A.Mahlke, R.E.Hank, R.A.Bringmann, J.C.Gyllenhaal, D.M.Gallagher, and W.W.Hwu:Characterizing the Impact of Predicated Execution on Branch Prediction, in Proceedings of the 27th International Symposium on Microarchitecture, pp.217- 227, Dec., 1994. [8] G.S.Tyson: The Effects of Predicated Execution on Branch Prediction, in Proceedings of the 27th International Symposium on Microarchitecture, pp. 196-206, Dec., 1994. [9] Chunho Lee, Iodrag Potkonjak, and William H. Mangione-Smith: Mediabench: A Tool for Evaluating and Synthesizing Multimedia and Communication Systems, in Proceedings of the 30th International Symposium on Microarchitecture, Dec., 1997. [10] S.A.Mahlke, D.C.Lin, W.Y.Chen, R.E.Hank, and R.A.Bringmann: Effective Compiler Support for Predicated Execution using the Hyperblock, in Proceedings of the 25th International Symposium on Microarchitecture, pp. 45-54, Dec., 1992. [11] S.A.Mahlke, R.E.Hank, J.McCormick, D.I.August, and W.W.Hwu: A Comparison of Full and Partial Predicated Execution Support for ILP Processors, in Proceedings of the 22th International Symposium on Computer Architecture, pp. 138-150, June., 1995. [12] 99-ARC-134-19, pp. 109-114, Aug., 1999. [13] A.Asato, E.Yamanaka. T.Ozawa, Y.Kimura: Compiler Approaches for Exploiting Various Levels of Parallelism, in Proceeding of RWC 2000 Symposium, pp. 71-76, Jan. 2000. [14] M.S.Schlansker, B. R. Ran: EPIC: Explicitly Parallel Instruction Computing, IEEE Computer, Vol.33, No. 2, pp.37 —45, Feb., 2000. [15] A.Nicolau, and J.A.Fisher: Measuring the parallelism available for very long instruction word architectures, IEEE Trans. On Computers, C-33, No. 11, pp968- 976,1984. - 61 - i.2.6 (l) littoK &£© < ofroft/gfl'SflciS^T*'!? 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[2] Wilson, R. and Lam, M.: Efficient context-sensitive pointer analysis for C programs, SIGPLAN 95 Conference on Programming Language Design and Implementation (1995). [3] Sites, R. et al.: Binary translation, Communications of the ACM,Vol. 36, No. 2 (1993). [4] /p#: Virtual Accelerator (3 L 7 —A P 7 Vol. 96, No. 231 (1996). [5] /J\#, ULl P: 7 U— ^ r;WlS7' < 5. n. P — 7 3 ><7)t&fp # #j^#,Vol. 97, No. 225 (1997). [6] /p#, iP^r, ill □ : 7##7 7 7 A Java Jog-time Analyzer - Java Virtual Accelerator ttT ©Y’iHf fffi - , : 7°D 7*7 ^ >7", Vol. 40 No. SIG(PR02), Feb. 1999. [7] Hammerstrom, D. W. and Davidson, E. S.: Information Content of CPU Memory Referencing Behavior, the 4th Annual Inti. Symp. on Computer Architecture (1977). [8] Bobrow, D. and Clark, D.: Compact Encodings of List Structure, ACM Trans, on Prog. Lang, and Systems, Vol. 1, No. 2 (1979). [9] Smith, J.: A Study of Branch Prediction Strategies, the 8th Annual Inti. Symp. on Computer Architecture (1981). [10] Young, C. and Smith, M.: Improving the Accuracy of Static Branch Prediction using Branch Correlation, ASPLOS VI (1994). [11] Yeh, T. and Patt, Y: Two-Level Adaptive Branch Prediction, the 24th Inti. Symp. on Microarchitecture (1991). [12] Nair, R.: Dynamic Path-Based Branch Correlation, the 28th Inti. Symp. On Microarchitecture (1995). - 71 - [13] #, /J\#, AB: 7 V ^ SWoPP97 (1997). [14] McFarling, S.: Combining Branch Predictors, WRL Tech. Note 36, Digital Equipment Corp (1993). [15] M. H. Lipasti, C. B. W. and Shen, J. P.: Value Locality and Load Value Prediction, ASPLOS VII (1996). [16] Lipasti, M. H. and Shen, J. P.: Exceeding the Dataflow Limit via Value Locality, the 29th Inti. Symp. on Microarchitecture (1996). [17] J. W. C. Fu, J. H. P. and Janssens, B.: Stride Directed Prefetching in Scalar Processors, the 25th Inti. Symp. on Microarchitecture (1992). [18] Eichemeyer, R. J. and Vassiliadis, S.: A Load-instruc-tion Unit for Pipelined Processors, IBM J. Res. Develop., Vol. 37, No. 4 (1993). [19] Sazeides, Y. and Smith, J. E.: The Predictability of Data Values, the 30th Inti. Symp. on Microarchitecture (1997). [20] Gabbay, F. and Mendelson, A.: Can Program Profiling Support Value Prediction?, the 30th Inti. Symp. on Microarchitecture (1997). [21] Joseph, D. and Grunwald, D.: Prefetching using Markov Predictors, the 24th Annual Inti. Symp. on Computer Architecture (1997). [22] J. A. Fisher: Walk-Time Techniques: Catalyst for Architectural Change, IEEE COMPUTER, Vol. 30, No. 9 (1997). 1.2.7 n7 y*-SUIF 7nyx ^ b CDhMT M WbSSE X fz SUIF 3>;W7[2][3]^#^L^m^Jfb^mm#, Parafrase ^7[6][7]&#a^ LTL-S & © £ UTtL & o (1) SUIF Explorer[l] SUIF >7 Monica Lam t & o X 'M&X U 3 W W 3 7 ©4 > 7 ^ £ UT&B Explorer HI 1.2.7-1 iz&to Explorer a. coarse ^ U Y > ft tz SUIF 4fe?0fb -72- Rivet visualize: m 1.2.7-1 SUIF Explorer t«08Mf6J. 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OpenMP ltA*A s#A£n/c Fortran V-X 7D 7 7 A14 A V X V 7 P 7 4 7X V [9][10]fftPtb L6^A£ Fortran 7P 77 A tC$#£flS „ C © 7 -4 77 U (43--—7 P ^;P©<6A—-0^7 P©X V 7 P 7 4 7*7 0 Tip So d. iTt ^ Jedit 14 A X X 7 7 XnJBt& X windows A AX hxr-f X T$i b, Tcl/Tk TSBizE A tl fc 7 7 0 7-'>3 >t7-f 77 V$lTiPSo Cft 14 Jstool[13] k»f.£7 7 7-7©-® k LTtg#t£ftTVSo SStptoXX'OPCSSIC OpenMP lgA*6#AT # S 4 7 &« (b6#3 Tla So X-^-*e.SALycV^}g^*6glRASe kte 4 b A AX P_t^© 1177# A^WtbT-feS, *fe, t3k%m@%mb#3>/W7©AX3>7'f A3i/-7 3>k$wx&So Jedit A>X —7zAX#3X7-f7t7 H:ff UT§Sl:3 >7 4 AAX SiiAnMSlA SA@k7X3©g|$4>A7>3 XSrHAASAfiSiStetttASo -80- e. f X 7 7 ^ HTGviz kmT###&#o<, HTG#;E^m^L, 3-K&HTG(D/-H:#J&2#ao - htg fawztm®?1 '-#2 3 4 5tmmy v—&*>%&{& ftmtirtzofaMit, nnm tfjcoMmk - xox^ A#^jfbaHTG HTGviz TBdlC^f S'OO^&t^f > —7ai-<7^i#X.Tl^o e ^%7^77#m m±0ckoC, GPE (±3>/W 7(:#T(±& <, t? L5^-if & D, >7-7 7^#x.Tv^o f x < z> bf&t)ti%>o [1] Shih-Wei Liao, Amer Diwan, Robert P. Bosch Jr., Anwar Ghuloum, Monica s. Lam SUIF Explorer: An Interactive and Interprocedural Parallelizes Seventh ACM SIGPLAN Symposium on Principles and Practice of Parallel programming(PPoPP), pp. 37-48, May 1999. [2] M. W. Hall, S. P. Amarasinghe, B. R. Murphy, S.-W. Liao, M. Lam, Detecting coarse-grain parallelism using an interprocedural parallelizing compiler, proceedings of Supercomputing ’95, San Diego, CA, November 1995. [3] R. Wilson, R. French, C. Wilson, S. Amarasinghe, J. Anderson, S. Tjiang, S.-W. Liao, C.-W, Tseg, M. Hall, M. Lam, and J. Hennessy, SUIF: An infrastructure for research on parallelizing and optimizing compilers, ACM SIGPLAN Notices, 29(1994), pp. 31-37. [4] M. Weiser, Program slicing, IEEE Transactions on Software Engineering, 10(4), pp. 352-357, 1984. [5] C. R. Calidonna, M. Giordano and M. Mango Furnari, A Graphic Parallelizing - 81 - Environment for User-Compiler Interaction, Intern. Conf. On SUPERCOMPUTING, pp. 238-245, June 1999. [6] Polychronopoulos C. D ., Gyrkar M. B., Haghighat M.R., Lee C. L., Leung B. P., and Schouten D. A. The Structure of Parafrase-2: An Advanced Parallelizing Compiler for Parallel Computing, MIT Press (1990) [7] Polychronopoulos C. D ., Gyrkar M. B. , Haghighat M. R., Lee C. L., Leung B. P., and Schouten D. A. Parafrase-2: An Environment for Parallelizing, Partitioning, Synchronizing, and Scheduling programs on Multiprocessors. Int. J. of High Speed Computing, 1,1 (1989) [8] Girkar M. and polychronopoulos C. D. The Hierarchical Task Graph as a Universal Intermediate Representation. Int. J. Parallel programming, 22(1994), pp. 519-551 [9] Polychronopoulos C. D. Nano-Threads: Compiler- Driven Multithreading. CSRD TR, Univ. of Illinois at urbana-Champaign(Urbana IL, 1993) [10] Martorell X., Labarta, J., Navarro N., and Ayguade E. A Library Implementation of the Nano-Threads Programming Model. In Proc. Of the 2nd Intern. Euro-Par Conf. 2(Lyon, France), pp. 644-649, August 1996. [11] http://graphics.stanford.edu/projects/rivet/ [ 12] http : //simo s. sianford.edu/ [13] The Jstool Application suite and libraries, http ://www 1.shore .net/~js/jstools/ [14] OpenMP Organization, Fortran languages Specification, http://www.openmp.org/openmp/mpdocuinents/ [15] Welsh B. B. Practical Programming in Tcl/Tk. Second edition, Prentice Hall(1997) [16] #r:c4v^- - w) 7 D 10 NEDO-PR-9809. 1.2.8 n WM 7 ©t$SBSMS©f$Wib[R] HjIpKcou-C (l)tlin > tfi — n > — (S)Zi±Z2 >;w 7%#g#@©4-#©& t> is Hon (i) Lf ©He#R0#SM&f^>f?-57D77A4v-Xt 6, kVd ITStt^bCfttt, i/Z=rh - 82 - — g##^IJ{b3 >/W7§afe3>/U7® cco&ax @m^^j v —^ 7°d ;W ;f Lfcn — F £%rM&Ui% C3 >/UJV lvfc3 — F#^iH-##±'T(D^fjR$fa]<#f & ^^9 ^©T'fe^o (C ^\ > ^- T — ^7 (benchmarks ;£ fc benchmark suite) — ^ 7” D ^7" 7AW:v-%3- F ^ u-cmmzfiao ^7—^yo^^A : ^ b y& j6^ij{b^#^ LX\^tztz®>, u^ yo^7 A^: X ^ tzo L- (D &. o t£^y ^ — 5? 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L/Tx ^>f7-^yn^7A®^i4 • ]E=M##gg#) 6:H& - ^yoy^A#v —yny-yt^h.—M^#(zX#i#(yDy7A(Z#ff#^ p^yyK yyoy^±#aj:o^yDy7A^m^^(:(±^<®@m^?^^^^o yuy^ Aa uymi^}:(±mT(D #c,j;o%R0mA^A#^L^ ^yyyy-s/a Uft&fc b &i^o - ^#^'T^t)fiyi^yDy7A(±/<>^'7-yyDy7AaL/ymto-c$)^^, - - ^;M#yy v y —s/3 >yoy^ A0#A(±M#f^0y >yy>yny - f ^h0#f##T^ew#&ct o ^:yu y^ A&^t-y >yf < ##;% • $^yoy^ < (D#t##%r#ffW#bky ^ ^yyv —^ yn y^ AGDaBx&fc^ffl£*iTi' $>5oo #t:yot—y (D^1f#MC6#^J -93- mtmmvmMtLTiz, ^©iitfo^toufTii ^m^x^^cDtzi-f^u^i, m &&:/n-fe y+h£Erc:Slfi:t"£ c h £ £ b £t£tb#;W/fbf'£ ^ bv^o fc, 3 - pcDX/r-7 u Vf-J 0##-^, ^>c kt: j; #a^6T&50o &tz-D tit tlfz^ — \s®Wb^'o fctJScDffe^ vxyo&.o v < o . .%-ifkCM' fb y —;k & £' L C^i^cDACM LT t)+^B &lo|U"Tl^(J^U^^ G&tG [1] Lyle Kipp, Perfect Benchmarks Decumentation Suite 1, CSRD University of Illinois at Urbana-Champaign, 1993. [2] Lyle Kipp, Perfect Benchmarks Benchmarking and Optimization Guidelines Suite 1, CSRD University of Illinois at Urbana-Champaign, 1993. [3] M. Berry, et al, The PERFECT Club Benchmarks: Effective Performance Evaluation of Supercomputers, Int’l Journal of Supercomputer Applications, Vol.3, No. 3, p.p.5-40, Fall 1989. [4] George Cybenko, Lyle Kipp, Lynn Pointer and David Kuck, Supercomputer Performance Evaluaiton and the Perfect Benchmarks™, Proc. of ICS, Amsterdam, Netherlands, p.p.254-266, March 1990. [5] Williiam Blume and Rudolf Eigenmann, Performance Analysis of Parallelizing Compilers on the Perfect BenchmarksTM Programs, IEEE Trans, of Parallel and Distributed Systems, Vol. 3, No. 6, p.p.643-656, Nov. 1992. [6] Rudolf Eigenmann, Jay Hoe Ringer and David Padua, On the Automatic Parallelization of the Perfect Benchmarks, IEEE Trans, of Parallel and Distributed Systems, Vol. 9, No.l, p.p.5-23, Jan. 1997. [7] Rudolf Eigenmann and Siamak Hassanzadeh. Benchmarking with Real industrial Applications: The SPEC High-Performance Group. IEEE Computational Science and Engineering. Vol. 3, No. 1. Spring 1996. Pages 18-23. [8] Rudolf Eigenmann, Greg Gaertner, Faisal Saied and Mark Straka, Performance -94- Evaluation with Industrial Applications, Purdue Univ. School of ECE, High- Performance Lab, ECE-HPCLab-98211, Oct. 1998. [9] SPEC High Performance Steering Committee, SPEC Run and Report Rules for SPEChpc Suite, http://www.spec.org/hpg/runrules.html , 1996. [10] SPEC, readmelst.txt, runrules.txt ,http://www.spec.org/osg/cpu2000/docs , 1999. [11] David Bailey, et al, The NASParallel Benchmarks, International Journal of Supercomputer Applications, Vol. 5, No. 3, p.p.63-73, Fall 1991. [12] David Bailey, et al, The NAS Parallel Benchmarks2.0, NASA Technical Report NAS-95-020, NASA Ames Research Center, Moffett Field, CA, Dec. 1995. [13] Roger Hockney and Michael Berry, Public International Benchmarks, PARKBENCH Committee Report-1, http://www.netlib.org/parkbench/ , 1994. [14] F.H. McMahon, The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range, Technical Report UCRL-53745, Lawrence Livermore National Laboratory, Livermore, Calif., Dec. 1986. [15] J.J.Dongarra, The LINPACK Benchmark: An Explanation. Supercomputing, Spring 1988, p.p.10-14. [16] J.J.Dongarra, Performance of Various Computers Using Standard Linear Equations Software in a Fortran Environment, TRMCSRD 23, Argonne National Laboratory, March 1988. [17] D. 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J.Kapasi, 7 7 7 7 3— K Ac#) 7;rMyM-e(i, i#^c io"eir&0;m#<&#a& %>o Z(Dfz&, 1 yot V^^0####0#^(^A ^,o c^o, D^7^77Aih0^m, ###m0m#@m 777®#, ^rr(i, D^7^7TA;h0#^^#h%&, ®#, m#mm, mmmii03A&6i±## M 0, 7' D —W1/& 7 7 7 7 7 y A UT, 7777 7 195 ^01, 20 ^01, 430 #01 c c, ##0mT& 8%}: - 139 - v—'>a ysmuttz g. -eofifeOfgH -Y U y 4" A#® J.Torrellas 6> ti, ^Toward a Cost-Effective DSM Organization that Exploits Processor -Memory Integration j kSLTSSSSffofco 7D -fe y 4" © cf1 ifi tt > PDA PIM(Processor in Memory)7r kffllutSt^i£*>, PIM 4$) V'Tk'®J;di: DSM S$S1-nii, DSM AsHS-eS3; (5) SE&autfflfllr® 4-0®si*s* dt, #ic*#®e%-ea, stsi-e-r <-{®x-5 »E^A45%lcfi:t>nTt'?,tS4a5ttoTE!$U7c<, ^ET-tiy «x« rl;'®7D77Ai; M7D77 A40KtC^E>-&5 fciWtfJft'j tft EPowerPoint^Excel^Java-® ®7D 77 At ffflggX V y P As<$ftft-tV'3©;tPj E x lz y Ptt*60±® teiACIB f^e,n-cv>5,®A\ znt&xu s. >y±, jFc (6) 7D77AIS1 HPCA-6 ®yD7'7A4U.TlCSt-fo - 140 - Keynote speech Relaxing Constraints: Thoughts on the Evolution of Computer Architecture Joel Emer, Compaq Computer Corporation Session 1: System Architecture Tradeoffs Impact of Chip-Level Integration on Performance of OLTP Workloads Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese Compaq Computer Corporation Toward a Cost-Effective DSM Organization that Exploits Processor-Memory Integration Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen University of Illinois, Urbana-Champaign; Sun Microsystems Impact of Heterogeneity on DSM Performance Renato J. Figueiredo, Jose A. Fortes Purdue University Session 2a: Memory and Cache Session 2b: Networks Design of a Parallel Vector Access Unit for SDRAM Memory Systems Flit-Reservation Flow Control Binu K. Mathew, Sally A. McKee, John Li-Shiuan Peh, William J. Dally B. Carter, A1 B. Davis Stanford University Department of Computer Science, University of Utah Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area ; Modified LRU Policies for Improving Networks Second-level Cache Behavior Rafael Casado, Aurelio Bermudez, ;i Wayne A. Wong, Jean-Loup A. Baer Francisco J. Quiles, Jose L. Sanchez, Jose University of Washington Duato Universidad de Castilla-La Mancha; Umversidad Politecnica de Valencia extended Block Cache In vestiga ting QoS Support for Traffic Mixes Stephan Jourdan, Lihu Rappoport, Yoav with the Media Worm Router Almog, Mattan Erez, Adi Yoaz, Ronny Ki H. Yum, Aniruddha H. Vaidya, Chita R. Ronen Das, Anand Sivasubramaniam Intel Corporation Penn State University Session 3a: Multithreading and Session 3b: Shared Memory Micro architecture Design and Performance of Parallel High-; Quantifying the SMT layout Overhead - Throughput Coherence Controllers Does SMT Pull Its Weight? Ashwini Nanda, Anthony-Trung Nguyen, James S. Burns, Jean-Luc S. Gaudiot Maged Michael, Douglas Joseph use IBM T.J. Watson Research Center; University of Illinois, Urbana-Champaign Software-Con trolled Multithreading Coherence Communication Prediction in \ Using Informing Memory Operations Shared-Memory Multiprocessors Todd C. Mowry, Sherwyn R. Ramkissoon Stefanos Kaxiras, Cliff Young Carnegie Mellon University; ATI Bell Laboratories, Lucent Technologies Technologies, Inc. - 141 - Dynamic Cluster Assignment Mechanisms Improving the Throughput ot Ramon Canal, Joan Manuel Parcerisa, Synchronization by Insertion of Delays Antonio Gonzalez Ravi Rajwar, Alain Kagi, James Goodman Universitat Politecnica de Catalunya - UW Madison; Intel Corporation Barcelona Keynote speech 2Kpapers on caches by Y2K: Do we need more ? Jean-Loup Baer, University of Washington Session 4: Software Techniques On the Performance of Hand vs. Automatically Optimized Numerical Codes Marta Jimenez, Jose Maria Llaberia, Agustin Fernandez Universitat Politecnica de Catalunya Cache-Efficient Matrix Transposition Siddhartha Chatterjee, Sandeep Sen The University of North Carolina at Chapel Hill; UNC Chapel Hill and IIT Delhi A Prefetching Technique for Irregular Accesses to Linked Data Structures Magnus Karlsson, Fredrik Dahlgren, Per Stenstrom Dept, of Computer Engineering, Chalmers University, Sweden; Ericsson Mobile Communications, Sweden Reducing Code Size with Run-Time Code Decompression Charles Lefurgy, Eva Piccininni, Trevor Mudge University of Michigan Session 5a: Prediction I Session 5b: Parallel Systems Decoupled Value Prediction on Trace The Effect of Network Total Order, Processors Broadcast, and Remote Write Capability on Sang-Jeong Lee, Wang Yuan, Yew Pen- Network-Based Shared Memory Computing Chung Robert Stets, Sandhya Dwarkadas, Dept. of Computer Science and Leonidas Kontothanasis, Umit Engineering Soonchunhyang Univ., Rencuzogullari, Michael L. Scott Korea; Dept, of Computer Science and University of Rochester Engineering,Univ. of Minnesota Branch Transition Rate: A New Metric PowerMANNA: A Parallel Architecture for Improved Branch Classification Based on the PowerPC MPC620 Analysis Peter M. Behr, Samuel M. Pletner, Angela Michael Haungs, Phil Sallee, Matthew C. Sodan Farrens GMD FIRST University of California, Davis A DSM Architecture for a Parallel Combining Static and Dynamic Branch Computer Cenju-4 Prediction To Reduce Destructive Takeo Hosomi, Yasushi Kanoh, Masaaki Aliasing Nakamura, Tetuya Hirose Harish G. Patil, Joel S. Emer C&C Media Research Laboratories, NEC Compaq Corporation Session 6b: Parallel Systems Session 6a: Prediction II Performance - 142 - Memory Dependence Speculation Trade offs in Centralized, Continuous-Window Evaluation of Active Disks for Large Superscalar Processors Decision Support Databases Andreas Moshovos, Gurindar S. Sohi Mustafa Uysal, Anurag Acharya, Joel Saltz Northwestern University; Computer University of Maryland, College Park; Sciences, University of Wisconsin- University of California, Santa Barbara Madison A Technique for High Bandwidth and Investigating the Performance of Two Deterministic Low Latency Load/Store Programming Models for Clusters of SMF Accesses to Multiple Cache Banks PCs Henk Neefs, Hans Vandierendonck, Franck Cappello, Olivier Richard, Daniel Koen De Bosschere Etiemble University of Gent CNRS, LRI Performance Analysis and Visualization ot Trace Cache Redundancy: Red & Blue Parallel Systems Using Sim OS and Rivet: A Traces Case Study Alex Ramirez, Josep L. Larriba-Pey, Robert P. Bosch, Chris R. Stolte, Gordon W. Valero L. Mateo Stoll, Mendel W. Rosenblum, Pat W. UPC-Barcelona Hanrahan Stanford University Keynote speech Networking At Home - Directions in Connected Computing for the Consumer Kevin Kahn, Intel Fellow and Director of Communication Architectures Lab, Intel Session 7: Novel Architecture Issues Register Organization for Media Processing Scott Rixner, William J. Dally, Brucek J. Khailany, Peter J. Mattson, Ujval J. Kapasi Stanford University Architectural Issues in Java Runtime Systems Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy K. 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V y XT'doiU'BEB Globus cn&©+»■—tr^ii/i>Bicj®dtibsij count'sceast* 3 - 163- Access Protocol) k ID 7 t7 ^— 7 ("T 4 V 7 b ]))\Z.'T 9 X't' %> tz &)Ot®*P 7 D b 7" —7 a >7°n7'7 < >7X >7 7 x — 7 http://www.globus.org/mds/ 0^-70 GCI 77V7b&il=amfflU\ Globus b%Ib #b#W:mf &##&#&c a#-?#&<) (4) £fc>0£ CCC^g^U/c 707^7 b(±c:<—gpco^T&^o 7 U^.—7 ^ >7(:^ frtlZX'&Z o $>®\£ Grid Forum #&£<> ^ CT' Grid h 7 <7)U:j£fi^S(7 >b°zL — 7^>7"£>fcffl©7D7:ii7 b&UCRf f xrlc^^cD 6 U k 10 U $^t/co #An#(± #&07-jr7777i/-7ia-na#9 OT&&0 • Scheduling Working Group (Sched-WG) • Grid Information Service Working Group (GIS-WG) • Security Working Group (Security-WG) • Remote Data Access Working Group (Data-WG) • Application and Tools Requirements Working Group (Apps-WG) • End-to-end Performance Working Group (Perf-WG) • Advanced Programming Models Working Group (Models-WG) • Account Management Working Group (Accounts-WG) • User Services Working Group (Users-WG) >Un.—T--r >^PI?t^^0^y£T*li"FaB ©$£>#& D > tuTftS 7 X* n — ^ x. -2) o • 3/15-17 7" O — A )l k 7 7 7 7 U > h° a — X 4 > 7"k: [H11~ £ 7 — 7 7 3 7 7° (WGCC2000)' , • 3/22-24 7" U 7 b 7 ;t “*7 A(Grid Forum) 12 ^ 3 4 7ir 4 rb • 7/18-21 4* 7 7 — * 7 b*>7yl/>7 (INET2000)\ ii/P>7>f 3 - 9 H 7 V 7 F7X--7 A. • 11/4-10 SC2000\ ^0777$ 1 http://www.trc.rwcp.or.jp/ 2 http://www.sdsc.edu/GridForum 3 http://www.isoc.org/ 4 http://www.sc2000.org/ - 164- 2.2.2 S^M5j$ri&fnJSl3E : Grid Forun 99, U.C.B., JavaGrande Portals Group Meeting C&tf & tiSS/lnj A;i/3 > b°iL— y 7 >7", Grid ®, £ 41 fob b 3 !H^£ £<£ftjC f®^^, fTrC Grid Forum anfw:ti6 Grid###/:#)® IETF #f&®ej^^j:77 -<®#^##'r##^ti/:7777&, —7-e^AL, 7^ v77%*^6 PDA Web #2:"®^ H7 L, -B ®±®yyV 7 —i>3 ^#Ag7—Ify tlTV^o G tlGCDib^^tb^, ##g®^7 H)/7^3 >P#;0^#® 0 — ^7 — (1) The Grid Forum fK0H ¥$1 1^1 0 0 1 80~¥$1 1^1 00 2 3 0 (60^) The 2nd Grid Forum Meeting (1999.10. 21~ 10.23) '>*d ’ffG y 7 U * Grid Forum( 7' U v F 7 t “ 7 A ) (http://www.gridforuin.org/ )U:@j£; # ###b #t #, #1# Grid Co^T®#&^®3 >V —7TAT&6o 1999 ^SC&^T NCSA, NPACI, NASA, DOE ASCI & 1999 ^fFCA® 7-773 CCDot,, 10/21-10/23®^, )Km7^^CT 10^1AI±# ADD, ###C#imL, 0*®Grid^#®#fq|&m^L^o #xH® Supercomputing ’99 4b, BoF (Birds-of-a-Feather Workshop)/) 5 HI #^ti, The Grid Forum a v7®#^^et)a^o The Grid Forum ®7§Wj(d: Internet Engineering Task Force (IETF) —7 A It l^/)5, IETF #1# Grid Co DT©7t-7At'fel,o IETF k|a]#, «lb®}Iffl&®$i]7£C £ o X Grid ®77f 4 tAx 'i £: 7°U B: — v 3 > G, ®)##C^3G»T (d: r^tft® n*^(rough consensus)j b ^ n — F (running code ) ® H >f< (o ;£ 0 , #0", ^ tOt ^ 17, ^G'OCai^^^aLTV^o The Grid Forum (±, #%, l^T® 9 ®7-=t>7"TOk-7(WG)T#M2f!-t!7ao ztiztuD wg ii Grid®mij®###ma&@^ o, m#8yC(±0#^tm#Ib^#(RFC &*> Draft Proposed Standard)® Ufe* 0 life U TC-BtlB-fl® 7 — A-> 701/ —7°® Chair, mailing list, webpage, 4o ck 77 PFl ^ ^ ^J #^7 %> o - 165- (D Scheduling Working Group (Sched-WG) Interim chair (s): Bill Nitzberg, [email protected] , Jenny Schopf, [email protected] Email list name: [email protected] Web page: http://www.nas.nasa.gov/~nitzberg/sched-wg/index.html — V ——713 Grid (2) Grid Information Service Working Group (GIS-WG) Interim chair(s): Gregor von Laszewski, [email protected] Email list name: [email protected] Web page: http://www.mcs.anl.gov/gridforum/gis Gis-wG a Grid ath-c XML (3) Security Working Group (Security-WG) Interim chair(s): Randy Butler, [email protected] . Andrew Grimshaw, grimS-hxi_w_@„v.irgi.nia J£.cLii Email list name: [email protected] Web page: ??? -te n. 'Jr>f © WG tJ Grid & I^EE(authentication)jo J: If qj (authorization) Gi §lj ih — PKI I'Zid' >7 (D Remote Data Access Working Group (Data-WG) Interim chair(s): Micah Beck, [email protected]. Reagan Moore, moore@sdsc. edu Email list name: [email protected] Grid heterogeneous iZjiZMlZftWL U fz remote data & ~T ' *? * 9fai& M&> fz Data Grid tlx at# Grid i:©jft W t iEfScIn (transparency) IZ J; C - 166 - Mitttemmibhzmt %), o Data-WGTUu Ztlt>(D& (D Application and Tools Requirements Working Group (Requirements-WG) Interim chair(s): Fran Berman, [email protected] . Bob Hood, [email protected] Email list name: [email protected] Web page: http://www.gridfbrum.org/www.ncsa.uiuc.edu/People/novotny/apps/index html C® WG TUG V /r—>7^ Grid — \ZftLT ¥(D£o %o li®77 © End-to-end Performance Working Group (Perf-WG) Interim chair(s): Mark Gates, [email protected] . and Valerie Taylor, [email protected] Email list name: [email protected] Web page: http://www.dast.nlanr.net-/Perf-WG/ Perf-WG U: Grid & WG T&&o a < (2) "En* — — (3) (4) © Advanced Programming Models Working Group (Models-WG) Interim chair(s): David Bader, [email protected]. and Craig A. Lee, [email protected] Email list name: models-wg@gridforum,org Web page: http://www.eece.unm.edu/~dbader/grid/ Models-WG Ji Grid ft7 7'J ©-'> a - 167- ® Account Management Working Group (Accounts-WG) Interim chair(s): Tom Hacker, [email protected]. and William W. Thigpen, [email protected] Email list name: [email protected] Web page : htt_pjl/www_lnas_,_nasa..go.Y/~iM^pen/_a_c_co_iLnts-.ws WG (D User Services Working Group (Userserv-WG) Interim chair(s): Rita Williams, [email protected] . John Towns, [email protected] Interim secretary: Email list name: [email protected] Web page: http://dast.nlanr.net/UserServ-WG/ WG $ 3 — D y :fe U £7" ]) y K©rS WjtLX^ European Grid initiative(egrid; http://www.egrid.org/ ) v7"(± 2000 ^ 3 B 22-24 (Dm, J (2) U.C.B., JavaGrande Portals Group Meeting fKBfl : fhRl 1$U 2B 6 B-fm 1 1^1 2B 1 1 B (6 BR3) IMS : y^' —7 L — TfU +h> 7 7 >7 77 rR,T7 V ;£? 12 B 6 B^6 12 B 10 Bomm, > 7 7 > 7X 3 ££ & tf UC Berkeley 0 EECS (D David E. Culler Wk, *5 - 168- LTBieL'3o $,.E>„ ^©fe©Cli^**g+*i: I/O ©tgXnb sSSCr X-bX njggT-fcS-il-S , |+S*f*©5 :'"-Xjp|+**©^ 5 ^ v-->3 >, t Ti'SIsJiSki' >XX X -> 3 XT-SS&S^ifcS,, ^©J;o»iSte&t6#lt'-5* m#^xxf-A©«#&«, $c»B3m#©3>^-*> hfr'ffiscjSELTX^'i'y > h<. ^-©gei&xxxAk v,xmw Tifc-5 i;#x-5(L'Stt* < *3o t? L3> SStt^tienfflyxu^-Xs >c*kM'g &dS( AX t- Al:iot7D/r- Uh5, k © - 170- • Berkeley Multimedia Research Center • lnierne.t.Si;ale„.Sj„s.t.e„ms.E.e.s.eMeh„Pjx>Mci- • Digital Libraries • Computational Astrophysics • Reconstructing the History of Life in Integrative Biology • Computational Finance • Chemistry • Civil Engineering • Economics • Ge.olo„gy.„„and..0.e„Qphy„s„ic.s.. • Parallel Computing for Optimization and Simulation in Complex Manufacturing Operations (IEOR) • National Energy Research Scientific Computing • Mechanical Engineering • M.ath_e.m.atic.&. • National Airspace System Simulation • Patient-Based Optimization and Treatment Planning for Neutron-Based Radiation Therapy of Brain Tumors (Department of Nuclear Engineering) • Physics • School of Information Management and Systems • Technology CAD Berkeley VIA CD ^^[4], # —bl/v^^CD^>f-T — 9 £>tl& [2] [3]0VIA Cornell I### cF tlfz U-net £ l'* o Active message CD f§ M ^ © if! V dr — y '> > £7t CG Intel £ CDIdJfiiff%Tr User-space low-latency ifBiiy y V 'y O £1*^ O & CD 1!\ £ft VIA CD fill % & fr o X O' £ o Millenium T: li Berkeley HE CD VIA £ L"£G NOW "Chi O C tlT O £ O h^'y hy — PT&Z Myrinet D v # [##%#] [1] REXEC: A Decentralized, Secure Remote Execution Environment for Clusters. Brent N. Chun and David E. Culler. To appear in 4th Workshop o n Comm unication. Architecture, and Applications for Network-based Parallel Computing . Toulouse, France, January 2000. [2] Architectural Requirements and Scalability of the NAS Parallel Benchmarks. Frederick C. Wong . Richard P. Martin. Remzi IP Arpaci-Dusseau . and David E. - 173 - Culler. In Proceedings of Supercomputing '99, Portland, Oregon, November 1999 [3] Millennium Sort: A Cluster-Based Application for Windows NT using DCOM, River Primitives and the Virtual Interface Architecture. Philip Buonadonna . Josh Coates , Spencer Low, and David E. Culler. In Proceedings of the 3rd USENIX Windows NT Symposium, Seattle, WA, July 1999. [4] An Implementation and Analysis of the Virtual Interface Architecture. Philip Buona donna . Andrew (lew eke, and David E. Culler In Proceedings of Supercomputing '98, Orlando, Florida, November 1998 • Ninja Project (http://ninja.cs.berkeley.edu/ ) Millenium Ninja — —a C JLLTV^o PDA Ninja A scalable Internet services architecture. 13 2.2.2-2 #t#*maLT(D"Base"WA ^/r-^yil/^NOWCDZo^ persistent u, workstation PC PDA, Units — #1: PDA T L,/7^T7> P#6D3 — P^mb^T/zU®/^ —^t#/z%V'oC(Di#'&,Base^6 Active Proxy > P P^y^>D- P^fl, Unit Ninja : • Structured Partitioning of State: o Ninja 0 T —A" T" Z7 V U persistent &tAS - 174- Staff and Visiting Researchers • Reiner Ludwig • Luis Barriga • Junichi Hagiwara [1] Jaguar: Enabling Efficient Communication and I/O from Java, Matt Welsh and David Culler. To appear in Concurrency: Practice and Experience, Special Issue on Java for High-Performance Applications, December, 1999. [2] The MultiSpace: an Evolutionary Platform for Infrastructural Services, by Steven D. Cribble, Matt Welsh, Eric A. Brewer, and David Culler. Proceedings of the 1999 Usenix Annual Technical Conference, Monterey, CA, June 1999. [3] An Architecture for a Secure Service Discovery Service, by Steven E. Czerwinski, Ben Y. Zhao, Todd D. Hodes, Anthony D. Joseph, and Randy H. Katz. Fifth Annual International Conference on Mobile Computing and Networks (MobiCom '99), Seattle, WA, August 1999, pp. 24-35. [4] The Ninja Jukebox, by Ian Goldberg, Steven D. Cribble, David Wagner, and Eric A. Brewer. 2nd USENIX Symposium on Internet Technologies and Systems, Boulder, CO, October 1999. [5] A Document-based Framework for Internet Application Control, by Todd Hodes and Randy H. Katz. 2nd USENIX Symposium on Internet Technologies and Systems, Boulder, CO, October 1999. b. JavaGrande Portals Group meeting (1999 ^ 12 H 7 0) (http://www.javagrande.org ) JavaGrande Portals Group Java tf'O h LT lb > b° n. —4 > [§|eN “ The JavaGrande Forum distributed computing working group ^(Grid 3 IETF 0Z3&## chUGS^PfbS: UTUt" The Grid Forum (http://www.gridforuni.org)0 IT - 177 - 2.2.2-1 JavaGrande Portals Group meeting Z7°D Duration If Topic | I it . ti 5 11 ! {Start 8:30am 1PART 1: Introduction ii ____ i 20 minutes | Datorr, Computing Portals, and Science Portals, Dennis f \Gannon, Pyuish Mehotra jj J30 minutes |Science Portals, Geoffrey C. Fox j PART II: Talks by Industry and Researchers j |s0-40 minutes pPlanet, Sun Microsystems { | 30-40 minutes je-Speak, Hewlett Packard j 30-40 minutes Ninja, UC Berkeley j 30-40 minutes NPACI Hotpage j __ \ Lunch | PART II: Working groups j {overlapping Group A: Computing Portal Frontends and Architecture j jWorking Groups This might include discussions about the Computing j Portals previous working groups, as well as, some proposals) that are submitted to the Gridforum in the area of the 1 [backend. j Group B: Industrial Portals | This might include discussions on how existing technology | lean be used and enhance Computing Portals in j jjexisting/future industrial applications and frameworks | ! Other groups upon suggestion by the community j | PART III: Summary | ^@(7) ^-7"4 y^xit, y v 3 wo c tt$t$)T±) X ^TXMtf) ^>tlX c? fz Grid 4o - 178 - An Object-Oriented Framework for Parallel Simulation of Ultra-large Communication Networks Dhananjai Madhava Rao and Philip A. Wilsey Computer Architecture Design Laboratory University of Cincinnati - Cincinnati, OH, USA ARAMIS: A Remote Access Medical Imaging System(short) David Sarrut and Serge Miguet Laboratoire ERIC -Bron Cedex - France Language Interoperability for High-Performance Parallel Scientific Components Brent Smolinski, Scott Kohn, Noah Elliott, and Nathan Dykman Lawrence Livermore National Laboratory - Livermore, CA, USA A Framework for Object-Oriented Metacomputing(short) Nenad Stankovic FSJ Inc. - Naka-Meguro, Meguro-ku, Tokyo, Japan Tiger : Towards Object-Oriented Distributed and Parallel Programming in Global Environment (short) Youn-Hee Han, Chan Yeol Park, Chong-Sun Hwang and Young-Sik Jeoung Korea Uni versity - Seoul, Republic of Korea (3) ### HPC by - 180- n y bn.-if- d * ‘,kU''Grid:3ybn.-A-f >ytji5!;i'i/;. $l:&#:t#©yr b A-y a y©A& 61\ d- y -y h ©(*❖* J-—if Cft-f SA -KXtSfttSfeiiKS^'n'?-^ HPC, A5»$Etot3t,. iS3pmCSe6«MsiW* ofeo LTtt, ?7X^3>lfa-f-( >y?lt b TFLOPS, Xf'jlT/iO, P /W h»©-*IBfi*liix.-5 * 7X^sHS®if#?*jntl>5, $ fc, Chien © A *§« t « » S 7J H T* » + gflops ©*mte###*w#r& t,, ^#©#fu #+##©#%%%:#& ii^&^tiTtySAL *>A sH©y — * —lixvo >S±^*T-$> 0, ttlSttiSiiTiy S b ux =fc -5 o *fc, Grid nybn.-Ad' y^ti, d1 > h ©S» k Sa&MiifblcfiH', TFLOPS «©§+*«, iifflST -^^/W MS©* F V Gigabit S^SfS Gbit © WAN kC«toTiWeig|+®* ‘d:tf€©5:-'-j'-fey b StSSStcjS# ■r^fctoffllted'A-efe^*s, x-tp^y^-r 7®'Mm^£.z>'mmw>mt\n, ^»©-by-9-©vni/j'd - am , Azv Digital Library ©A9/W MS©?-£ ©A'- f ^-XM, lt*«4alBTffi-5 bt'y!gt;tttt*o-C*3?>'f . ^*©Itffd' >77©iittj:?,5J 8&tt* sfcSo *Brti;C© 2-3 NGI iSAW Internet2 % b'©@A#m%@ftd' yX-r y h b»P(SLr, SSCa- h\ 7 7 1, DB, * J;tFA Wft-f >770Sii|iIlflTl'-5. 7D77At L T & 133 ji E © Alliance, DOE© DOE2000, NSF © NPACI, NASA © IPG, DOE/DOD © ASCI DISCOM &k'#& b, 5i A&E?Eil4/I>s7} ffjiAS ftoo ai?> S <, M A H SDSC (San Diego Supercomputing Center—NCSA fcHfcV NSF © 2 *X-t13yea-f-f y XA y £ ®-o)T*tt, 50% &l±ostwmsmiz npaci cgbiAHtr Ab, NASA &Eg%m©xA3 'sltt^T Grid © V 7 h L, G/75 (CjglS'f S C. i; SAMftC LT © So Crawford MffliSOidt, ASCI T* H AE^lft £ TFLOPS #^(,4*# PFLOPS *©H-K«£l®»8!ILT^<-S, E^Sf®$ 100Gbit E©Bgi§-fb* y h V -XTISSL, Grid H*&ffaite$ilTTV'^<, -AfctfH© X-*, A#, jbATT E^Srttc©'$n*e.ttS^:C8ti)Bd:nT* b, hpc * au ** hpn ©m,#t:A < op (Sr* s f t; t' s © *ssttr $, s „ Kifflidiy 3®ttr*(d;t>* 5Bttt'*KP#r/oy±r©%* Sfflrru©tt|g|cg±©*tCy< —, E%#, +f©MiC,'* si±* snr*b , f rtisisa^wtcftifift hpc • hpn ^©AyX'd - A77 bt*bsnri3b, s e>tx hpc 03Uzf t LTV'S©»sSttrafe So -tiJ6¥<*B©Stt& HPC jbcktH yX-*y 103U-f-(MiL, fflS ffiA'J'SrfcfltfcoT Network Supercomputing ©Hr Lf''ttt^C[S|lPfeE5SRB^4b d" yy^sfitciqiA^o^tgrifeSyo - 181 - NCSA Supercluster f TIZ production use Tf 24x7 T'lsBb LTD , ^ Origin, T3E, 10#jg V'— ^7 cF tifz t)Ss C C T'JJ 2D Navier Stokes CD Pi $: tf o ^^07 7 V Zeus-MP (256P, Mike Norman) ISIS++ (192P, Robert Clay) ASPCG (256P, Danesh Tafti) Cactus (256P, Paul Walker/John Shalf/Ed Seidel) MILC QCD (256P, Lubos Mitas); QMC (128P, Lubos Mitas) Boeing CFD Test Codes, CFD Overflow (128P, David Levine) freeHEP (256P, Doug Toussaint) ARPI3D (256P, weather code, Dan Weber) GMIN (L. Munro in K. Jordan) DSMC (Ravaioli) FUN3D with PETSc (Kaushik) SPRNG (Srinivasan) MO PAG (Me Ke Ivey) Astrophysical N body codes (Bode) Parallel Sorting (Rivera - CSAG), 10.3 GB Minutesort World Record AS-PCO MM Perfemmride»S3 Navier Stokes Kernel 20 18 4k v; \’i , 16 > ' r”. 5 .'i . ?<: < 14 ...... # 12 10 mr .... * ♦ Ml O20M. 250 WU R1KM0 NT Out* a* 950 FMI Ms 9 32 128 180 192 224 256 Processors mn 2.2.3-4 NT 0 Origin2000 £ - 185 - $ tzn ffe© NT Cluster t LX ^ Sandia's Kudzu Cluster (10/98), Cornell's AC3 Velocity Cluster (8/99) frgtlfco 10 {%LL±CD=1Z X — £$8££tl NT Supercluster, NCSA - http://www.ncsa.uiuc.edu/General/CC/ntcluster/ , - http://www-csag.ucsd.edu/projects/hpvm.html AC3 Cluster, TC - http://www.tc.cornell.edu/UserDoc/Cluster/ Communication Hardware - Myrinet, http://www.myri.com/ - Giganet, http://www.giganet.com/ - Servernet II, http://www.compaq.com/ Cluster Management and Communication Software - LSF, http://www.platform.com/ - Codeine, http://www.gridware.net/ - Cluster CoNTroller, MPI, http://www.mpi-softtech.com/ - MPICH, http://www-unix.mcs.anl.gov/mpi/mpich/ - PVM, http://www.epm.ornl.gov/pvm/ Microsoft Cluster Info - Win2000, http://www.microsoft.com/windows2000/ - MSCS, http://www.microsoft.com/ntserver/ntserverenterprise/exec/overview/clustering.asp - UCSD CSAG # f 7 X f : Andrew Chien UIUC/NCSA 6, UCSD/SDSC UCSD CO#^-^ UT#, WAN a^7^^#@C0 #^CO^^%^^^am#^#^)^(Cluster Federation), fCOP^CO h FD V^com#, WAN ^CO - f ^ #3^ Hbl:Z D, ^ P u y ^ ^ 5 73 P71/#j^T 1G I/O ^ I/O a COM*&;i> P#^ Gigabit WAN U%, 3000km NCSA C0^7%^ k® I/O federation CO^#&fT - 186 - ddTrfJJiCG Pozo IS IT l'' 'b *~SciMark2 Benchmark j tz o SciMark2 CGJ\ • 5 ocD^##t#± —$11/ - fast Fourier transform - successive over-relaxation (SOR) - Monte Carlo integration - sparse matrix multiply - dense LU factorization k(Dda-(X dh&kL Java771/vk^LTaax&2flT^&Z:#X Recent SciMark2 Results http://math.nist.gov/scimark/ 51.6 MFlops IE VM 1.1.4 WinNT 4.0 Intel Pentium III 450MHz 47.7 MFlops IE VM 1.1 Win95, Mobile Pentium II PE 366MHz 45.8 MFlops NE VM 1.1.5 WinNT 4.0 Dell ... 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Globus Globus [7] [10] 14 University of Southern California - Information Sciences Institute(USC-ISI) fc ANLO/nyi]' liitF77 b 9 Globus "J —A*"J b l4j£ti6gt@©$$]k&S&l$-9- —e7$ig#t-4S 5. #-^147077 S L%©o %1B#I4, Globus -9 —t*7©±lcfggt£n/c MPI-G tl'-ofcMl'^Ai)-- t*7, 7>g(Ma->77"A6m' -tfl-iraissff&do Globus l4*©-9--U7&m# LTf^So C ft 5> © MOBA f, ©fflfflnJIgtt 61^14* S o ♦ «SM d gram sn»e.©ya7©jsx^ So o DUROC S»->'3 7©|Blliega. @atSt6SEtt1"So (co-allocation) ♦ mm □ Nexus active message S®, 7—j7tUS&ffofciSSIX V '7 b'@Wj© «si££Sl#tf So □ Globus I/O TCP, UDP, IP ZA-f- * -y 7 b tt £©fiJIS, SSL Lfc®mi*lS©6^'fb6'9'4: — b -f So ♦ SPi^T'f ;i/747-bx □ GASS 3cA%ai#7 y-fib7f-UXWE&mKfSo ♦ t+a'lft □ GSI 9 X -f y7f A0 ftfflf < ©It — fXA^fflfBSnSo ♦ 97bU □ MDS LDAP ^-7©|+**iiXV W b 9„ □ Gloperf AV b >7 —^]f«©iilse„ NWS © Globus ^©gtl^C 4 0 k&So □ NWS * v b9-f %#©#]&&47b?#lo ♦ □ hbm 7 7 >©####&«[#&f,#mfs##&m#o Globus ±(CSI$$nfcg$#0iW V-x;t-9--H7Ci4^IX.I4y.T©'fe©» sSSo MOBA A>& Globus if—U7£fiJM1-S|Sg©#if fctSo ♦ MPICH-G ANL (C 4 S MPI[11]©*#7&S MPICH & Globus 54oC Lfc*©» # < © Globus tt-£7 6180 S: MDS, GSI, GASS, GRAM, DUROC, Nexuso ♦ Nimrod/G Nimrod[12]l4 Monash University frUH^cf ttfeX^ yt—j7 -9" —Xffl©iftti:tbl+S 7 XfA« Nimrod/G[13]l4 Globus th—UXSrfiJfilTS Nimrodo Nimrod/G t" - 205 - □ mds mmumo □ Nexus JS&o Nimrod Resource Broker(NRB)©^SBb 0 □ GRAM NRB # £, © V 3 7"^Ao ♦ Ninf on Globus Ninf[14](i Remote Procedure Call(RPC) ^ — X © Global Computing '> 7 r A t fe o Ninf-on-Globus[15]{i Ninf © MM Dt "P Nexus \Z b # & OX £ o C. CD Globus Nexus CD Ninf D s MftXfotlU Nexus Tit:# < X Globus I/O £TiJfd t~ ^ ^ X fe 3 o d. MOBAon Globus MOB A H!k Globus #1 ©7%## G, MOBA on Globus © C#o ZZXlt^f Gregor J3; © IS) S#{£:IZiL^tzo ♦ MOBA ##6, {Sl/^l/th-C'X©^- □ MOBA ©T >X b —;V0 □ Place ©^SHJ □ St S S $1 © £* S (resource locating) O □ tlJffl#©I^SE(authenticataion) A: X V V Itbl(authorization) ♦ Globus## 6, MOBA □ GRAM ©tllfflfBHilS) D o Place ©^SIKo □ DUROC □ Nexus X^#o Globus I/O©## MOBA tcmL-C^a&A&o □ Globus I/O Q$C TCP & ck^#\ secure □ GSI ©^ftu:#d: GRAM&^##mf&o □ MDS □ NWS □ HBM ##lto □ GASS ##lto MOBA#^ Globus Gregor #it-lf ©tSlS'S^/c/cl't/'co o) ®fam&%MLX0ffim IE W S o T N Global Computing C:?jS'n f £ TX]) >T — 'y 3 >© *7 y X&M b ti -206- NCSA l8Uf4 Globus fili: bft (tft&ft £ ft t'fro [1] Grid Forum Home Page, http://www.gridforum.org/ . [2] A National Partnership for Advanced Computational Infrastructure, http://www.npaci.edu/ . [3] SCXY Conference Series, http://www.supercomp.org/ . [4] Computing Portals, hitp://ww.w 1.CQmpu_tLngp„ort„aly„.„Qr^/. [5] IETF Home Page, http://www.ietf.org/ . [6] Internet Society Web Site, http://www.isoc.org/ . [7] The Globus Project, http://www.globus.org/ . [8] Kazuyuki Shudo,Yoichi Muraoka, Noncooperative Migration of Execution Context in Java Virtual Machines, Proc. Of the First Annual Workshop on Java for High- Performance Computing, 1999. [9] ##-$,#W#-, Java CPSY98-32, pp. 39-46, 1998. [10] Ian Foster,Carl Kesselman, Globus: A Metacomputing Infrastructure Toolkit, Inti J. Supercomputer Applications, 11(2), pp. 115-128, 1997. [11] Message Passing Interface Forum, Document for a standard message-passing interface, 1994. [12] Abramson D.,Sosic R.,Giddy J. and Hall B., Nimrod: A Tool for Performing Parametised Simulations using Distributed Workstations, The 4th IEEE Symposium on High Performance Distributed Computing, 1995. [13] Abramson D.,Giddy J.,Foster I., and Kotler L., High Performance Parametric Modeling with Nimrod/G: Killer Application for the Global Grid?, to appear in proc. Of Inti Parallel and Distributed Procesing Symposium 2000, 2000. W, JSPP’97 mJtM, pp. 281-288, 1997. [i5]^##^ai3,^;n#^,mM#, > h - o-wi/:] >7"'>7ir A CD.bblk---Ninf,NetSolve,CORBA,Ninf-on-Globus O'fTtbfFffi---, tSIBM 99-HPC-77-34, pp. 197-202, 1999. -207- 2.3.1 ie5<4IBU-SCj3»5je«5-E3 yy fcMfrWL^i > b^-7 ^ Ui^o t)^,5Avx (l) /s—nytr^L —^ . r>-9->7> ^#J0/£ijj^fC3 >h°i— 7 ^ >^<7M y — -3 > bn.— £ & * y h V-^Trjg^U — ^ >ba—ft D b:i-7-f >7"bd; D >bn.-x'T Supercomputing ’99 b&UT C 3 -o £l0 7D i/x^ hf- Ali '^© HLRS (High Performance Computing Center Stuttgart) $: 41 ^> t ^r V 7 CD CSAR/MCC (Computer Services for Academic Research/ManchesterX 7 ^ V ^7 RUS/HLRS and Partners @ SC‘99 Portland Network Topology Cerfecs ► Toulouse EU Projects Optiblade TEN .. , ■-' ""T * > : «» " 155 . vBNS EQ 1 Y ARAN . Abilene 1 T 1 JANET S. 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"The Stanford Hydra Chip Multiprocessor"##^ (1999.11.22,24) OHP -215- University University to of Stanford Stanford easier blocks single chip composed of the localized slow fast speculation programs across and slow advantage architecture requires transistors especially 2000 and levels parallel to by taking are thread-level all plentiful bandwidth at by Architecture innovation control and latency relative wires develop plentiful of for <-> cheap, to low communication processors multiprocessor transistors implications simple slower are room easy parallelism law than cheap, fast it of cycle s renaming ’ get threads cross-chip communication Approach million are design implementation Long Plenty logic Exploits Makes Single achieve Moore Wires simple single-chip High 100 > > > > > > > > > Memory Multiple Keep of chip Wires Architectural A Transistors Hydra ■ ■ ■ ■ ■ ■ Technology ■ University University Stanford Stanford 1M Chip 100K Laboratory 10K Team Hydra (instructions) Parallelism University 1K Olukotun Size Hydra Systems Grain Kunle 100 The Stanford 10 Multiprocessor Program Stanford Computer " ' Loop The Thread Process Instruction 5 o 1 a! | Exploiting - 216 - ” better CMP a University better University thread Hydra for Hydra thread 96 buses ‘ 1.5-2x Stanford Stanford 30-50% and fine fine coarse Case cycles) single Interface write l : only & & i cache SS SS Hydra (10 LIOdaCadM Bus CPUS The and (64b (256b) ILP => processor ILP => ILP than comparable => “ ASPLOS TO is interprocessor T CmiHtawyCMhddr | C*5»| Bi ► # > > Bus ► read ----- 2nd-level , latency T 2 ; Write-through Read/Replace 5 Interface Low Shared communication Separate ' LltWiOaehe Memory CPU > >■ > | MwhuitaM lfMt.1 “ Main CPUaMdnqrCMrdhr Cache Memory LI T! : ArbNraton DRAM J |- 1 Rambus But Design 1 r CootroSw DeteCeehe L1 CanlraVlMf CPU Memeqf j caches 1 taetl caches CPU Cache i |Lt { I data Hydra J Cache Superscalar multiprocessor coherence primary f Cad* I «« processors “ 10 vs. On-cMpL* L CPUO maintain Base T “ Four Single-chip Separate Write-through CWSUMMyCoaMW- to Cadwj > >• > > Hydra The University University Stanford Stanford access) cycle cycle (~5 cache lines L2 performance time purposes caches 16-byte writethroughs array writethrough writeback most Details L1 for on-chip thread architecture for Data, performance support bus lines 2-cycle 8K bus design base access write Associative, Associative, read of 32-byte Architecture thread thread buses cycle single-ported Set Set speculative single-ported pipelined, KB, of Instruction, Hierarchy data prototype Hydra Single Fully 2-way 8K 4-way Line-wide 256 Word-wide sets ------ 4 Shared, Two > > > Performance Improving Base Hydra Speculative Speculative Conclusions Outline ■ ■ ■ ■ ■ ■ ■ Cache - 217 - University University very Stanford Stanford is I Loop early applications too expensive write: synchronization Parallelized from Forwarding and threads C-programs => occur of FORTRAN conservative difficult Speculatively reads disambiguation parallel too aggressive matrix is Requirements Software is be to dependencies limited help? when applications pointer dense is between for data analysis i Sequential compiler compiler Parallel data Loop auto-parallelization Iteration need time have disambiguation hardware violations the software Original Speculation can Pointer Remove Hand-parallelized Compile Allow Threads Auto-parallelized Forward Detect >- >- >- > > > >- How Parallel difficult Traditional O © ■ ■ ■ Problem: Data University University regard Stanford Stanford semantics without CMP writes speculative for for memory commits automated (e.g. writes sequential time correctness writes for support support performance bottleneck 40-60% a easily easily are perfect for parallelization t of the ’ threads code >95% original of sequential isn Performance now refills, ensures only is 0-7% cache for 10% refills, Speculation with follow L2 enables support arbitrary arbitrary low-overhead for miss to <10% structure parallelize within hardware ) into stores multiscalar ~35% to bus only Data System execution and provides code parallelization rate: accesses synchronization ways speculation speculation Hit Internal Occupancy: caches - - - data-dependencies Loads Loop Break Speculation Parallel subroutines Hydra Add Wisconsin Performance L1 Most > >- > > > > > > >- > > Data Data Other for Memory Solution: ■ ■ ■ - 218 - University University Stanford Stanford set III are by bits in CPU A-D) read #i+1 CPU later later Hi Speculative hit pulled The parallel L1 are in (priority memory O ---- line #i L1 byte a of CPU *1 Cache n: ” to L checked each Requirements are on CPU written views “ #i-1 CPU Speculative earlier buffers bytes encoders Reads write CPU ” newest © multiple and #i-2 priority CPU miss Head L2 “ The Nonspeculative L1 © Speculation D — Maintain Cache © Data Speculative University University ” M Stanford view Stanford “ Iterations II for Iteration © STATE Successful PERMANENT forwarding L2 after IteraUoni violation state backup smart state & Writes after threads Support provide Requirements speculative state control F7 buffers to retire pre-invalidation violations speculative bad write and with detect and retire bits bits reorder caches coprocessors discard tag tag L1 L1 Speculation L1 ” buffers ” Speculation Safely Correctly Read Dirty “ Separate “ Write Speculation © © © © © © Data Hydra - 219 - University University of a -02 for but on modeling the Stanford Stanford runtime applications architecture aspects 2.7.2 real all single-issue Support Support Hydra GCC processors 4 of system Accurate and interface hardware Entire Improving > > > > “ Applications dependency CP2 than and data 98 ‘ Speculation Parallel System threads implement from through to Data “ Thread speculation in ASPLOS to 99 ‘ ” threads recover simpler speculative ICS Speculatively ” Runtime all and of of overhead routines CMP description speculative Handlers order more flexible Multiprocessor Hydra Speculative Exception more Performance Chip Complete violations Adds the Control Track >- > > > » Software Performance Base Speculation ■ University University checks that Stanford Stanford hazard L2 the RAW into variables buffer L1 out cause thread & © write our CPU local ilidations iteration & L1 #i+1 CPU drains -gnffgr later Speculative any per our Pre-inv cache buffer speculatively Threads . - L1 te speculative #i pre-invalidate its write Wri thread CPU a dependencies invalidate Cache to just globalize # iterations CPUs writes translator procedure and CPUs ” & #i-1 CPU generate in CPU loop Speculative Earlier" Writes A Later after “ speculative Non-speculative body “ loop-carried Detection source O © © © loops procedures calls © CPU one Invalidations Speculative RAW to while code loop support pwhile #i-2 CPU mmm cause "Head" o Nonspeculative and Bus source Write Execute Procedure Pfor, Typically C Analyze could L2 for > > > > > > Cache > Speculative Speculative Compiler Speculative Creating ■ ■ ■ - 220 - University university ► RC32364 Stanford lost) Stanford code (IDT) work L2 source KB with 128 violations frequency, Technology and ------ values Transformations D (PCs, mm I, PC Device 11 occurring KB 8 thread write Code thread loads in statistics load-stores with in and Integrated frequently up down on and read violation tool 0.25gm loads stores in Prototype based dependent non-violating 2 Motion mm Synchronize Use Move Move Collects Correlates Find > > > > > > > Design 88 Feedback Synchronization Code > > Feedback Hydra ■ ■ ■ used University University transform Stanford Stanford of statistics performance manually hardware impact Base code Violation to ■ m and performance some Flashpoint) limit Performance help frequency latency (requires Performance locality memory can violations (MemSpy, data reduce for to statistics movement independence shared misses prediction Parallel Speculative data data communication threads Feedback Base dependence optimize optimize cache violation H ■ to to at at cycle violations coherent explicit explicit Look Frequent Dependence 100+ Need Look Need data support) No No - > > > > > > > > > 4-i 3 Speculative Cache 35- Optimizing Optimized -221 - University University Stanford Stanford Hubbert, all Maciek 2000 of Ben and 00 late ’ Chen, Lim by H1 models by out Mike Melvyn 99 ’ Verilog tape Map layout Siu, H2 and Hammond, by and Mike Road Lance Finish design . (IDT) synthesizable Prahbu, verification Lam, on Team circuit Design Kozyrczak Monica Manohar http://www-hydra.stanford.edu > URL Team Finish Complete Working components Hydra ■ ■ Chip ■ ■ ■ University University and Stanford Stanford for path with levels evaluation parallelism all compiler at microprocessors migration mechanism and applications controller applications on design performance speculative details parallelism to for controller for screening parallelism evaluation fine-grain reference Tasks optimization application interface way resources tuning for buses exploits all support performance memory new memory exception MR for code cache a large-grain parallelize coprocessor write mechanisms implementation high performance main L2 to Implementation platform to debugging performance system and out overhead offers and facilitate Read Speculative Speculative I/O Controllers On-chip Off-chip Statistics Provides Low medium to Realistic Single-chip Provide difficult Allows development Work v v > > v > v > > > >- > v » v Memory Speculative Hydra Prototype Implementation Conclusions ■ ■ ■ ■ - 222 - University University Stanford Stanford CMP a CMP in processors all large to Hydra implemented the in be architecture broadcast arbitrarily may implemented prototype be implemented be possible support Bandwidth be made buses memory are Hydra may simply be may the faster may CMP can buses of buses CMP? speculation CMP? writes a a techniques Hydra Pipelined, Multiple All Wider > > > > Bandwidth New Overview Why Thread The Why Outline ■ ■ ■ ■ University University Stanford Stanford the critical Latency t ’ from of memory from isn or more cycles) cycles) cycles) Cache Read (50 main L2 CMP Read (-5 100 communication parallelism #2 #2 than CPU CPU Laboratory Team (more University Olukotun Main MP cycles) Hydra Cache communication 10 Hydra Memory fine-grained L2 DRAM Systems interprocessor of Kunle Communication about multi-chip The #1 #1 Stanford faster CPU CPU (usually to minimizing more to Implementation more Cache Computer or memory cycles) Write or L2 (5 offers cycles) Conventional, Hydra Write exploitation • CMP? • (50 Stanford main a CMP The A Therefore, Allows Why - 223 - of to SM University University full the time an a prevent a CRA remainder remainder statistics at buses from to into , Stanford does Stanford handle * from take to write Devices caches ,cm i cache necessary also access through passed turned if I/O CPUS 1 access machine and (64b (256b) necessary w be arbitration stages ON**** sequence: Bi Bus arbitration s as H primary read ’ counters state access 2nd-level conditions Handles pipeline, Accesses SM SM memory Could Get Sequence - - - - - Each Control Each race address Write-through Read/Replace brtarface Separate Shared Separate > > > > State Memory Memory > >- > Main Memory rest chip to DRAM of Control Rambus Design . 1 Design rtumber rtumber CPU state Logic Output the caches fist in count to data FIFO cycles Hydra state multiprocessor coherence of up : LSCedw per State Buffer 1; Access Queues processors On-chlp Machine CPUO maintain Base Four Single-chip to Write-through Next- Arbiter Central > >- >- Resource State The University University Stanford Stanford lines less reads writes of transfers on on sequence processors allow errors and access access L2 unit ownership system the interface well bus bandwidth controllers possible cache-to-cache to memory memory controller: do acquire work high data to to off-chip main main memory still and memory interface: Coherence to execution protocols hard-to-find have have memory start start drive return the t t ’ ’ time for to to to to machine machine design don don faster memory in protocols Controllers state state through design coherence independent CMP? processor machine machine machine machine potential easier communication main read write a result Processors Processors Fast Less Shorter efficient L2 L2 State State State State each the >- > > > > v > > v > > Faster, Can Simpler In In Several accesses Memory Why ■ a ■ ■ ■ ■ - 224 - University University s ’ its ” Stanford clear Stanford clear it is early will program as accesses older each need? reserve too performed “ up threads all matches bits for violations vector is of vector bit ... multiple original occur must bit after match queued its L2 those immediately 12 system the the cache indicating access memory memory its to when are Arbiter in reads speculative the state L2 of the clear bits when ” simultaneously done in in the clears be Requirements set write are in writes when memory address address views will all “ memory conditions its between with an it bad misses misses access to main of Address missed processed race when the a data that is that same address same vector each — violations multiple of that speculative bit thread of the a while of accesses does to competition, prevents access access access Speculation discarding no Central Parallel-compares If miss Saves accesses Otherwise, completes This Later > > > > > > Every Each Each address Forwarding Detection Retiring Maintaining Safe order executing Data ■ m ■ ■What The O 0 © © © University University Stanford Stanford system try to the tracking easier in threads re-execute automatic requests & parallel R/W interface CPUs) in resources bus writes full send hardware all writes) grants do reads automatic correctness of support becomes write t among Arbiter to ’ fine-grained shared memory own allows more? the access of isn dependencies before parallelization segments track code its an cycles real use with still generates main keep memory hardware reads track acquire support start find makes even can program add then maintain make to parallelization to to (priority can (usually Resource do can prioritized this broadcast CPU table allocates must necessary need memory by type ... tracking therefore therefore are speculative are support, processor processors processors sequential that ROM by parallelization also uses can R/W when add CMP this cycle First SMs Second SM Each Other Do writes We communication small CRA a Central ------ Requests Programmers A All Programmer Speculative running All With > > > >- > > > > Each Every Fast buffers, However Hence The ■ The * ■ ■ Can ■ ■ - 225 - University University Bus Only Mask byte) Clear and Clear (by Stanford Write Stanford Write Invalidation from Commit Gang (he) in Force on Bus backups commits Data Data cache Read (L2 Write on on to advance and Only out bits backups Clear ICAM] L2T«g Data and Invalidation clear clear Addresses of array Backup V violations Read Gang on to to and Force renaming the detection after bits bits types commit in up to until commits valid memory valid us are extra back violation on 4 here to line required Details buffers cause cause Allow pointer Allow bits priority ” us Allow held complete on each line are tail all bits bits cache ler are *** Clear of for earlier L2 e Tag requires “ when Details present with muxing Allow cache if L2 Gang mask by and from writes byte-by-byte from clear array circuits tricky into modified pre-inval tag write time read data are Read-by-word: Pre-invalidation: Modified: Set Set Gang Written-by-word: Buffer Cache Drains Requires Line Collected Byte Any substituted, encoding > > > > > > > CAM Special Speculation ------Speculative commit ■ 12 L1 > > Reads University University ” to view Stanford Stanford 't SM “ 1 1 for : thread Icpzj i ‘ small Sw:, threads UDMCMwl SpwwkrtkH. Pd (64b) .0 ' <»• ' Bys ^ buffers: with forwarding complete 1 1 | L2 reads the &** ™*- i IcPZj 1 speculative C«h*A A completed Write-through state smart backup ■ buffers „ U & | restart threads per of buffer * " A UM::* from ^ : threads i provide Support > forwarding manages ' , 1 ; ' when speculative order ■» CP2 included 1 threads control j control L2 buffers i buffers to i retire * pre-invalidation provide violations to be to UOwNCwlw* Spee»l*tXt»D*» of I maintained write and when * with is detect background and controller buffers may 'S'"* sequencing jvC#D ' L2 bits buffers Overview bits reorder the sr caches CM coprocessors 1 draining buffers tag and in tag L1 buffer sequencing t buffer L1 Speculation 3pM»OT*ol»b- L1 ” buffers bus buffers ! ” ■V>. - L2 ■ C occur Clears Maintains Uses Allows Commits Dirty Read Separate Speculation “ “ Write Write Buffer > > > > > Extra One Simple 0 0 o e & ■ ■ ■ Hydra L2 - 226 - University University Stanford Stanford needed changes is tone 7 2 12 - - 12 -30 OS -22 address + processors Loop-only Omhid 17 end bits tine handler sequence 15 -70 -70 OS other -no Hs sequencing special + threads OwM 25 Procedure a tag of if this on CPU that to starts snd and track Mice by loop execute from routines: the present) cache and iter buffers if Ae thread procedure SYSCALL on execution a execution a to on end loop speculative iteration, iteration, this code, procedure registers thread task cache primary a software starts thread, non-speculative. committed less next of cache loop loop a for at speculatively the processor then the speculative following following a requires out to is Vee writes speculative Summary processing it when snd completion secondary violation current current speculative runs procedure code thread major if tone L1 or head" its cerent stops down system the the until ... processing " the off processor processor coming bits RAW bits the the a another off iterations, shuts the processor, processor of attempts machine speculative forked control of this control then the the loop Forks loop Completes Completes Restarts ■utiuctioB, Completes then Temporarily (or Prepares running has Handles Pauses simply CPU a Coprocessor of thread Full running loop T Local from ” Loop speculative state are each Exception Procedure Buffer Procedure of the stop SunL the together Finish Receive End new Start Vioimkm: Hold: End Hold: System clearing the a or to some all operation commands examples: small “ it ~i a Procedures L *W<»* speculation Restart Start Start are - - - Has Initiates Commands Some > > > > Interrupts Holds Maintains Here Controls Catches Putting Speculative Runtime ■ ■ ■ ■ ■ KB 2 University University a for but on the Stanford Stanford Lines violations KB processors Support Cache 1 B hardware 64 Improving “ Applications other than to structures and dependency 98 ‘ Speculation System Parallel KB implement 0 from memory to Data commands “ speculation in ASPLOS to 99 ‘ ” threads Sizing recover simpler to ICS Speculatively speculation Runtime ” write-based writes and of coprocessor size overhead are line routines CMP description thread fully full in caches the Buffer most a speculative Handlers managing sending per more L1 flexible Multiprocessor when Hydra By Using By buffers used of KB - - - 1 Exception Control more Performance Complete Chip Adds the Data buffers buffer < captures Stall We associative pair > > > > Software > > > Small sufficient comparable a All L2 Speculation ■ ■ * - 227 - University University and bits Stanford Stanford avoid ... Hydra to logic of tuning evaluation ... including speculation code merging necessary version macros L1 for as mechanism here buses controller read controller for including cores cache performance write functional implementation pipelined for and required coprocessor, cache information screening memory reference be and existing system, fully interface structures resources invalidation of core fan-out CPUs will arbiter main buses all yet read Challenges rate the rate operation high gang memory interrupt feedback for bits cache CPU Overview of secondary write mechanisms memory speculative long system L2 small memory debugging clock off-chip cycle clock a with clear resource and for fan-in, our our and generate MHz Design Memory Single slowdown Conditional Read Gang Simple Target Controllers I/O Speculative Statistics On-chip Speculative to High > > > > > > > > > > > > > > Drivers Speculative Clearable Central Building Starting Adding Adding 250 Key Prototype ■ ■ ■ ■ ■ University university -► RC32364 out hazard, Stanford Stanford X to X by KILL data sends restart (IDT) handler the VIOLATION the address address message L2 the speculative respond CPUs handler - 3 KILL notices notices reads writes KB 1 1 a more processors executing handler starts The They All 0 exception 128 ***** Technology access and D bus C«w#wuc«b Hazard Device ______i \ 11 write IcigwAfl* ***** a KB Floorplan — [ NMI 8 | ******* mi indicate Data :■ with ****** Integrated a Lines CM) OwtM* - \ on I of 0.25p.m * in based Prototype '**£$!* 2 mm ■< Design 88 > > Hydra Anatomy - 228 - University University of Stanford Stanford purposes between make efficiently easy can evaluation memory workstation memory balance fine-grained statistics memory execution host for easier implementation resources main main relatively relatively a further main makes software is effective to into speculation CMP from program allow allocate internals off-chip like performance latency offers automatic will hardware chip and interface results programs during large speculative parallelization to of of I/O nearly to I/O reasonable structure and techniques I/O mechanisms a make prototype for possible speculative interface interface loading reading simple complexity communication can parallel interface offers Hydra hardware Allows Allows Lower Allows Allows Bus-and-SM Support parallelization design Arbitration threads Adding CMP >- > > > > > > > > Direct Simple Hydra A our The Prototype Conclusions ■ ■ ■ ■ ■ University University Stanford Stanford tuning 2000 all code of of for circuitry end coprocessors by HTOO models by monitors out 1999 violations system of on times Verilog tape Map layout speculative monitors end machines Mechanisms in and memory reference by and feedback state arbiter debugging utilization Road timers in Finish for design . through memory synthesizable provide verification on idle-arbitrating-busy resource resource circuit counters chains Design monitors Track Track Primarily > >- > Bus Programmable State Scan Central Speculative Finish Working Complete components Statistics/Debug ■ ■ ■ ■ ■ ■ Chip ■ ■ ■ - 229 - University University but Stanford Stanford violations loops processors hardware ... other parallel than to structures threads CPUs dependency dependency System system the implement from sequence in memory to commands speculation speculatively Java parallelizer to speculative caches threads in recover C into simpler simpler properly L2 for management speculation caches Runtime collector to to concepts write-based and L1 coprocessors coprocessor loops overhead routines threads in thread the speculative added automatic Handlers support code managing garbage system sending bits more flexible together together By Using By user the - - - In Dynamic Basic In Extra Buffers Exception automatically Speculation Transforms Control more Adds > > > > > > > > > > > Speculative Hydracat Software Hardware Software Works Speculation Outline ■ ■ ■ ■ ■ ■ University University while code easier Stanford Stanford dependencies parallel the management data in parallelism data conservative for CMP Hydra of post-subroutine for programming easier parallelization enforces parallel program Laboratory semantics a in with on Team of much simplifies make instead system parallel University Olukotun Hydra parallel program Hydra iterations Systems Support in runtime locks opportunities sections threads Kunle optimistic The for loop Stanford be parallelization communication sequential conventional execute can expands parallel to Computer multiple subroutines Programming manual supported Stanford latency run run allows Hardware-software Software - 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() variable out hazard, Stanford Stanford used location to X X function i*l; ,..)i * by ( KILL Xi data counter » y = sends yt restart loop W) * y handler the VIOLATION the 2S| Loop variables < address original address dependencies message f l* «** s // t //Loop-carried the •I** ’ speculative respond CPUs * handler (Hi U () 3 « KILL reads notices writes if spec_end_of_iter»tion X it tool*er_BigJunctiontl HOr»_Cod«_B«r separate loop 1 1 processors handler a more executing All 0 starts exception The They processors data all the TtiisLoop New, to In true Loops ThistoopUi void I: hardware: broadcast when write a Dependencies invoked indicate loop is code speculative in Lines the code itself Data locally Conversion by variable system function x, used Siwj , loop control , ti encapsulation i CPUs own ( counter i*i; the all its =, x? loop Loop, Variables Loop-carried y in * i++* runtime on / body detected // // loop / variables y 25} speculative 90; loop !* oop « loop else are I FOR The i <1 Add Put * > Hydracat Enforcing if X Another_Bifl_Funcfelon — — Program Start Speculative The The i, Transform 1. int University University ” that body only Stanford Stanford 7 7 -22 Improved Overhead “ ... loop loop code system single loops tedious equivalent ” purposes a by the the is II Quick subroutine in converted required “ on just special register-allocated ; t ’ be ” own not loops pwhile simplified 80 with ~ to Slow programs a its system “ aren returns speculative code automated performance Loops and s ’ need into the and uses processors marked shuts be loop for this attempts processor, processor procedure to parallel user values then for then all this this that execute pfor and subroutine, requires to on by then loop and can body) execution speculative a the speculative loop speculation management locals, thread on are start (or starts iteration, processor present) iteration, committed loops loops if speculatively Use into then loop loop added develop into continues, to to loop iteration and to loop pure speculative processing thread, to management violation thread current speculative ” (or system loop converts current process original of loop-carried p down the less the current the “ code RAW next made a iterations, Overview a loops the the a loop easy subroutine breaks, the is Software loop the when tool that overhead run Prepares ” it Completes localize to Handles Completes Restarts all add setup the portions to subroutine loop CPU loop initial Local Receive Loop Loop Minimal No Key Ensure each Makes Add Convert Convert Try Just Pull another of iteration Routine Start - - - Finish Improved > > > > > > > > Violation: Entire End “ However, disables Converting Our from Violation: > > Hydracat Support ■ ■ ■ - 232 - University University up t x: Stanford Stanford +■ ; be i*i; loc*l_*W value * violations t speed parallel y, lot! locals# x, local_sum) * a r even maintained , frequently not critical i fi ( parallelism looal^ann information * i*i; case parallelization the = are help can (...); hidden y necessary (nonlocals*>wum) that may most * 25) dependency failure can be (oanltxsala-xetaR) so != application A_Big_Function of i value common violation calculating track (nonlocalB->si*R) occur local_auaa Anotbaar^BigJPunction More_Code_Here the Prediction may semantics semantics A automatic movement artificially with the of r written information critical is chance value Rare is the parallelism Case a Fixup lative Move code runs for of provides monitors make s involved ’ tuning allows improvements to code Value ); *->«»)); sequential y; there + loop-carried dependencies without algorithm optimization calculation quick support untuned nonlocal Optimization ( occasionally always the true y, with with when critical attempts speculation, in a code x, (nonlocale->sum) because record first, sequential , small, , i to ( i performance ( is i*i; * where Hardware/software and is writes involved = few (...); - y Fix not Often, present Speculation during that that A This 25) performed Prediction Thanks > > > > > != Hence However Speculation A_Big_Function Code Code Code > > (i Feedback ■ ■ ■ Optimization: if x* More_Code_Here AnotherJBig_Punction University University ; ; StfUCt Locals StfUCt ; ; )); ) Induction Stanford sum PdCk Optimization Loop-carried loop -> s UfipBCk Transformation i 1 in tnonloeels->«M*n variable local_au»> tl closer the ; « y, y. . «t, iOttloeal»->*UB> variables locally nonloca x, loop location counter , ( function ■ variable 1 < ndnloeals->suN) of ( , used ; Ci, l i loop-carried loop 0 ( ( ■* local.eum p ; ; *nonlocale) loop ..,); . copy +* i*i; • ) counter %:' subi sun original . i = variable 0: = s ’ increase increase y * Nonlocal Nonlocal Loop-carried Local (nonlocals->*um) Loop loop-carried Variable* sum i ' , . U ft II // * // Au.Bia_Functi Variables separate 25) ( loop thieLoopVars ; ( with » thieLoppNonlocals; != (nohlocals-?: (nonlocals->su«i x Another_Sigjhmeeion Nor*_CodejH*re( the i; A_Big_Function sub 0; New, (i struct = value In II: y; int int thisLoopNonlocals nonlocala->su») Struct IhieLoop ( greatly if local_»ua i: - Amather^BiflJFiwcfcion More_Code_Here x, sub thisLoopVare; ) typed*! thisLoopVar# thlsLoopNonlocals Movement int int int thieLoopNonlocals sun void tfci»Lo«s>(6t&i*L6opllonlocal»t : critical loop-carried can value a the of ) to body registers parallelism compilers of Code ); code y; write SGI ♦ loop-carried out loop a for calculation ndnlocal»->euni> ( -**«*) the work Conversion with critical y, transformations of available a variables (nonlocals->sura) x, transformation CPUs , of i moving nonlocal# itself < ( all top loop variable * writes on body Involved = loop variables transformations y the oop not loop that I FOR loop-carried 25) Simply amount to These != Program Start Speculative The Speculative The A_Big_Function(i, — Code Code (i > Force = Hydracat (nonlocal»**>stmt) Optimization: if x Another More_Code_Here 2. ■ - 233 - no used University University Class with and transform RTS Stanford Stanford statistics dynamic intervention performance C compiler, manually manual Base Optimized code to Violation JIT multiprocessing fine-grained ■ # ■ facilitate with for GC, from (e.g. Java suited compiler benefit for JIT well required can environment and model Ideal and speculation multiprocessing implementation Performance routines routines is of thread environment these Java support of machine specification Hydra Native Runtime Many loading/verification) Most management coarse-grained > > > > Virtual Java 4-, Programs Speculation Why ■ ■ is University University that until C ): loops, waits structure Stanford Stanford normal )); >aum) that * overheads code with continuing routine frequent like most its synced optimizations with "nonlocals" {nonlocals before the , easy performance be i i in ; ( just i to with { dependencies parallel i i*i; helpful is be direct « X; protect equal {...); variable with = a(nonlocals->sum_lock y assembly-language high be >eum_loek) y amortize new w to an a 25) along should is Hydracat minor can is help becomes 0, to helpful else =» to can (i to « be used used (ncm,locals spec_lock(i, x if with Another_Big_Function More_Code_Here form sum_lock spec_lock sum_lock ' initiated ^ conventional conventional protect achieve be can in enough programming to Speculation can can feedback dependencies speculation large programming ; ; ) Synchronization parallel dependencies continue the from low-overhead parallelization code speculation provide for can critical y? its local_sum) ♦ routines ; synchronization y, programming in parallelism parallel code can it x, to (nonlocals->#t»t) of , most , i { synchronization i ( locel_etaa iteration automatic i*i; «: speculation, the * x; protect (...}; unpredictable synchronization = y section (nonlocsl$">etm) Similar variable to y Speculation ” * 25) - - Loop Post-subroutine-call predictable Fully sequential especially With Explicit Only and Hardware =» •else A„Big_Functioo sum >- > > > > Explicit Critical “ added (i Speculative > > Speculative = {r»5»iiocals->s«ml if x Another_Big_Function More_Code_Here Optimization: Conclusions ... □ □ ■ ■ - 234 - University University / for Stanford Stanford stack code required by as during from C disables profiling / invoke in speculative detail (LOD) compiled Java passed to JIT vs. dynamically accesses of code code enables Methods compilation identifies top heap controlled registers Under at speculation overhead flag system level-of-detail annotations techniques assembly Java space dynamic separate code minimize access of runtime dynamically on profile code dynamically inserts can annotation procedural considerations Profiling the performance clearly sampling of methods code to to method speculation assembly system remove accesses change utilize adjust / reserved compiler compiler advantage rewriting Use profile Can local Can Can method Unused methods speculation Add Bytecodes JIT JIT > > > > > » > > > Implementation Runtime speculative Take Advantages Analogous Java-specific ■ Speculating ■ ■ ■ Advanced ■ ■ University University ) Stanford Stanford run to platform call penalty any control, code Java version on ISA method in source-to-classfile process source only or performance MIPS g. d) choses ’ implemented or no (e required bytecodes for executable for call (GPL hand, http://www.transvirtual.com translator ( body class-private speculation by primitives common support compiler allocation normally normally Environment dynamically into for loop licensed method additions handlers loop Speculation done (JIT) of for machine compliant transformation inlined register compiler SwingSet body libraries public / 1.1 normal easily be system specific body Hydra Loop be code source-to-source loop Multiprocessing synchronization) Global Optimization AWT virtual JDK Can - Speculation versions ------Hydra Support General Just-in-time bytecode Default Loop Can Via > > > > > > > > Kaffe Move Some Runtime Two Using * Java ■ ■ ■ ■ - 235 - source University University source object speedup hand- 38x Stanford Stanford stack 1.98x 1 garbage gray completes Hand-picked methods => => speculative Unmodified optimized With be objects roots speedup occupancy > > » ■ □ as runtime must sweep objects; objects classes points-to from after gray marked white Speculation all or default objects or to heap; pointers marks black white black heap explicitly to all Collection to pointers live object Method sweep left, - - unmarked of objects points points or - after stack loader base from objects heap; Sweep heap; black as garbage live class gray live thread model - - references - no and acts Default Black Native Root becomes Gray White and > > > > > > Roots Tri-color Mark Speedups ■ ■ in University University sweep Stanford Stanford critical objects with be and live regions from longer mark speedup call Profiling optimizations no to frequencies identify / benefit programs and can method C with Collection statistics or speculative may as speculation incremental accuracy which of that is speculation bodies addresses dynamically disable profiling / transformations loop loop can objects of execution prediction sections from performance optimizations Garbage violation of based and enable of free effectiveness Speculation value cycles system critical in results and collection implementation sorts detailed Return Frequency Size Speculative - - - - procedure heap Dynamically Determine Programmer runtime Same Identify speculation >- > > > > Collect Applying referenced Use Baseline Garbage sections the Speculative Optimize ■ ■ ■ ■ ■ - 236 - University a University each calling size from Stanford modify Stanford with barriers bytes 300 that examined object object 200 list write speculative < than we by barrier as gray white violations with list collection a more invariant aastore) the bytecodes sorted to write arrays no at gray on method short-lived, on Barriers computed lists thread but applications expected onto putfield, pointer pre no Collector free barrier a head calling objects most incremental long-lived black/white are sweep off in of as accomplished objects, of common, good object Write write for write and speculation to sizes required, (putstatic, usually most 10-25 on white barrier objects number - - maintains results inserts barrier mark value collection object least Garbage sizes continuation write these attempts some at requirements trapped objects write objects object; references all procedural return compiler of allocation object Place Sweep Execute Execute No method Sweep thread Within black Large heap Non-array Allocate JIT Trap Small > > > > > > > > >- > > > > Role Using Experimental Fast Incremental Non-copying Two Baseline Speculating ■ ■ ■ ■ ■ ■ ■ University University Stanford Stanford Non-spec Non-spec Non-spec Non-spec Non-spec spec Implementation(s) spec, spec, spec, spec, spec, Parallel Procedure Loop Loop Loop Loop Loop references root Collection stack GC finalize thread needed again thread to Collection if invoke list list objects native objects objects Function Program object limit, objects gray gray Finalizer barrier at root root Garbage white Resume Mark Heap Mark Invoke Identify Free Write Sweep Finalize Sweep Sweep loader class and GC GC GC GC GC GC GC GC Thread default Program Program Flnallzer Mark Parallelizing - 237 - in University and University and spent speedsup JIT speedups code speedup loops larger time Stanford Stanford as on sections have critical when based relative Calculated in GC application Collector impact improves compiled will identifying Only * ■ wait like variables idle in implementation non-issue GC a in 1% 0% 0% 7% 7% 3% 7% 5% 6% 2% shared 16% 12% 16% 10% 27% iterations 20% is debugging time debug on Speedups % resulting 9.5 9.2 and 17.4 16.5 58.3 58.2 33.5 70.2 79.4 40.4 62.3 89.3 135.2 122.1 2837 295.2 time between speculative (ms) Parallelization model, to Elapsed correctness design loops performance to is 1.00 1.11 1.05 1.04 1.21 1.12 1.12 1.04 Overall balanced since synchronization loops similar iterative Collection not work GC to 3.41 3.12 2.27 2.66 2.28 3.78 2.53 2.84 Speedup difficult is have of orig opt orig opt orig orig opt orig orig opt orig opt orig opt opt opt Bound Bulk Must More violations, work Traditional > > > > Set Non-speculative Speculative Structurally Garbage ■ ■ vs. ■ Benchmark mtrt Swing compress db jack javac jess jBYTEmark University University 2.20 2.61 2.11 - Stanford Speedup Stanford from 2.22, 2.41,2.61 2.41, 2.09, 3.41,3.11 Loops between speculative benefit per speculative linked-list can iteration Non-spec Non-spec Non-spec Non-spec Non-spec iterations spec Implementation dependencies per each Collector spec, spec, spec, spec, spec, Collection loop which for Parallel Procedure Loop Loop Loop Loop Loop elements accessing loops for between overheads GC Critical finalize thread needed again linked-lists to non-essential if linked-list Garbage invoke list list on collector objects objects in Function Program balancing object limit, objects gray gray gray Finalizer dependency speculative at root root multiple four load multiple eliminate Resume Mark Heap Mark Invoke Finalize Identify Sweep Sweep to Eliminate iterations Better iteration Maintain Amortize > > > > GC GC GC GC GC Process Identified Need iteration speculation Thread Program Rnalizer Program Speculating Speedups ■ ■ ■ lilSBfli IlliilgmgM 238 - University Stanford JIT GC, VM: high! into speculation and method processors system verification concurrently utilization and speculation match / profiling and Java loops runtime threads good available optimization loader of a for processor to Java Java managed parallelism on based class keep Hydra work to multiple advantage is with Dynamically Run Feedback Incorporate compiler, Speculate > > >- > > Distribute Goal Java Take Conclusions ■ ■ ■ ■ - 239 - m IS 03-3987-9354 FAX 03-3981-1536 /l —3 ? •ri'yp ^©iSSW^E 16 fi ¥1® 1 2 ^ 3 H =7=105-0011 ESSSKS&E3-5-8 * IS 03-3432-9390 FAX 03-3431-4324?7;VT-7 V y f 7 V 5 7 -f 7&#->@#§©3 >711 75 vt3 Lfetfo T£/J'£ < */A£A-2>o Cffl^SI4ti£*©X7 7 V^TX Mctt^T*S1i*X7 7 4 & r the Alliance 7*D id5 x7Fj, © 7 3©±g&##. doJO'T'Di/z^ F£*fSik L£o iS*©iSS. 4-JPiWl4fElt*iti:ri7 7d'A77 F&iBC LT*b. -rt-tc Grid Forum kPflifl-S Grid US®/cto® IETF(Internet Engineering Task ForcejlC jgo As Md&©®J£doir>'«|g©*d|i • SftS;J;*&lfoTU5cil)S|iJlibfe. $£. -f >77tFttt3;ET-( f-f Fife 7 7 7 7 £. iS&#Wl&%* 7 F y-y-n^Hb. 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