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Retrobrew Computers Forum a Z80 Subject: 8086 maximum mode SBC Posted by lynchaj on Sun, 30 Apr 2017 18:03:00 GMT View Forum Message <> Reply to Message Hi I've been mulling over an 8086 maximum mode SBC based on the Intel datasheet. It is simple computer with just CPU, RAM, ROM, & DUART. No PIC, PIT, DMA, and no wait state generator. Take a look at the schematic and tell me what you think. The PCB is fairly small & 2 layer 5.525" x 4.700" which I am guessing would be fairly inexpensive to build. All the parts a PTH so easy construction. Note1: I noticed there was a problem with the memory decoder so I fixed it and updated the schematic. Also included the memory decode truth table and the PCB layout file. Note2:Argh! I thought about the IO decoder some more and realized if I made some minor changes I could use left over gates and eliminate the second 74LS688 so I updated the schematic and PCB layout (again). Subject: Re: 8086 maximum mode SBC Posted by lynchaj on Mon, 01 May 2017 11:42:56 GMT View Forum Message <> Reply to Message Hi The 8086 maximum mode SBC is in no way intended to be IBM PC compatible. In fact, just the opposite. I'd like it to be a clean sheet design without any of the limitations of the IBM PC heritage design. So far, it is an 8086 CPU with 1MB SRAM, 256KB Flash ROM, a DUART which provides two UARTs and a parallel printer port. Also added a general purpose output latch (used to swap the 256KB Flash ROM in/out of memory after booting) and an IDE port (which is practically free on 16 bit x86 computers). Is anyone interested in collaborating on said project? I am considering building this one myself since I never seem to get to do that anymore. Subject: Re: 8086 maximum mode SBC Posted by jcoffman on Mon, 01 May 2017 15:07:02 GMT View Forum Message <> Reply to Message Andrew, Before the NS32202 was put on the MF/PIC board, I did a series of experiments with the NEC 8289A. Perhaps it is easy to interface it to 80x86 systems, but I was unable to get it to work with Page 1 of 31 ---- Generated from RetroBrew Computers Forum a Z80. Part of the problem was the 8289 data sheet -- clear as mud. Note that the 8086, in taking an interrupt, must read the 8289 twice. This seems to me to be a very odd requirement, and may have been part of the reason I could not use the 8289 on a Z80. I was looking at the 8289 because I felt it was easier to source than the NS32202 chip, and the latter worked fine on Z80, NS32000, and later on Motorola 68000's. By buying the '202 in bulk and providing it with the board, the chip sourcing problem was solved. =============================================== BTW: if we can get the VGA3 board to work satisfactorily, I've considered a re-spin of the SBC-188, mainly to add full memory (2 x 512K chips). The board is known to run as it is at 25mhz, but needs to be slowed to 16mhz to access off-board 4MEM. A re-spin needs to address the wait-state problem with off-board accesses. =============================================== RE: pure 8086 & software The SBC-188 was intended to be a non-MSDOS computer entirely. However, the lesson learned is that one wants to run available s/w, and MSDOS is the most available. The earliest revision of the SBC-188 (timer fix), made it a little more like a PC. There are several other things to be done to make it even more like a PC, and these would be incorporated into any re-spin. However, the '188 will NEVER be a total PC-clone. An 8086 could be. Plan on running MSDOS. ============================================================ === For running Linux on a home-built PC, have you looked at Mark Williams' COHERENT. It will run on a 386, with relatively little memory. It is more a clone of System V, since it pre-dates Linux' wide acceptance. It is now open source. --John Subject: Re: 8086 maximum mode SBC Posted by lynchaj on Mon, 01 May 2017 15:42:08 GMT View Forum Message <> Reply to Message Hi John, did you mean 8259A (programmable interrupt controller) instead of 8289A? The 8289A is a bus arbiter for Multibus although it looks like an interesting addition to the SBC. For instance, it provides AEN# which is useful for an expansion bus. The current 8086 SBC does not support expansion bus of any kind. Everything is CPU local bus for now. Page 2 of 31 ---- Generated from RetroBrew Computers Forum Frankly, I would like to get away from the IBM PC standard for how it implemented its on-the-mainboard peripherals. Its practically a war-crime. I think the PIC and PIT could be used to much greater potential. For instance, I think the PIC could support a *lot* more interrupts with a slightly different configuration and an adjusted interrupt service routine (see the other thread on 8259A PIC in General Discussion). Similarly with the PIT, however the PIC has to be working before the PIT can be used so the CPU can utilize the PIT interrupts. Subject: Re: 8086 maximum mode SBC Posted by lynchaj on Mon, 01 May 2017 16:00:07 GMT View Forum Message <> Reply to Message Hi John Would you be interested in a re-design of the SBC-188 to incorporate an 8086, PIC, PIT, and DMA? It is probably too big to put on a 160x100mm Euro board but it might fit on a double stack board (like the uPD7220). If we were to go down that road though, I would like to implement the PIC (and the PIT) differently than the IBM PC did. I think the PIC could support 256 different interrupts with level detection vs. edge detection along with a different interrupt service routine. Also the PIT could have three separate interrupts (one for each timer channel). With 256 interrupts we could assign them with abandon rather than hoard them like you have to do with the current IBM PC/ISA architecture. Every device could have its own unique interrupt or even more than one if needed for separate modes, etc. I am thinking the PIC would receive multiple interrupts at once, read them as levels, update its internal registers, and call the CPU via the INTR line. Then the CPU passes the INTA line back to the PIC and reads the internal PIC registers to assess which interrupt was called (status of IRR) then clears the PIC. The CPU would handle the rest via its interrupt service routine. Does that make sense? It's a theory I've held for a long time but never had a chance to experiment with. Thanks, Andrew Lynch PS, the 8259A datasheet says the PIC supports level detection and multiple interrupt requests. From the datasheet: The events occur as follows in an 8086 system: 1. One or more of the INTERRUPT REQUEST lines (IR7±0) are raised high, setting the corresponding IRR bit(s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive the Data Bus during this cycle. 5. The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases an 8-bit pointer onto the Data Bus where it is read by the CPU. 6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. Page 3 of 31 ---- Generated from RetroBrew Computers Forum Subject: Re: 8086 maximum mode SBC Posted by jcoffman on Mon, 01 May 2017 16:01:03 GMT View Forum Message <> Reply to Message Yes, I totally mean the Interrupt Controller, 8259A (not 8289). You can argue that the IBM-PC architecture has its flaws, but there is too much s/w written for it to ignore. I found the Intel PIC architecture to be a bit odd. I think it was meant to work originally with the 8085, and was never updated to a newer version for the 8086. --John Subject: Re: 8086 maximum mode SBC Posted by lynchaj on Mon, 01 May 2017 16:10:39 GMT View Forum Message <> Reply to Message jcoffman wrote on Mon, 01 May 2017 12:01Yes, I totally mean the Interrupt Controller, 8259A (not 8289). You can argue that the IBM-PC architecture has its flaws, but there is too much s/w written for it to ignore. I found the Intel PIC architecture to be a bit odd. I think it was meant to work originally with the 8085, and was never updated to a newer version for the 8086. --John Hi John, According to the 8259A datasheet there is both an MCS-80/85 and an 8086 mode in the PIC. They are different but very similar. What IBM did with the PIC and PIT (and even more ghastly MDA and CGA boards) are crimes against nature and it doesn't have to be that way. Unfortunately the software written for the IBM PC had to be written "on the metal" as to extract out every last bit of performance.
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