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NAND Flash Controller 13 2014.08.18 NAND Flash Controller 13 2014.08.18 a10_54010 Subscribe Send Feedback The hard processor system (HPS) provides a NAND flash controller to interface with external NAND flash memory in Altera® system-on-a-chip (SoC) FPGA systems. You can use external flash memory to store a processor boot image, software, or as extra storage capacity for large applications or user data. The HPS NAND flash controller is based on the Cadence® Design IP® NAND Flash Memory Controller. NAND Flash Controller Features The NAND flash controller provides the following functionality and features: • Supports one x8 or x16 NAND flash device Note: The HPS supports booting only from a x8 NAND flash device. • Supports Open NAND Flash Interface (ONFI) 1.0 • Supports NAND flash memories from Hynix, Samsung, Toshiba, Micron, and STMicroelectronics • Supports programmable 512 byte (4-, 8-, or 16-bit correction) or 1024 byte (24-bit correction) error correction code (ECC) sector size • Supports pipeline read-ahead and write commands for enhanced read/write throughput • Supports devices with 32, 64, 128, 256, 384, or 512 pages per block • Supports multiplane devices • Supports page sizes of 512 bytes, 2 kilobytes (KB), 4 KB, or 8 KB • Supports single-level cell (SLC) and multi-level cell (MLC) devices with programmable correction capabilities • Provides internal direct memory access (DMA) • Provides programmable access timing • Provides three NAND FIFOs—ECC buffer, Write FIFO, and Read FIFO, using single-error detection/correction and double-error detection NAND Flash Controller Block Diagram and System Integration The flash controller receives commands and data from the host through the command and data slave interface. The host accesses the flash controller’s control and status registers (CSRs) through the register slave interface. The flash controller handles all command sequencing and flash device interactions. The bootstrap interface supports configuration of the NAND flash controller when booting the HPS from NAND flash memory. The flash controller generates interrupts to the HPS Cortex®-A9 MPCore™ processor generic interrupt © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes Registered no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 a10_54010 13-2 Functional Description of the NAND Flash Controller 2014.08.18 controller. The DMA master interface provides accesses to and from the flash controller through the controller's built-in DMA. Figure 13-1: NAND Flash Controller Block Diagram The following figure shows integration of the NAND flash controller in the HPS. NAND Flash Controller Controller Core Map 00 Master Map 01 A Request Data Interface A DM Sequencer/Status Map 10 NAND Device DM Module fers Interface to f Command Bu Pin Multiplexer Map 11 Data L3 & FIFO Interconnect Interface Map Block ECC Logic Slave Command and Buffer MPU Asynchronous Interrupt Generic Registers Module Interrupt Slave Controller Interface Register Bootstrap Write Read Interface FIFO FIFO ECC Status and Control Signals System Manager Functional Description of the NAND Flash Controller This section describes the functionality of the NAND flash controller. Discovery and Initialization The NAND flash controller requires a specific initialization sequence after the HPS receives power and the flash device is stable. During initialization, the flash controller queries the flash device and configures itself according to one of the following flash device types: • ONFI 1.0 compliant devices • Legacy (non-ONFI) NAND devices The NAND flash controller identifies ONFI-compliant connected devices using ONFI discovery protocol, by sending the Read Electronic Signature command. For devices that do not recognize this command (especially for 512-byte page size devices), software must write to the system manager to assert the bootstrap_512B_device signal to identify the device type before reset is de-asserted. To support booting and initialization, the rdy_busy_in pin must be connected. The NAND flash controller sends the reset command to the connected device. Altera Corporation NAND Flash Controller Send Feedback a10_54010 2014.08.18 Bootstrap Interface 13-3 The NAND flash controller performs the following initialization steps: 1. If the system manager is asserting bootstrap_inhibit_init, the flash controller goes directly to step 7. 2. When the device is ready, the flash controller sends the ONFI Read ID command to read the ONFI signature from the memory device, to determine whether an ONFI or a legacy device is connected. 3. If the data returned by the memory device has an ONFI signature, the flash controller then reads the device parameter page. The flash controller stores the relevant device feature information in internal memory control registers, enabling it to correctly program other registers in the flash device, and goes to step 5. 4. If the data does not have a valid ONFI signature, the flash controller assumes that it is a legacy (non- ONFI) device. The flash controller then performs the following steps: a. Sends the reset command to the device b. Reads the device signature information c. Stores the relevant values into internal memory controller registers 5. The flash controller resets the memory device. At the same time, it verifies the width of the memory interface. The HPS supports one 8-bit or 16-bit NAND flash device. The flash controller detects the memory interface width. 6. The flash controller sends the Page Load command to block 0, page 0 of the device, configuring direct read access, so the processor can boot from that page. The processor can start reading from the first page of the flash memory, which is the expected location of the pre-loader software. Note: The system manager can bypass this step by asserting bootstrap_inhibit_b0p0_load before reset is de-asserted. 7. The flash controller sends the reset command to the flash. 8. The flash controller sets the value of the rst_comp bit in the intr_status0 register in the status group. Bootstrap Interface The NAND flash controller provides a bootstrap interface that allows software to override the default behavior of the flash controller. The bootstrap interface contains four bits, which when set appropriately, allows the flash controller to skip the initialization phase and begin loading from flash memory immediately after reset. These bits are driven by software through the system manager. They are sampled by the NAND flash controller when the controller is released from reset. Related Information System Manager For more information about the bootstrap interface control bits. Bootstrap Setting Bits The following table lists the relevant bootstrap setting bits, found in the system manager’s bootstrap register, in the nandgrp group. This table also lists recommended bootstrap settings for a 512-byte page device. NAND Flash Controller Altera Corporation Send Feedback a10_54010 13-4 Configuration by Host 2014.08.18 Table 13-1: Bootstrap Setting Bits Register Value noinit 1(1) page512 1 noloadb0p0 1 tworowaddr • 1—flash device supports two-cycle addressing • 0—flash device support three-cycle addressing Related Information Configuration by Host on page 13-4 Configuration by Host If the system manager sets bootstrap_inhibit_init to 1, the NAND flash controller does not perform the discovery and initialization process. In this case, the host processor must configure the flash controller. When performance is not a concern in the design, the timing registers can be left unprogrammed. Related Information Bootstrap Setting Bits on page 13-3 For recommended configuration-by-host settings to enable the basic read, write, and erase operations for a single-plane, 512 bytes/page device. Recommended Bootstrap Settings for 512-Byte Page Device Table 13-2: Recommended Bootstrap Settings for 512-Byte Page Device Register(2) Value devices_connected 1 device_width 0 indicating an 8-bit NAND flash device number_of_planes 1 indicating a single-plane device device_main_area_size The value of this register must reflect the flash device’s page main area size. device_spare_area_size The value of this register must reflect the flash device’s page spare area size. pages_per_block The value of this register must reflect number of pages per block in the flash device. (1) When this register is set, the NAND flash controller expects the host to program the related device parameter registers. For more information, refer to Configuration by Host. (2) All registers are in the config group. Altera Corporation NAND Flash Controller Send Feedback a10_54010 2014.08.18 NAND Page Main and Spare
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