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IIIHIIIHIIII US005333120A United States Patent (19) (11) Patent Number: 5,333,120 Gilbert 45) Date of Patent: Jul

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IIIHIIIHIIII US005333120A United States Patent (19) (11) Patent Number: 5,333,120 Gilbert 45) Date of Patent: Jul IIIHIIIHIIII US005333120A United States Patent (19) (11) Patent Number: 5,333,120 Gilbert 45) Date of Patent: Jul. 26, 1994 (54) BINARY TWO'S COMPLEMENT (57) ABSTRACT ARTHMETCCRCUIT A negation circuit (28) generates a two's complement (76) Inventor: Joseph R. Gilbert, 1802 W. Cholla negation by inverting only those bits of an incoming St., Unit 210, Phoenix, Ariz. number which have a level of significance greater than 85029-3769 the significance level at which a transition bit resides. The transition bit and all bits of the incoming number (21) Appl. No.: 977,652 having a significance level less than the transition bit are (22 Filed: Nov. 17, 1992 reproduced at the output (32) of the negation circuit (28). The transition bit is the least significant bit in the 51) Int. Cl................................................. G06F 7/50 incoming number to exhibit a logic one. A negation 52 U.S. C. ................................ 364/786; 364/715.01 selector circuit (40) selectively overrides the negation 58) Field of Search............ 364/786, 787, 788, 715.01 so that a negation is generated only when a select nega 56) References Cited tion signal (34) is active. When a transition detected U.S. PATENT DOCUMENTS input signal (38) is active, all bits of the incoming num ber are inverted- A transition detected output signal 3,816,734 6/1974 Brendzel ............................. 364/786 3,975,624 8/1976 Kay ..................................... 364/786 (36) provides a signal which activates to indicate that 3,976,866 8/1976 Motegiet al. .. 364/786 the circuit (28) has detected a transition bit. The nega 4,707,800 1 1/1987 Montrone et al. ..... tion circuit (28) may be coupled to an adder (66) to form 364/788 a direct subtractor or a direct adder/subtractor (64). Primary Examiner-David H. Malzahn Attorney, Agent, or Firm-Donald J. Lisa; Steven Lin 26 Claims, 6 Drawing Sheets NEGATION SELECTR SELECTIVE NVERTOR LiftsTRANSITION BIT DETECTOR U.S. Patent July 26, 1994 Sheet 1 of 6 5,333,120 Palºº?/21,B^N;N?ILJSNv?). TOLFOOTOOLLOETLILIIOTOTOOOIIO__F?l????LOIF?OTT?TO I_.TOETOETOEDOELL?010F?LOTTO LIFTÕLLIOLIDIOTIFTIT?T?T I_FOFFOTODOLG_LOIOTOTTOE I?,31SV*XISS3·LDN30ILISNwèl1NDI18 I_0010_(D)LTOLLOF?|LIO LT-T-T-T-T-T-FTIT?TOOLLOI00UFTITLIFITOTOOIDIODO TILL0000_TTT OTOELOEDDOLL D(O)L_0_[LIIII_(O)TO?ILODOO LOLFI????????FŒTO LODILT(|)||0TTTTOT? ]I_F-T-T-T-T-T-3IDIOOFTIT?TOT _(13103130~]'####| FTõõ??D?TOLFOOTOGTOELOL FTOOTOLIITOOLFOTFOLI_ ZL)FT?õõ?IODOLFT-I-T-I-O-T, U.S. Patent July 26, 1994 Sheet 2 of 6 5,333,120 oTDI o AD 34 ND0 3OA 32A NEGATION SELECTOR SN1 A1 C O SELECTIVE INVERTOR A2 SNO2 O r 32C A3 is . U.S. Patent July 26, 1994 Sheet 3 of 6 5,333,120 SN AD SNOO O 30A 32A NEGATION SELECTOR Al 3OB le) SELECTIVEINVERTOR A2 F 3OC I.L-3) A3 . TRANSITION BIT 28 DETECTOR U.S. Patent July 26, 1994 Sheet 5 of 6 5,333,120 SN D so D D SNDO * - THD a O 30C ItHRT Dshoe O i-D =HEDt - | HD EDs; 28 IIIB7 - " FIG s LLE is U.S. Patent July 26, 1994 Sheet 6 of 6 5,333,120 3OD 32D 68D C 30C 68C ( 30B 68B ( 30A 63A ( 32A 28 36 V 7 OD O-Hi | || t 7 oc L -70B 270A 64 FIG 6 N. 5,333,120 2 efficiently generate negations for incoming numbers BINARY TWO'S COMPLEMENT ARTHMETC having any number of bits. CRCUT The above and other advantages of the present inven tion are carried out in one form by a binary two's com TECHNICAL FIELD OF THE INVENTION 5 plement arithmetic circuit for performing arithmetic The present invention relates generally to digital operations on an incoming number. The incoming num electronic circuits, such as those used in general pur ber is expressed as N bits, where N is an integer number, pose computers and microprocessors and in special where each of the N bits exhibits either a logic zero or purpose machines. More specifically, the present inven a logic one, and where a transition bit from these N bits tion relates to electronic circuits which are used in 10 is the least significant one of the N bits to exhibit a logic performing arithmetic operations on two's complement one. The circuit includes an input section that has N binary numbers. terminals. The N terminals are adapted to receive the N bits of the incoming number in a one-to-one correspon BACKGROUND OF THE INVENTION dence. A combinatorial logic circuit couples to the Conventional binary arithmetic circuits perform 15 arithmetic operations, particularly subtraction and ne input section. The combinatorial logic circuit is config gation, in an indirect and inefficient manner. Subtrac ured to invert all bits of the incoming number having tion has been performed by inverting a subtrahend num greater significance than the transition bit and to trans ber to form a one's complement of the subtrahend, add fer, without inverting, the transition bit and all bits ing the inverted subtrahend to a minuend number, and 20 having less significance than the transition bit. An out then incrementing the addition result. The incrementing put section couples to the combinatorial logic circuit. of the addition result is typically accomplished by sup The output section has at least N-1 terminals corre plying a carry pulse to an adder when a subtraction is sponding to the N-1 most significant ones of the N bits performed. A simple negation has been treated as a of the incoming number. special subtraction problem with the minuend forced to 25 BRIEF DESCRIPTION OF THE DRAWINGS equal zero. Thus, the same indirect steps are involved in obtaining a two's complement negation of an incoming A more complete understanding of the present inven number. Often, additional enabling combinatorial logic tion may be derived by referring to the detailed descrip is required to selectively invert the subtrahend and to tion and claims when considered in connection with the selectively apply the carry pulse when a subtraction or 30 Figures, wherein like reference numbers refer to similar negation operation is required and to prevent inversion items throughout the Figures, and: of the subtrahend and addition of a carry pulse when FIG. 1 presents a table of two's complement binary addition and other arithmetic operations are required. notations with respect to a four bit numbering system; In many situations, the indirect techniques for per FIG. 2 shows a schematic logic diagram of a first forming subtraction and negation operations are unde 35 embodiment of a selective negation slice circuit which sirable. These indirect techniques often require an unde selectively negates an incoming four bit number; sirably large amount of circuit area or number of com FIG. 2A shows a schematic logic diagram of an alter ponents for their implementation. Moreover, these indi native first embodiment of a selective negation circuit rect techniques often cause the propagation delay be which selectively negates an incoming number; tween the time when an incoming number is valid and FIG.3 shows a block diagram of a selective negation the time when the subtraction or negation operation circuit which includes numerous selective negation results are valid to be undesirably long. slice circuits; FIG. 4 shows a schematic logic diagram of a second suMMARY OF THE INVENTION embodiment of a transition bit detector portion of a Accordingly, it is an advantage of the present inven 45 selective negation slice circuit; tion that an improved arithmetic circuit is provided. FIG. 5 shows a schematic logic diagram of a second Another advantage of the present invention is that an embodiment of a selective negation slice circuit; and arithmetic circuit is provided which may be incorpo FIG. 6 shows a four bit direct adder/subtractor cir rated in a wide variety of applications, including arith cuit which incorporates a selective negation slice cir metic logic units (ALUs) for microprocessors or other 50 cuit. computing circuits, add/subtract circuits, subtraction In the following description of preferred embodi circuits, and negation circuits. ments, certain items are either identical to or closely Another advantage of the present invention is that an related to other items. This description distinguishes arithmetic circuit is provided which generates a two's such items from their counterparts by the use of lower complement negation of an incoming number in a small 55 case alphabetic characters ("a", "b", and so on) which amount of space and with a small amount of propaga are appended to a common reference number. When an tion delay. alphabetic character is omitted, the description refers to Another advantage of the present invention is that an any one of such items and their counterparts individu arithmetic circuit is provided which selectively gener ally or to all of them collectively. ates a negation of an incoming number. Another advantage of the present invention is that an DETAILED DESCRIPTION OF THE arithmetic circuit is provided which selectively per PREFERRED EMBODIMENTS forms addition or subtraction operations, wherein the FIG. 1 presents a table of two's complement binary subtraction operations are performed in a direct manner notations with respect to a four bit numbering system. which does not require the generation of a carry input 65 Incoming number columns 10 and 12 show decimal and pulse. binary representations, respectively, of a four bit num Another advantage of the present invention is that an ber upon which a selective negation slice circuit, dis arithmetic circuit is provided which may be adapted to cussed below, operates. Rows listed in the table of FIG. 5,333,120 3 4. 1 are dedicated to each of 16 different numbers repre of the incoming number having a significance level less sentable in a four bit numbering system.
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