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Bits and Bytes and Words, Oh My!

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Bits and Bytes and Words, Oh My! Bits and Bytes and Words, Oh My! Let’s get down to the real ni8y gri8y • CIS 211 In principle you already know ... Computer memory is binary (base 2) Everything: instrucEons, numbers, strings, ... memory is just one big array of binary numbers If I ask you what 01101011101010 represents, the only correct answer is “it depends” 0 = False = 0 volts; 1 = True = 5 volts (maybe) • CIS 211 CPU and Memory Main Memory CPU Address ALU Reg Reg Reg Values Reg Reg Reg Reg Reg Reg Other buses • CIS 211 CPU and Memory (simplified*) Main Memory CPU Address ALU Reg Reg Reg Values Reg Reg Reg Reg Reg Reg Other buses • CIS 211 (*with several useful lies) CPU and Memory CPU places a memory address on the address bus CPU may place a value on the data base and assert a “write” line (wire) or assert a “read” line and read a value from the data bus Main Memory CPU Address ALU Reg Reg Reg Values Reg Reg Reg Reg Reg Reg Other buses • CIS 211 A few terms: • A bit is a single binary digit • A byte is 8 binary digits • Most computer memory is “byte addressed”; a byte is the smallest addressable unit • What’s half a byte? (4 bits)? • A “word” is a sequence of bytes • Usually 4 bytes (32 bits) or 8 bytes (64 bits) depending on the computer (see next slide) 1 = True = 5 volts ; 0 = False = 0 volts (or 3.3 volts) • CIS 211 Typical byte-addressed memory 15 0 1 0 1 0 0 0 1 with 32-bit words 14 0 0 1 0 0 1 0 0 13 1 1 0 0 1 1 1 0 12 0 0 0 1 1 0 0 0 11 0 1 0 0 1 1 0 0 10 0 0 0 0 0 0 0 0 9 0 0 0 1 1 0 0 0 8 0 0 0 0 0 1 1 0 7 0 0 0 0 0 0 0 0 6 0 0 1 1 1 0 0 1 5 0 1 1 0 0 1 1 0 4 0 1 1 1 1 0 0 0 3 0 1 1 1 0 0 0 0 2 0 0 1 1 1 0 1 0 Memory 1 1 1 0 0 1 1 0 0 addresses: 0 0 0 1 1 0 0 0 0 Word • CIS 211 Word size A “32-bit CPU architecture” Has 32-bit registers (special high-speed memory cells within the CPU) Has 32-bit addresses (32 wires on address bus) Fetches and stores values from memory 32 bits at a Eme (sort of) (32 wires on data bus) A “64-bit CPU architecture” has 64-bit registers, addresses, and data movement (64 wires on address & data bus) • CIS 211 Bit numbering We normally number the bits of a word from 0 to word-size - 1 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 31 30 29 28 27 … 5 4 3 2 1 0 Bit n has value 2n (for posiEve and unsigned numbers – negave numbers use 2s complement representaon) • CIS 211 What the hex? ConverEng between decimal and binary is a pain and binary is hard to read and write But ... base 16 (hexadecimal) is excellent: Each hex digit represents 4 bits; 2 hex digits represent 1 byte digits 0,1,2,3,4,5,6,7,8,9,A,B,C,d,E,F F1 3316 is 1111 0001 0011 00112 Easy peasy! • CIS 211 It is always binary internally If I write v = 13, Python converts 13 to 011012 before storing If I write v = 0b01101 Python stores exactly the same number If I write v = 0xd Python stores exactly the same number Always binary. The conversions is when Python reads or prints the number. • CIS 211 Hex values to know by heart Hex Binary Decimal 0 0000 0 1 0001 1 7 0111 7 F 1111 15 FF 1111,1111 255 You will use these a lot, especially in “masking”, e.g., use w & x0F to get the low 8 bits of w use w & xF0 to get the second nybble of w • CIS 211 Packing bit fields A computer architecture typically packs a whole instrucEon into different “bit fields” in a word Operaon code (the instrucEon) Operands (register numbers, small constants, and/or memory addresses) duck machine model 2018S instrucEon word 22-25 (4 bits) Op code Condition Target Register Src 1 Reg Src 2 Reg Offset V P Z M 31 26-30 18-21 14-17 10-13 0-9 & & & & reserved (5 bits) (4 bits) (4 bits) (4 bits) (10 bits, signed) • CIS 211 ShiOing bits (in an 8-bit word) 0 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 << 2 1 0 1 0 1 1 0 0 7 6 5 4 3 2 1 0 0 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 >> 2 0 0 0 1 1 0 1 0 7 6 5 4 3 2 1 0 1 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 >> 2 1 1 1 1 1 0 1 0 7 6 5 4 3 2 1 0 • CIS 211 Masking (and, or) 0 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 & 0 0 1 1 1 0 0 0 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 0 7 6 5 4 3 2 1 0 0 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 | 0 0 1 1 1 0 0 0 7 6 5 4 3 2 1 0 0 1 1 1 1 0 1 1 7 6 5 4 3 2 1 0 • CIS 211 Masking Think of it like a stencil for spray-paint, or image masking in graphics. & 1 1 1 1 • CIS 211 Packing bits: Masking and shiOing Suppose I want to pack two 4-bit numbers (0..15) into one integer ... 1510 = xF = 11112 a good “mask” for 4 bits Help me code pack(x: int, y: int) -> int and unpack(w: int) -> (int, int) where x and y must be in range 0..15 • CIS 211 OperaSon field of DM2018W 22-25 (4 bits) ... Op code Condition Target Register . V P Z M 26-30 18-21 (5 bits) (4 bits) How can we extract bits 26—30 as a 5-bit posiEve integer (range 0..31)? • CIS 211 Python EnumeraSons Look like classes, but they act peculiar ... class OpCode(Enum): >>> from instr_format import OpCode LOAd = 1 >>> OpCode(2) STORE = 2 <OpCode.STORE: 2> Add = 3 >>> OpCode["STORE"] SUB = 5 <OpCode.STORE: 2> MUL = 6 >>> dIV = 7 SAVE = 8 RESTORE = 9 We’ll convert the operaon code biield into an OpCode enumeraon object for execuEon • CIS 211 The condion code field (inspired by ARM CPU instrucEon predicaon) 24-26 (3 bits) InstrucEon is executed only if Condition instrucEon (condiEon & condiEon code) N Z P is non-zero & & & N Z P Condition Code Register Example: if instrucEon condiEon is 010, and last instrucEon had a posiEve result, this instrucEon will be skipped • CIS 211 NegaSve numbers Only the offset field of the dM2018S instrucEon word is “signed” (can be negave) It is in bits 0..9 and represents a quanEty from -29 to 29 – 1 in 2s complement 0 is x000 3 is x003 -1 is xFFF 10 -5 is 11 1111 10112 or x3FB = 2 – 5 (slightly tricky in Python; I’ll provide negaon) • CIS 211 Assignment: Decode instrucons I’ll provide class InstrucEon with fields for operaon code, condiEon flags, etc You provide translaon from 32-bit integer into an InstrucEon object The following week: The full dM2018S CPU and memory with fetch/decode/execute cycle. (Then we’ll translate from assembly code, then we’ll translate from a higher level language) • CIS 211 You are here ⦿ Main Memory CPU Address Control Logic Instruction decoding ALU Values Reg Reg Reg Reg Reg Reg Reg Reg Reg Other buses • CIS 211 .
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