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Altivec™ Technology Programming Environments Manual AltiVec™ Technology Programming Environments Manual ALTIVECPEM Rev. 3, 04/2006 How to Reach Us: Home Page: www.freescale.com email: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) Information in this document is provided solely to enable system and software +49 89 92103 559 (German) implementers to use Freescale Semiconductor products. There are no express or +33 1 69 35 48 48 (French) implied copyright licenses granted hereunder to design or fabricate any integrated [email protected] circuits or integrated circuits based on the information in this document. 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Box 5405 unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor Denver, Colorado 80217 and its officers, employees, subsidiaries, affiliates, and distributors harmless against all (800) 441-2447 claims, costs, damages, and expenses, and reasonable attorney fees arising out of, 303-675-2140 directly or indirectly, any claim of personal injury or death associated with such Fax: 303-675-2150 LDCForFreescaleSemiconductor unintended or unauthorized use, even if such claim alleges that Freescale @hibbertgroup.com Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2001, 2003, 2006. All rights reserved. Document Number: ALTIVECPEM Rev. 3, 04/2006 Overview 1 AltiVec Register Set 2 Operand Conventions 3 Addressing Modes and Instruction Set Summary 4 Cache, Interrupts, and Memory Management 5 AltiVec Instructions 6 AltiVec Instruction Set Listings A Revision History B Glossary GLO Index IND 1 Overview 2 AltiVec Register Set 3 Operand Conventions 4 Addressing Modes and Instruction Set Summary 5 Cache, Interrupts, and Memory Management 6 AltiVec Instructions A AltiVec Instruction Set Listings B Revision History GLO Glossary IND Index Contents Paragraph Page Number Title Number About ThisContents Book Audience ............................................................................................................................xx Organization.......................................................................................................................xx Suggested Reading........................................................................................................... xxi General Information..................................................................................................... xxi Related Documentation................................................................................................ xxi Conventions .................................................................................................................... xxii Acronyms and Abbreviations ........................................................................................ xxiii Terminology Conventions................................................................................................xxv Chapter 1 Overview 1.1 Overview.......................................................................................................................... 1-1 1.2 AltiVec Technology Overview......................................................................................... 1-3 1.2.1 Levels of AltiVec ISA.................................................................................................. 1-4 1.2.2 Features Not Defined by AltiVec ISA ......................................................................... 1-5 1.3 AltiVec Architectural Model............................................................................................ 1-5 1.3.1 AltiVec Registers and Programming Model ................................................................ 1-5 1.3.2 Operand Conventions .................................................................................................. 1-6 1.3.2.1 Byte Ordering .......................................................................................................... 1-6 1.3.2.2 Floating-Point Conventions..................................................................................... 1-7 1.3.3 AltiVec Addressing Modes .......................................................................................... 1-7 1.3.4 AltiVec Instruction Set................................................................................................. 1-9 1.3.5 AltiVec Cache Model................................................................................................. 1-10 1.3.6 AltiVec Interrupt Model............................................................................................. 1-10 1.3.7 Memory Management Model .................................................................................... 1-10 Chapter 2 AltiVec Register Set 2.1 Overview of AltiVec and PowerPC Registers ................................................................. 2-1 2.2 AltiVec Register Set Overview ........................................................................................ 2-3 2.3 Registers Defined by AltiVec ISA................................................................................... 2-3 2.3.1 AltiVec Vector Register File (VRF)............................................................................. 2-4 2.3.2 Vector Status and Control Register (VSCR)................................................................ 2-4 2.3.3 Vector Save/Restore Register (VRSAVE) ................................................................... 2-6 AltiVec™ Technology Programming Enviroments Manual, Rev. 3 Freescale Semiconductor v Contents Paragraph Page Number Title Number 2.4 Additions to PowerPC UISA Registers ........................................................................... 2-7 2.4.1 PowerPC Condition Register....................................................................................... 2-7 2.5 Additions to PowerPC OEA Registers ............................................................................ 2-8 2.5.1 AltiVec Field Added in the PowerPC Machine State Register (MSR)........................ 2-8 2.5.2 Machine Status Save/Restore Registers (SRRs).......................................................... 2-9 2.5.2.1 Machine Status Save/Restore Register 0 (SRR0).................................................... 2-9 2.5.2.2 Machine Status Save/Restore Register 1 (SRR1).................................................. 2-10 Chapter 3 Operand Conventions 3.1 Data Organization in Memory ......................................................................................... 3-1 3.1.1 Aligned and Misaligned Accesses ............................................................................... 3-1 3.1.2 AltiVec Byte Ordering................................................................................................. 3-2 3.1.2.1 Big-Endian Byte Ordering....................................................................................... 3-2 3.1.2.2 Little-Endian Byte Ordering.................................................................................... 3-2 3.1.3 Quad Word Byte Ordering Example............................................................................ 3-3 3.1.4 Aligned Scalars in Little-Endian Mode ......................................................................
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