DOCSLIB.ORG

Science Journals — AAAS

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Science Journals — AAAS RESEARCH ◥ and sporadically and must ultimately face di- REVIEW SUMMARY minishing returns. As such, we see the big- gest benefits coming from algorithms for new COMPUTER SCIENCE problem domains (e.g., machine learning) and from developing new theoretical machine There’s plenty of room at the Top: What will drive models that better reflect emerging hardware. ◥ Hardware architectures computer performance after Moore’s law? ON OUR WEBSITE can be streamlined—for Read the full article instance, through proces- Charles E. Leiserson, Neil C. Thompson*, Joel S. Emer, Bradley C. Kuszmaul, Butler W. Lampson, at https://dx.doi. sor simplification, where Daniel Sanchez, Tao B. Schardl org/10.1126/ a complex processing core science.aam9744 is replaced with a simpler .................................................. core that requires fewer BACKGROUND: Improvements in computing in computing power stalls, practically all in- transistors. The freed-up transistor budget can power can claim a large share of the credit for dustries will face challenges to their produc- then be redeployed in other ways—for example, manyofthethingsthatwetakeforgranted tivity. Nevertheless, opportunities for growth by increasing the number of processor cores in our modern lives: cellphones that are more in computing performance will still be avail- running in parallel, which can lead to large powerful than room-sized computers from able, especially at the “Top” of the computing- efficiency gains for problems that can exploit 25 years ago, internet access for nearly half technology stack: software, algorithms, and parallelism. Another form of streamlining is the world, and drug discoveries enabled by hardware architecture. domain specialization, where hardware is cus- powerful supercomputers. Society has come tomized for a particular application domain. Downloaded from to rely on computers whose performance in- ADVANCES: Software can be made more effi- This type of specialization jettisons processor creases exponentially over time. cient by performance engineering: restructur- functionality that is not needed for the domain. Much of the improvement in computer per- ing software to make it run faster. Performance It can also allow more customization to the formance comes from decades of miniatur- engineering can remove inefficiencies in pro- specific characteristics of the domain, for in- ization of computer components, a trend that grams, known as software bloat, arising from stance, by decreasing floating-point precision was foreseen by the Nobel Prize–winning phys- traditional software-development strategies for machine-learning applications. http://science.sciencemag.org/ icist Richard Feynman in his 1959 address, that aim to minimize an application’s devel- Inthepost-Mooreera,performanceim- “There’s Plenty of Room at the Bottom,” to opment time rather than the time it takes to provements from software, algorithms, and the American Physical Society. In 1975, Intel run. Performance engineering can also tailor hardware architecture will increasingly re- founder Gordon Moore predicted the regu- software to the hardware on which it runs, quire concurrent changes across other levels larity of this miniaturization trend, now called for example, to take advantage of parallel pro- of the stack. These changes will be easier to im- Moore’s law, which, until recently, doubled the cessors and vector units. plement, from engineering-management and number of transistors on computer chips every Algorithms offer more-efficient ways to solve economic points of view, if they occur within 2 years. problems. Indeed, since the late 1970s, the time big system components: reusable software with Unfortunately, semiconductor miniaturiza- to solve the maximum-flow problem improved typically more than a million lines of code or tion is running out of steam as a viable way nearly as much from algorithmic advances hardware of comparable complexity. When a to grow computer performance—there isn’t as from hardware speedups. But progress on single organization or company controls a big on June 5, 2020 much more room at the “Bottom.” If growth a given algorithmic problem occurs unevenly component, modularity can be more easily re- engineered to obtain performance gains. More- over, costs and benefits can be pooled so that The Top important but costly changes in one part of the big component can be justified by benefits Technology elsewhere in the same component. OUTLOOK: As miniaturization wanes, the silicon- fabrication improvements at the Bottom will Software Algorithms Hardware architecture no longer provide the predictable, broad-based Opportunity Software performance New algorithms Hardware streamlining gains in computer performance that society has engineering enjoyed for more than 50 years. Software per- formance engineering, development of algo- Examples Removing software bloat New problem domains Processor simplification rithms, and hardware streamlining at the Tailoring software to New machine models Domain specialization Top can continue to make computer applica- hardware features tions faster in the post-Moore era. Unlike the historical gains at the Bottom, however, gains at the Top will be opportunistic, uneven, and sporadic. Moreover, they will be subject to diminishing returns as specific computations The Bottom become better explored.▪ for example, semiconductor technology SCIENCE Performance gains after Moore’s law ends. In the post-Moore era, improvements in computing power will The list of author affiliations is available in the full article online. “ ” “ ” *Corresponding author. Email: [email protected] increasingly come from technologies at the Top of the computing stack, not from those at the Bottom , Cite this article as C. E. Leiserson et al., Science 368, CREDIT: N. CARY/ reversing the historical trend. eaam9744 (2020). DOI: 10.1126/science.aam9744 Leiserson et al., Science 368, 1079 (2020) 5 June 2020 1of1 RESEARCH ◥ Working at the Top to obtain performance REVIEW also differs from the Bottom in how it affects a computing system overall. The performance COMPUTER SCIENCE provided by miniaturization has not required substantial changes at the upper levels of the There’s plenty of room at the Top: What will drive computing stack, because the logical behavior of the digital hardware, software, and data in computer performance after Moore’s law? a computation is almost entirely independent of the size of the transistors at the Bottom. As Charles E. Leiserson1, Neil C. Thompson1,2*, Joel S. Emer1,3, Bradley C. Kuszmaul1†, a result, the upper levels can take advantage Butler W. Lampson1,4, Daniel Sanchez1, Tao B. Schardl1 of smaller and faster transistors with little or no change. By contrast—and unfortunately— The miniaturization of semiconductor transistors has driven the growth in computer performance for many parts of the Top are dependent on each more than 50 years. As miniaturization approaches its limits, bringing an end to Moore’s law, other, and thus when one part is restructured to performance gains will need to come from software, algorithms, and hardware. We refer to these improve performance, other parts must often technologies as the “Top” of the computing stack to distinguish them from the traditional technologies adapt to exploit, or even tolerate, the changes. at the “Bottom”: semiconductor physics and silicon-fabrication technology. In the post-Moore era, the When these changes percolate through a sys- Top will provide substantial performance gains, but these gains will be opportunistic, uneven, and tem, it can take considerable human effort to sporadic, and they will suffer from the law of diminishing returns. Big system components offer a correctly implement and test them, which in- promising context for tackling the challenges of working at the Top. creases both costs and risks. Historically, the strategies at the Top for improving perform- Downloaded from ance coexisted with Moore’s law and were ver the past 50 years, the miniaturiza- physics of materials changes at atomic levels— used to accelerate particular applications that tion of semiconductor devices has been and because of the economics of chip manu- needed more than the automatic performance at the heart of improvements in com- facturing. Although semiconductor technology gains that Moore’s law could provide. puter performance, as was foreseen by may be able to produce transistors as small Here, we argue that there is plenty of room O http://science.sciencemag.org/ physicist Richard Feynman in his 1959 as 2 nm (20 Å), as a practical matter, min- at the Top, and we outline promising opportu- address (1) to the American Physical Society, iaturization may end around 5 nm because of nities within each of the three domains of soft- “There’s Plenty of Room at the Bottom.” Intel diminishing returns (10). And even if semi- ware, algorithms, and hardware. We explore founder Gordon Moore (2)observedasteady conductor technologists can push things a little the scale of improvements available in these rate of miniaturization and predicted (3)that further, the cost of doing so rises precipitously areas through examples and data analyses. We the number of transistors per computer chip as we approach atomic scales (11, 12). also discuss why “big system components” will would double every 2 years—a cadence, called In this review, we discuss alternative ave- provide a fertile ground for capturing these Moore’s law, that has held up considerably nues for growth in computer performance after gains at the Top.
Load more

Recommended publications
  • Low-Power Computing
    LOW-POWER COMPUTING Safa Alsalman a, Raihan ur Rasool b, Rizwan Mian c a King Faisal University, Alhsa, Saudi Arabia b Victoria University, Melbourne, Australia c Data++, Toronto, Canada Corresponding email: [email protected] Abstract With the abundance of mobile electronics, demand for Low-Power Computing is pressing more than ever. Achieving a reduction in power consumption requires gigantic efforts from electrical and electronic engineers, computer scientists and software developers. During the past decade, various techniques and methodologies for designing low-power solutions have been proposed. These methods are aimed at small mobile devices as well as large datacenters. There are techniques that consider design paradigms and techniques including run-time issues. This paper summarizes the main approaches adopted by the IT community to promote Low-power computing. Keywords: Computing, Energy-efficient, Low power, Power-efficiency. Introduction In the past two decades, technology has evolved rapidly affecting every aspect of our daily lives. The fact that we study, work, communicate and entertain ourselves using all different types of devices and gadgets is an evidence that technology is a revolutionary event in the human history. The technology is here to stay but with big responsibilities comes bigger challenges. As digital devices shrink in size and become more portable, power consumption and energy efficiency become a critical issue. On one end, circuits designed for portable devices must target increasing battery life. On the other end, the more complex high-end circuits available at data centers have to consider power costs, cooling requirements, and reliability issues. Low-power computing is the field dedicated to the design and manufacturing of low-power consumption circuits, programming power-aware software and applying techniques for power-efficiency [1][2].
    [Show full text]
  • Computer Organization and Architecture Designing for Performance Ninth Edition
    COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION William Stallings Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montréal Toronto Delhi Mexico City São Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editorial Director: Marcia Horton Designer: Bruce Kenselaar Executive Editor: Tracy Dunkelberger Manager, Visual Research: Karen Sanatar Associate Editor: Carole Snyder Manager, Rights and Permissions: Mike Joyce Director of Marketing: Patrice Jones Text Permission Coordinator: Jen Roach Marketing Manager: Yez Alayan Cover Art: Charles Bowman/Robert Harding Marketing Coordinator: Kathryn Ferranti Lead Media Project Manager: Daniel Sandin Marketing Assistant: Emma Snider Full-Service Project Management: Shiny Rajesh/ Director of Production: Vince O’Brien Integra Software Services Pvt. Ltd. Managing Editor: Jeff Holcomb Composition: Integra Software Services Pvt. Ltd. Production Project Manager: Kayla Smith-Tarbox Printer/Binder: Edward Brothers Production Editor: Pat Brown Cover Printer: Lehigh-Phoenix Color/Hagerstown Manufacturing Buyer: Pat Brown Text Font: Times Ten-Roman Creative Director: Jayne Conte Credits: Figure 2.14: reprinted with permission from The Computer Language Company, Inc. Figure 17.10: Buyya, Rajkumar, High-Performance Cluster Computing: Architectures and Systems, Vol I, 1st edition, ©1999. Reprinted and Electronically reproduced by permission of Pearson Education, Inc. Upper Saddle River, New Jersey, Figure 17.11: Reprinted with permission from Ethernet Alliance. Credits and acknowledgments borrowed from other sources and reproduced, with permission, in this textbook appear on the appropriate page within text. Copyright © 2013, 2010, 2006 by Pearson Education, Inc., publishing as Prentice Hall. All rights reserved. Manufactured in the United States of America.
    [Show full text]
  • Trends in Electrical Efficiency in Computer Performance
    ASSESSING TRENDS IN THE ELECTRICAL EFFICIENCY OF COMPUTATION OVER TIME Jonathan G. Koomey*, Stephen Berard†, Marla Sanchez††, Henry Wong** * Lawrence Berkeley National Laboratory and Stanford University †Microsoft Corporation ††Lawrence Berkeley National Laboratory **Intel Corporation Contact: [email protected], http://www.koomey.com Final report to Microsoft Corporation and Intel Corporation Submitted to IEEE Annals of the History of Computing: August 5, 2009 Released on the web: August 17, 2009 EXECUTIVE SUMMARY Information technology (IT) has captured the popular imagination, in part because of the tangible benefits IT brings, but also because the underlying technological trends proceed at easily measurable, remarkably predictable, and unusually rapid rates. The number of transistors on a chip has doubled more or less every two years for decades, a trend that is popularly (but often imprecisely) encapsulated as “Moore’s law”. This article explores the relationship between the performance of computers and the electricity needed to deliver that performance. As shown in Figure ES-1, computations per kWh grew about as fast as performance for desktop computers starting in 1981, doubling every 1.5 years, a pace of change in computational efficiency comparable to that from 1946 to the present. Computations per kWh grew even more rapidly during the vacuum tube computing era and during the transition from tubes to transistors but more slowly during the era of discrete transistors. As expected, the transition from tubes to transistors shows a large jump in computations per kWh. In 1985, the physicist Richard Feynman identified a factor of one hundred billion (1011) possible theoretical improvement in the electricity used per computation.
    [Show full text]
  • Computer Performance Evaluation and Benchmarking
    Computer Performance Evaluation and Benchmarking EE 382M Dr. Lizy Kurian John Evolution of Single-Chip Microprocessors 1970’s 1980’s 1990’s 2010s Transistor Count 10K- 100K-1M 1M-100M 100M- 100K 10 B Clock Frequency 0.2- 2-20MHz 20M- 0.1- 2MHz 1GHz 4GHz Instruction/Cycle < 0.1 0.1-0.9 0.9- 2.0 1-100 MIPS/MFLOPS < 0.2 0.2-20 20-2,000 100- 10,000 Hot Chips 2014 (August 2014) AMD KAVERI HOT CHIPS 2014 AMD KAVERI HOTCHIPS 2014 Hotchips 2014 Hotchips 2014 - NVIDIA Power Density in Microprocessors 10000 Sun’s Surface 1000 Rocket Nozzle ) 2 Nuclear Reactor 100 Core 2 8086 10 Hot Plate 8008 Pentium® Power Density (W/cm 8085 4004 386 Processors 286 486 8080 1 1970 1980 1990 2000 2010 Source: Intel Why Performance Evaluation? • For better Processor Designs • For better Code on Existing Designs • For better Compilers • For better OS and Runtimes Design Analysis Lord Kelvin “To measure is to know.” "If you can not measure it, you can not improve it.“ "I often say that when you can measure what you are speaking about, and express it in numbers, you know something about it; but when you cannot measure it, when you cannot express it in numbers, your knowledge is of a meagre and unsatisfactory kind; it may be the beginning of knowledge, but you have scarcely in your thoughts advanced to the state of Science, whatever the matter may be." [PLA, vol. 1, "Electrical Units of Measurement", 1883-05-03] Designs evolve based on Analysis • Good designs are impossible without good analysis • Workload Analysis • Processor Analysis Design Analysis Performance Evaluation
    [Show full text]
  • Performance Scalability of N-Tier Application in Virtualized Cloud Environments: Two Case Studies in Vertical and Horizontal Scaling
    PERFORMANCE SCALABILITY OF N-TIER APPLICATION IN VIRTUALIZED CLOUD ENVIRONMENTS: TWO CASE STUDIES IN VERTICAL AND HORIZONTAL SCALING A Thesis Presented to The Academic Faculty by Junhee Park In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Computer Science Georgia Institute of Technology May 2016 Copyright c 2016 by Junhee Park PERFORMANCE SCALABILITY OF N-TIER APPLICATION IN VIRTUALIZED CLOUD ENVIRONMENTS: TWO CASE STUDIES IN VERTICAL AND HORIZONTAL SCALING Approved by: Professor Dr. Calton Pu, Advisor Professor Dr. Shamkant B. Navathe School of Computer Science School of Computer Science Georgia Institute of Technology Georgia Institute of Technology Professor Dr. Ling Liu Professor Dr. Edward R. Omiecinski School of Computer Science School of Computer Science Georgia Institute of Technology Georgia Institute of Technology Professor Dr. Qingyang Wang Date Approved: December 11, 2015 School of Electrical Engineering and Computer Science Louisiana State University To my parents, my wife, and my daughter ACKNOWLEDGEMENTS My Ph.D. journey was a precious roller-coaster ride that uniquely accelerated my personal growth. I am extremely grateful to anyone who has supported and walked down this path with me. I want to apologize in advance in case I miss anyone. First and foremost, I am extremely thankful and lucky to work with my advisor, Dr. Calton Pu who guided me throughout my Masters and Ph.D. programs. He first gave me the opportunity to start work in research environment when I was a fresh Master student and gave me an admission to one of the best computer science Ph.D.
    [Show full text]
  • An Algorithmic Theory of Caches by Sridhar Ramachandran
    An algorithmic theory of caches by Sridhar Ramachandran Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Master of Science at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY. December 1999 Massachusetts Institute of Technology 1999. All rights reserved. Author Department of Electrical Engineering and Computer Science Jan 31, 1999 Certified by / -f Charles E. Leiserson Professor of Computer Science and Engineering Thesis Supervisor Accepted by Arthur C. Smith Chairman, Departmental Committee on Graduate Students MSSACHUSVTS INSTITUT OF TECHNOLOGY MAR 0 4 2000 LIBRARIES 2 An algorithmic theory of caches by Sridhar Ramachandran Submitted to the Department of Electrical Engineeringand Computer Science on Jan 31, 1999 in partialfulfillment of the requirementsfor the degree of Master of Science. Abstract The ideal-cache model, an extension of the RAM model, evaluates the referential locality exhibited by algorithms. The ideal-cache model is characterized by two parameters-the cache size Z, and line length L. As suggested by its name, the ideal-cache model practices automatic, optimal, omniscient replacement algorithm. The performance of an algorithm on the ideal-cache model consists of two measures-the RAM running time, called work complexity, and the number of misses on the ideal cache, called cache complexity. This thesis proposes the ideal-cache model as a "bridging" model for caches in the sense proposed by Valiant [49]. A bridging model for caches serves two purposes. It can be viewed as a hardware "ideal" that influences cache design. On the other hand, it can be used as a powerful tool to design cache-efficient algorithms.
    [Show full text]
  • 02 Computer Evolution and Performance
    Computer Architecture Faculty Of Computers And Information Technology Second Term 2019- 2020 Dr.Khaled Kh. Sharaf Computer Architecture Chapter 2: Computer Evolution and Performance Computer Architecture LEARNING OBJECTIVES 1. A Brief History of Computers. 2. The Evolution of the Intel x86 Architecture 3. Embedded Systems and the ARM 4. Performance Assessment Computer Architecture 1. A BRIEF HISTORY OF COMPUTERS The First Generation: Vacuum Tubes Electronic Numerical Integrator And Computer (ENIAC) - Designed and constructed at the University of Pennsylvania, was the world’s first general purpose - Started 1943 and finished 1946 - Decimal (not binary) - 20 accumulators of 10 digits - Programmed manually - 18,000 vacuum tubes by switches - 30 tons -15,000 square feet - 140 kW power consumption - 5,000 additions per second Computer Architecture The First Generation: Vacuum Tubes VON NEUMANN MACHINE • Stored Program concept • Main memory storing programs and data • ALU operating on binary data • Control unit interpreting instructions from memory and executing • Input and output equipment operated by control unit • Princeton Institute for Advanced Studies • IAS • Completed 1952 Computer Architecture Structure of von Neumann machine Structure of the IAS Computer Computer Architecture IAS - details • 1000 x 40 bit words • Binary number • 2 x 20 bit instructions Set of registers (storage in CPU) 1 • Memory buffer register (MBR): Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit. • • Memory address register (MAR): Specifies the address in memory of the word to be written from or read into the MBR. • • Instruction register (IR): Contains the 8-bit opcode instruction being executed.
    [Show full text]
  • Measurement and Rating of Computer Systems Performance
    U'Dirlewanger 06.11.2006 14:39 Uhr Seite 1 About this book Werner Dirlewanger ISO has developed a new method to describe and measure performance for a wide range of data processing system types and applications. This solves the pro- blems arising from the great variety of incompatible methods and performance terms which have been proposed and are used. The method is presented in the International Standard ISO/IEC 14756. This textbook is written both for perfor- mance experts and beginners, and academic users. On the one hand it introdu- ces the latest techniques of performance measurement, and on the other hand it Measurement and Rating is a guide on how to apply the standard. The standard also includes additionally two advanced aspects. Firstly, it intro- of duces a rating method to compute those performance values which are actually required by the user entirety (reference values) and a process which compares Computer Systems Performance the reference values with the actual measured ones. This answers the question whether the measured performance satisfies the user entirety requirements. and of Secondly, the standard extends its method to assess the run-time efficiency of software. It introduces a method for quantifying and measuring this property both Software Efficiency for application and system software. Each chapter focuses on a particular aspect of performance measurement which is further illustrated with exercises. Solutions are given for each exercise. An Introduction to the ISO/ IEC 14756 As measurement cannot be performed manually, software tools are needed. All needed software is included on a CD supplied with this book and published by Method and a Guide to its Application the author under GNU license.
    [Show full text]
  • Computer Performance Factors
    Advanced Computer Architecture (0630561) Lecture 7 Computer Performance Factors Prof. Kasim M. Al-Aubidy Computer Eng. Dept. ACA-Lecture Objective: ACA-Lecture Performance Metrics: ACA-Lecture Performance Metrics: ACA-Lecture CPU Performance Equation: ACA-Lecture CPU Performance Equation: ACA-Lecture Execution Time (T): T = Ic *CPI *t T: CPU time (seconds/program) needed to execute a program. Ic: Number of Instructions in a given program. CPI: Cycle per Instruction. t: Cycle time. t=1/f, f=clock rate. • The CPI can be divided into TWO component terms; - processor cycles (p) - memory cycles (m) • The instruction cycle may involve (k) memory references, for example; k=4; one for instruction fetch, two for operand fetch, and one for store result. T = Ic *( p + m*k)*t ACA-Lecture System Attributes: T =Ic *(p+m*k)*t The above five performance factors (Ic, p, m, k & t) are influenced by these attributes: FACTORS Ic p m k t Instruction set architecture. X X Compiler technology. X X X CPU implementation & control X X Cache & memory hierarchy X X •The instruction set architecture affects program length and p. •Compiler design affects the values of IC, p & m. •The CPU implementation & control determine the total processor time= p*t •The memory technology & hierarchy design affect the memory access time= k*t 7 ACA-Lecture MIPS Rate: • The processor speed is measured in terms of million instructions per seconds. • MIPS rate varies with respect to: – Clock rate (f). – Instruction count ( Ic ). – CPI of a given machine. I f f * I MIPS = c = = c T *106 CPI *106 N *106 Where N is the total number of clock cycles needed to execute a given program.
    [Show full text]
  • A Review of High Performance Computing
    IOSR Journal of Computer Engineering (IOSR-JCE) e-ISSN: 2278-0661, p- ISSN: 2278-8727Volume 16, Issue 1, Ver. VII (Feb. 2014), PP 36-43 www.iosrjournals.org A review of High Performance Computing 1 2 3 G.Sravanthi , B.Grace , V.kamakshamma 1 2 3Department of Computer Science, PBR Visvodaya Institute of Science And Technology, India Abstract: Current high performance computing (HPC) applications are found in many consumers, industrial and research fields. There is a great deal more to remote sensing data than meets the eye, and extracting that information turns out to be a major computational challenges, so the high performance computing (HPC) infrastructure such as MPP (massive parallel processing), clusters, distributed networks or specialized hardware devices are used to provide important architectural developments to accelerate the computations related with information extraction in remote sensing. The focus of HPC has shifted towards enabling the transparent and most efficient utilization of a wide range of capabilities made available over networks. In this paper we review the fundamentals of High Performance Computing (HPC) in a way which is easy to understand and sketch the way to standard computers and supercomputers work, as well as discuss distributed computing and essential aspects to take into account when running scientific calculations in computers. Keywords: High Performance Computing, scientific supercomputing, simulation, computer architecture, MPP, distributed computing, clusters, parallel calculations. I. Introduction High Performance Computing most generally refers to the practice of aggregating computing power in a way that delivers much higher performance than one could get out of a typical desktop computer or workstation in order to solve large problems in science, engineering, or business.
    [Show full text]
  • Performance of a Computer (Chapter 4) Vishwani D
    ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Performance of a Computer (Chapter 4) Vishwani D. Agrawal & Victor P. Nelson epartment of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 ELEC 5200-001/6200-001 Performance Fall 2013 . Lecture 1 What is Performance? Response time: the time between the start and completion of a task. Throughput: the total amount of work done in a given time. Some performance measures: MIPS (million instructions per second). MFLOPS (million floating point operations per second), also GFLOPS, TFLOPS (1012), etc. SPEC (System Performance Evaluation Corporation) benchmarks. LINPACK benchmarks, floating point computing, used for supercomputers. Synthetic benchmarks. ELEC 5200-001/6200-001 Performance Fall 2013 . Lecture 2 Small and Large Numbers Small Large 10-3 milli m 103 kilo k 10-6 micro μ 106 mega M 10-9 nano n 109 giga G 10-12 pico p 1012 tera T 10-15 femto f 1015 peta P 10-18 atto 1018 exa 10-21 zepto 1021 zetta 10-24 yocto 1024 yotta ELEC 5200-001/6200-001 Performance Fall 2013 . Lecture 3 Computer Memory Size Number bits bytes 210 1,024 K Kb KB 220 1,048,576 M Mb MB 230 1,073,741,824 G Gb GB 240 1,099,511,627,776 T Tb TB ELEC 5200-001/6200-001 Performance Fall 2013 . Lecture 4 Units for Measuring Performance Time in seconds (s), microseconds (μs), nanoseconds (ns), or picoseconds (ps). Clock cycle Period of the hardware clock Example: one clock cycle means 1 nanosecond for a 1GHz clock frequency (or 1GHz clock rate) CPU time = (CPU clock cycles)/(clock rate) Cycles per instruction (CPI): average number of clock cycles used to execute a computer instruction.
    [Show full text]
  • HOW MODERATE-SIZED RISC-BASED Smps CAN OUTPERFORM MUCH LARGER DISTRIBUTED MEMORY Mpps
    HOW MODERATE-SIZED RISC-BASED SMPs CAN OUTPERFORM MUCH LARGER DISTRIBUTED MEMORY MPPs D. M. Pressel Walter B. Sturek Corporate Information and Computing Center Corporate Information and Computing Center U.S. Army Research Laboratory U.S. Army Research Laboratory Aberdeen Proving Ground, Maryland 21005-5067 Aberdeen Proving Ground, Maryland 21005-5067 Email: [email protected] Email: sturek@arlmil J. Sahu K. R. Heavey Weapons and Materials Research Directorate Weapons and Materials Research Directorate U.S. Army Research Laboratory U.S. Army Research Laboratory Aberdeen Proving Ground, Maryland 21005-5066 Aberdeen Proving Ground, Maryland 21005-5066 Email: [email protected] Email: [email protected] ABSTRACT: Historically, comparison of computer systems was based primarily on theoretical peak performance. Today, based on delivered levels of performance, comparisons are frequently used. This of course raises a whole host of questions about how to do this. However, even this approach has a fundamental problem. It assumes that all FLOPS are of equal value. As long as one is only using either vector or large distributed memory MIMD MPPs, this is probably a reasonable assumption. However, when comparing the algorithms of choice used on these two classes of platforms, one frequently finds a significant difference in the number of FLOPS required to obtain a solution with the desired level of precision. While troubling, this dichotomy has been largely unavoidable. Recent advances involving moderate-sized RISC-based SMPs have allowed us to solve this problem.
    [Show full text]