Department of Electrical Engineering Indian Institute of Technology (IIT) Jammu Jammu - 181221, India Satyadev Ahlawat T +91-1912570732 H +91 7506051908 B [email protected] Assistant Professor Í www.iitjammu.ac.in/faculty/˜satyadevahlawat

Research Interests VLSI Testing and Design-for-Testability (DfT), Trusted System Design, Hardware Security, High Performance Processor Design Teaching Interests VLSI Design and Test, Cryptography and Hardware Security, Semiconductor Device Physics and Technology, Computer Architecture Education July 2014 - Dec. Doctor of Philosophy, Indian Institute of Technology (IIT) Bombay, India, 2018 Department: Electrical Engineering. Thesis Security and Testability Issues in Modern VLSI Chips Supervisor Prof. Virendra Singh, Dept. of Electrical Engineering, IIT Bombay July 2008 - Aug Master of Technology in Microelectronics, Panjab University, Chandigarh, 2010 Department: University Centre of Instrumentation and Microelectronics (UCIM). Dissertation Minimization of test power during scan test; (done at IISc. Bangalore) July 2006 - May Master of Science in Electronics, Kurukshetra University, Kurukshetra (India), 2008 Department: Electronic Science. Dissertation Fabrication of PIN photodiode and simulation of epitaxial structure of GaN based blue LED; (done at CSIR-CEERI, Pilani) Professional Experience July 2019 - Till Assistant Professor, Indian Institute of Technology (IIT) Jammu, India, . date Department of Electrical Engineering Sep 2018 - June Research Scientist, CADS Laboratory, IIT Bombay, India. 2019 Project Title: Architecting Intelligent Dependable Cyber Physical Systems Targeting IoT and Mobile Big Data Analysis Collaborative Institutes: Indian Institute of Technology (IIT) Bombay, India and The University of Tokyo (UTokyo), Tokyo, Japan Jul 2014 - Jul Teaching Assistant, Indian Institute of Technology (IIT) Bombay, India, . 2018 Department of Electrical Engineering Sep 2012 - June Lecturer, Kurukshetra University, Kurukshetra (India). 2013 Course Instructor of undergraduate Microelectronics and Digital Electronics courses. Dec 2011 - Aug Research Associate, Indian Institute of Technology (IIT) Bombay, India. 2012 Project Title: Development and recommendation of effective high speed test techniques supporting LSI’s test flow Collaborative Institutes: IIT Bombay and LSI India R&D Pvt. Ltd. Aug 2010 - Nov Research Assistant, Indian Institute of Science (IISc), Bangalore (India). 2011 Project Title: Investigation of techniques to speedup loading of scan test patterns Collaborative Institutes: Indian Institute of Science (IISc) and LSI India R&D Pvt. Ltd. Research Funding 2020 − 2022 Project: Securing Quantum Cryptographic Chips Against Scan-based Side-channel Attacks Agency: SERB - Startup research grant; Funding: 30.12 Lacs 2021 - 2024 Institute seed grant for research lab establishment Agency: IIT Jammu; Funding: 30 Lacs Teaching Current semester Jan 2021 EEL318: Digital Hardware Design Jan 2021 EEP305: Design and System Laboratory Jan 2021 EEL748: SoC Design and Test Recent past Aug 2020 EEL305: Computer Architecture Jan 2020 CSL216: Computer Architecture Lab Jan 2020 CSL216: Computer Architecture Jan 2020 EEL316: Introduction to VLSI Design Aug 2019 EEL211: Physical Electronics Professional Activities Institute Coordinator, SPARC, MHRD India, 2019 – 2021 Institute Co-coordinator, GIAN, MHRD India, 2019 – 2021 Warden, Boys Hostel, IIT Jammu, 2019 – 2021 Reviewer, Transactions on VLSI (TVLSI), IEEE Access Member, IEEE Technical Program Committee Member ATS – 2020 Asian Test Symposium (ATS), November 2020, Penang, Malaysia VDAT – 2020 VLSI Design and Test Symposium (VDAT), July 2020, Bhubaneswar, India ITC India–2020 International Test Conference (ITC) India, May 2020, Bangalore, India VDAT – 2019 VLSI Design and Test Symposium (VDAT), July 2019, Indore, India Invited Talks August 2019 Talk on "Chemical Vapour Deposition Techniques", in TEQIP-III (1.3) Spon- sored One Week Faculty Development Program on Nanoscience and Nanotech- nology, Dept. of Electronic Science, Kurukshetra University, India June 2019 Talk on "Testing VLSI Circuits in Nanotechnology Regime : An Introduc- tion", in AICTE Sponsored National Level 2 weeks Faculty Development Program on “Advances in Signal Processing & its Applications”, Sardar Patel Institute of Technology (SPIT), Mumbai, India May 2018 Talk on "Security and Testability Issues in Modern VLSI Chips", in AICTE Sponsored National Level 1 weeks Faculty Development Program on “Digital VLSI Systems Design & implementation”, Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat, India Publications 2021 Jaynarayan Tudu, Satyadev Ahlawat, and Virendra Singh, “Architectural Frame- work for Configurable Joint-scan DFT Architecture” Journal of Electronic Testing: Theory and Applications (JETTA), 2021 [under review] DFT - 2019 Satyadev Ahlawat, Jaynarayan Tudu, Manoj Singh Gaur, Masahiro Fujita and Virendra Singh, “Securing Scan Architecture through Test Response En- cryption”Proceedings in 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2019, ESA−ESTEC & TU Delft, Netherlands, October 02 − 04, 2019, https://doi.org/10.1109/ DFT.2019.8875355 IOLTS - 2019 Satyadev Ahlawat Jaynarayan Tudu, Masahiro Fujita and Virendra Singh, “On Securing Scan through Plain-text Restriction” Proceedings in 25th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2019, Rhodes Island, Greece, July 01 − 03, 2019, https://doi.org/10.1109/ IOLTS.2019.8854411 EWDTS - 2018 Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, and Virendra Singh, “Using MISR as Countermeasure Against Scan-based Side Channel Attacks” Pro- ceedings in 16th IEEE East-West Design and Test Symposium (EWDTS) 2018, Kazan, Russia, Sep 14 − 17, 2018, http://doi.org/10.1109/EWDTS.2018. 8524752 TDMR - 2018 Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, “A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test” IEEE Transactions on Device and Materials Reliability (TDMR) 2018, Volume: 18, Issue: 2, pp. 1 − 11, http://doi.org/10.1109/TDMR.2018. 2835414 ISCAS - 2018 Darshit Vaghani, Satyadev Ahlawat, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, “On Securing Scan Design Through Test Vector Encryption” Proceedings in 51st IEEE International Symposium on Circuits & Systems (ISCAS) 2018, Florence, Italy, May 27 − 30, 2018, https://doi.org/10.1109/ISCAS. 2018.8351212 ISCAS - 2018 Nihar Hage, Satyadev Ahlawat, and Virendra Singh “In-situ Monitoring for Slack Time Violation Without Performance Penalty” Proceedings in 51st IEEE International Symposium on Circuits & Systems (ISCAS) 2018, Florence, Italy, May 27 − 30, 2018, https://doi.org/10.1109/ISCAS.2018.8351000 ATS - 2017 Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, and Virendra Singh, “On Securing Scan Design from Scan-Based Side-Channel Attacks” Proceedings in 26th IEEE Asian Test Symposium (ATS) 2017, Taipei, Taiwan, Nov 27 − 30, 2017, https://doi.org/10.1109/ATS.2017.23 DFT - 2017 Satyadev Ahlawat, Darshit Vaghani, and Virendra Singh, “Preventing Scan- Based Side-Channel Attacks Through Key Masking” Proceedings in 30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2017, Cambridge, UK, October 23 − 25, 2017, https://doi.org/10.1109/DFT.2017.8244434 VDAT - 2017 Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, and Ashok Suhag,“A Cost Effective Technique for Diagnosis of Scan Chain Faults” Proceedings in 21st International Symposium on VLSI Design and Test (VDAT) 2017, Roorkee, India, June 29 -July 2, 2017, CCIS, Springer, Singapore, Volume: 711, pp. 191 − 204, https://doi.org/10.1007/978-981-10-7470-7_20 ISCAS - 2017 Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, and Virendra Singh, “A Low Cost Technique for Scan Chain Diagnosis” Proceedings in 50th IEEE Inter- national Symposium on Circuits & Systems (ISCAS) 2017, Baltimore, USA, May 28 − 31, 2017, https://doi.org/10.1109/ISCAS.2017.8050440 ETS - 2017 Satyadev Ahlawat, Darshit Vaghani, and Virendra Singh, “An Efficient Test Technique to Prevent Scan-Based Side-Channel Attacks” Proceedings in 22nd IEEE European Test Symposium (ETS) 2017, Cyprus, May 22 − 26, 2017, https://doi.org/10.1109/ETS.2017.7968241 EWDTS - 2016 Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, and Virendra Singh, “Enabling LOS delay test with slow scan enable” Proceedings in 14th IEEE East-West Design and Test Symposium (EWDTS) 2016, Yerevan, Armenia, Oct 14 − 17, 2016, https://doi.org/10.1109/EWDTS.2016.7807648 IOLTS - 2016 Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, “A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test” Proceedings in 22nd IEEE International Symposium on Online Testing and Robust System Design (IOLTS) 2016, Catalunya, Spain, July 4 − 6, 2016, https://doi.org/10.1109/IOLTS.2016.7604709 VDAT - 2016 Jaynarayan T. Tudu and Satyadev Ahlawat, “Guided shifting of test pattern to minimize test time in serial scan” Proceedings in 20th International Symposium on VLSI Design and Test (VDAT) 2016, Guwahati, India, May 24 − 27, 2016, https://doi.org/10.1109/ISVDAT.2016.8064851 VDAT - 2016 Satyadev Ahlawat and Jaynarayan T. Tudu, “On Minimization of Test Power through Modified Scan Flip-Flop” Proceedings in 20th International Sympo- sium on VLSI Design and Test (VDAT) 2016, Guwahati, India, May 24 − 27, 2016, https://doi.org/10.1109/ISVDAT.2016.8064878 ATS - 2015 Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, “A New Scan Flip-Flop Design to Eliminate Performance Penalty of Scan” Proceedings in 24th IEEE Asian Test Symposium (ATS) 2015, Mumbai, India, Nov 22 − 25, 2015, https://doi.org/10.1109/ATS.2015.12 WRTLT - 2012 Satyadev Ahlawat, Ashok Suhag, Jaynarayan Tudu, and Virendra Singh, “Power Aware Scan Flip Flop Design for Scan Test” In 13th IEEE Workshop on RTL and High Level Testing (WRTLT) 2012, Niigata, Japan, November 22 − 23, 2012 ATS - 2010 Amit Mishra, Nidhi Sinha, Satyadev Ahlawat, Virendra Singh, Sreejit Chakravarty, and Adit D. Singh, “Modified Scan Flip-Flop for Low Power Testing” Pro- ceedings in 19th IEEE Asian Test Symposium (ATS) 2010, Shanghai, China, December 1 − 4 2010, http://doi.org/10.1109/ATS.2010.69 Current Students Jul 2017 Ms. Aditi Gupta, Ph.D Research: AI and Machine Learning Jul 2020 Mr. Gaurav Kumar, Ph.D Research: High performance computer architecture Dec 2020 Mr. Pradeep Kumar, Ph.D Research: VLSI testing and hardware security Dec 2020 Ms. Anjum Riaz, Ph.D Research: VLSI Testing and secure system design