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Design of High Performance MIPS Cryptography Processor Based On International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 1 Issue 3, May - 2012 Design of High Performance MIPS Cryptography Processor Based on T-DES Algorithm Kirat Pal Singh1, Shivani Parmar2 1Research Fellow, 2Assistant Professor 1Academic and Consultancy Services Division, 2 ECE Department 1Centre for development of advanced computing (C-DAC), 2GGS College 1, 2 Mohali-160071, India ABSTRACT Operation Performed) instruction which generate some The paper describes the design of high performance delays for the proper execution of instruction [4]. The MIPS Cryptography processor based on triple data pipelining Hazards are of three type’s data, structural encryption standard. The organization of pipeline and control hazard. These hazards are handled in the stages in such a way that pipeline can be clocked at MIPS processor by the implementation of forwarding high frequency. Encryption and Decryption blocks of unit, Pre-fetching or Hazard detection unit, branch and triple data encryption standard (T-DES) crypto system jump prediction unit [2]. Forwarding unit is used for and dependency among themselves are explained in preventing data hazards which detects the dependencies detail with the help of block diagram. In order to and forward the required data from the running increase the processor functionality and performance, instruction to the dependent instructions [5]. Stall are especially for security applications we include three occurred in the pipelined architecture when the new 32-bit instructions LKLW, LKUW and CRYPT. The consecutive instruction uses the same operand of the design has been synthesized at 40nm process instruction and that require more clock cycles for technology targeting using Xilinx Virtex-6 device. The execution and reduces performance. To overcome this overall MIPS Crypto processor works at 209MHz. situation, instruction pre-fetching unit is used which reduces the stalls and improve performance. The Keywords control hazard are occurs when a branch prediction is ALU, register file, pipeline, memory, T-DES, mistaken or in general, when the system has no throughput mechanism for handling the control hazards [5]. The 1. INTRODUCTION control hazard is handled by two mechanisms: Flush mechanism and Delayed jump mechanism. The branch oday’s digital world, Cryptography is the art and and jump prediction unit uses these two mechanisms for science that deals with the principles and methods T preventing control hazards. The flush mechanism runs for keeping message secure. Encryption is emerging as instruction after a branch and flushes the pipe after the a disintegrable part of all communication networks and misprediction [5]. Frequent flushing may increase the information processing systems, involving transmission clock cycles and reduce performance. In the delayed of data. Encryption is the transformation of plain data jump mechanism, to handle the control hazard is to fill (known as plaintext) into inintengible data (known as the pipe after the jump instruction with specific cipher text) through an algorithm referred to as cipher. numbers of NOP’s [5]. The branch and jump prediction MIPS architecture employs a wide range of unit placement in the pipelining architecture may affect applications. The architecture remains the same for all the critical or longest path. To detecting the longest MIPS based processors while the implementations may path and improving the hardware that resulting differ [1]. The proposed design has the feature of 32- minimum clock period and is the standard method of bit asymmetric and symmetric cryptography system as increasing the performance of the processor. a security application. There is a 16- bit RSA To further speed up processor and minimize clock cryptography MIPS cryptosystem have been previously period, the design incorporates a high speed hybrid designed [2]. There are the small adjustments and adder which employs both carry skip and carry select minor improvement in the MIPS pipelined architecture techniques with in the ALU unit to handle the additions. design to protect data transmission over insecure This paper is organized as follows. The system medium using authenticating devices such as data architecture hardware design and implementation are encryption standard [DES], Triple-DES and advanced explained in Section II. Instruction set of MIPS encryption standard [AES] [3]. These cryptographic including new instructions in detail with corresponding devices use an identical key for the receiver side and diagrams shown in sub-sections. Hardware sender side. Our design mainly includes the symmetric implementation design methodology is explained in cryptosystem into MIPS pipeline stages. That is suitable section III. The experimental results of pipeline stages to encrypt large amount data with high speed. are shown in section IV. Simulation results of The MIPS is simply known as Millions of encrypted MIPS pipeline processor and their instructions per second and is one of the best RISC Verification & synthesis report are describes in sub (Reduced Instruction Set Computer) processor ever sections. The conclusions of paper are described in designed. High speed MIPS processor possessed section V. Pipeline architecture for speed up processing, increase the frequency and performance of the processor. A 2. SYSTEM ARCHITECTURE MIPS based RISC processor was described in [4]. It The global architecture of encrypted and decrypted consist of basic five stages of pipelining that are pipelined processor is shown in Fig.1 which contain 5 Instruction Fetch, Instruction Decode, Instruction basic pipeline stages that are Instruction Fetch [IF], Execution, Memory access, write back. These five Instruction Decode [ID], Instruction Execution [EXE], pipeline stages generate 5 clock cycles processing delay Memory Access [MEM], Write Back [WB]. These and several Hazard during the operation [2]. These pipeline stages operate concurrently, using pipelining Hazard are eliminates by inserting NOP (No synchronization signals: Clock and Reset. MIPS www.ijert.org 1 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 1 Issue 3, May - 2012 architecture employs three different Instruction format: standard (AES) etc. to the pipeline stage. Only single R-Type Instruction, I-Type Instruction, and J-Type cryptographic module is used in same hardware Instruction [3]. MIPS processor for implementation. In this design, we insert T-DES crypto encryption/decryption we just insert the cryptography core inside the instruction fetch stage and memory module such as data encryption standard (DES), Triple access stage for instructions fetching and data storing. data encryption standard (T-DES), advanced encryption Figure 1. Block diagram of Encrypted/Decrypted MIPS processor 2.1 Encrypted MIPS Processor decrypted instruction. The instruction fetch unit of The 32-bit Encrypted MIPS processor is generally decrypted MIPS processor contains program counter based on MIPS architecture. The pipelined MIPS (PC), instruction memory, T-DES encryption core and architecture is modified in such a way that it executes MUX. The instruction memory read address from PC encrypted instruction. The function of Instruction fetch and store instruction value at the particular address that unit is to obtain an instruction from the instruction points by the PC. Instruction memory sends decrypted memory using the current value of PC and increment instruction to both MUX and encryption core. The PC value for next instruction and placed that value to IF encryption core give encrypted instructions and further register. The instruction fetch unit of encrypted MIPS send to the MUX and output of MUX is fed to the IF contains program counter (PC), instruction memory, T- register. The MUX control signal comes from control DES decryption core and MUX. The instruction unit. The instruction decode unit contain register file memory read address from PC and store instruction and key register. Key register store the key data of value at the particular address that points by the PC. encryption/decryption core. Key address and key data Instruction memory sends encrypted instruction to comes from write back stage. Once the key data to be MUX and decryption core. The decryption core give stored into register file it will remain same for all decrypted instructions and further send to the MUX and program instruction execution. The control unit output of MUX is fed to the IF register. The MUX provides various control signals to other stages. The control signal comes from control unit. The instruction execute unit executes the register file output data and decode unit contain register file and key register. Key perform the particular operation determined by the register store the key data of encryption/decryption ALU. The ALU output data send to EXE register. The core. Key address and key data comes from write back memory access unit contains T-DES encryption core, stage. Once the key data to be stored into register file it T-DES decryption core, data memory, MUX, DEMUX. will remain same for all program instruction execution. The second register data from register file fed to the The control unit provides various control signals to decryption core and also to MUX. Here the crypt signal other stages. The execute unit executes the register file enable/disable decryption operation. The read/write output data and perform the particular operation signal of data memory describes whether determined by the
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