TL431,A,BSeries, NCV431A

Programmable PrecisionReferences The TL431, A, B integrated circuits are three−terminal programmable shunt regulator diodes. These monolithic IC voltage http://onsemi.com references operate as a low temperature coefficient zener which is TO−92 (TO−226) programmable from Vref to 36 V with two external resistors. These LP SUFFIX devices exhibit a wide operating current range of 1.0 mA to 100 mA CASE 29 with a typical dynamic impedance of 0.22 W. The characteristics of these references make them excellent replacements for zener diodes in Pin 1. Reference many applications such as digital voltmeters, power supplies, and op 1 2 2. Anode amp circuitry. The 2.5 V reference makes it convenient to obtain a 3 3. Cathode stable reference from 5.0 V logic supplies, and since the TL431, A, B operates as a shunt regulator, it can be used as either a positive or negative voltage reference. PDIP−8 P SUFFIX CASE 626 Features 8 • Programmable Output Voltage to 36 V 1 • ± ° Micro8E Voltage Reference Tolerance: 0.4%, Typ @ 25 C (TL431B) DM SUFFIX • W 8 Low Dynamic Output Impedance, 0.22 Typical 1 CASE 846A • Sink Current Capability of 1.0 mA to 100 mA • Equivalent Full−Range Temperature Coefficient of 50 ppm/°C Cathode 1 8 Reference Typical • N/C 2 7 N/C Temperature Compensated for Operation over Full Rated Operating N/C 3 6 Anode Temperature Range N/C 4 5 N/C • Low Output Noise Voltage (Top • Pb−Free Packages are Available View) SOIC−8 8 D SUFFIX CASE 751 1

Cathode 1 8 Reference 2 7 Anode Anode 3 6 N/C 4 5 N/C

(TopView) This is an internally modified SOIC−8 package. Pins 2, 3, 6 and 7 are electrically common to the die attach flag. This internal lead frame modification increases power dissipation capability when appropriately mounted on a printed circuit board. This modified package conforms to all external dimensions of the standard SOIC−8 package.

ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.

DEVICE MARKING INFORMATION See general marking information in the device marking section on page 15 of this data sheet.

 Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: March, 2005 − Rev. 21 TL431/D TL431, A, B Series, NCV431A

Symbol Representative Schematic Diagram Component values are nominal Cathode (K) Cathode(K)

Reference (R) 800 800 Anode Reference (A) (R) 20pF

Representative Block Diagram 150 3.28k 4.0k Reference Cathode 20pF 10k 2.4k 7.2k (R) + (K)

− 1.0k 2.5Vref 800

Anode(A) Anode(A) This device contains 12 active transistors. MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.) Rating Symbol Value Unit

Cathode to Anode Voltage VKA 37 V

Cathode Current Range, Continuous IK −100 to +150 mA

Reference Input Current Range, Continuous Iref −0.05 to +10 mA

Operating Junction Temperature TJ 150 °C

Operating Ambient Temperature Range TA °C TL431I, TL431AI, TL431BI −40 to +85 TL431C, TL431AC, TL431BC 0 to +70 NCV431AI, TL431BV −40 to +125

Storage Temperature Range Tstg −65 to +150 °C

Total Power Dissipation @ TA = 25°C PD W Derate above 25°C Ambient Temperature D, LP Suffix Plastic Package 0.70 P Suffix Plastic Package 1.10 DM Suffix Plastic Package 0.52

Total Power Dissipation @ TC = 25°C PD W Derate above 25°C Case Temperature D, LP Suffix Plastic Package 1.5 P Suffix Plastic Package 3.0 NOTE: ESD data available upon request.

RECOMMENDED OPERATING CONDITIONS Condition Symbol Min Max Unit

Cathode to Anode Voltage VKA Vref 36 V

Cathode Current IK 1.0 100 mA

THERMAL CHARACTERISTICS D, LP Suffix P Suffix DM Suffix Characteristic Symbol Package Package Package Unit

Thermal Resistance, Junction−to−Ambient RqJA 178 114 240 °C/W

Thermal Resistance, Junction−to−Case RqJC 83 41 − °C/W

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ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.) TL431I TL431C

Characteristic Symbol Min Typ Max Min Typ Max Unit

Reference Input Voltage (Figure 1) Vref V VKA = Vref, IK = 10 mA TA = 25°C 2.44 2.495 2.55 2.44 2.495 2.55 TA = Tlow to Thigh (Note 1) 2.41 − 2.58 2.423 − 2.567

High Logic Level Supply Current from VCC ICCH 60 − 45 60 mA mA mA

Reference Input Voltage Deviation Over DVref − 7.0 30 − 3.0 17 mV Temperature Range (Figure 1, Notes 1, 2) VKA= Vref, IK = 10 mA Ratio of Change in Reference Input Voltage to Change DV mV/V ref in Cathode to Anode Voltage DV IK = 10 mA (Figure 2), KA DVKA = 10 V to Vref − −1.4 −2.7 − −1.4 −2.7 DVKA = 36 V to 10 V − −1.0 −2.0 − −1.0 −2.0

Reference Input Current (Figure 2) Iref mA IK = 10 mA, R1 = 10 k, R2 = ∞ TA = 25°C − 1.8 4.0 − 1.8 4.0 TA = Tlow to Thigh (Note 1) − − 6.5 − − 5.2

Reference Input Current Deviation Over DIref − 0.8 2.5 − 0.4 1.2 mA Temperature Range (Figure 2, Note 1, 4) IK = 10 mA, R1 = 10 k, R2 = ∞

Minimum Cathode Current For Regulation Imin − 0.5 1.0 − 0.5 1.0 mA VKA = Vref (Figure 1)

Off−State Cathode Current (Figure 3) Ioff − 20 1000 − 20 1000 nA VKA = 36 V, Vref = 0 V

Dynamic Impedance (Figure 1, Note 3) |ZKA| − 0.22 0.5 − 0.22 0.5 W VKA = Vref, DIK = 1.0 mA to 100 mA f ≤ 1.0 kHz

1. Tlow = −40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM; =0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM 2. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies.

Vrefmax DVref=Vrefmax −Vrefmin DTA=T2−T1 Vrefmin

T1 T2 AmbientTemperature

D V ǒ ref Ǔ 6 _ X10 V @25 C D V x106 ppm ref ref a V + + The average temperature coefficient of the reference input voltage, Vref is defined as: ref _C D T D T (V @25_C) A A ref

aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)

Example : DV + 8.0 mV and slope is positive, ref 0.008 x 106 V @25_C + 2.495 V, DT + 70_C a V + + 45.8 ppmń_C ref A ref 70 (2.495)

D V 3. The dynamic impedance Z is defined as: |Z | + KA. When the device is programmed with two external resistors, R1 and R2, KA KA D I K (refer to Figure 2) the total dynamic impedance of the circuit is defined as: |Z Ȁ| [ |Z | ǒ 1 ) R1 Ǔ KA KA R2

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ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.) TL431AI / NCV431AI TL431AC TL431BI / TL431BV

Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Unit

Reference InputIn ut Voltage (Figure 1) Vref V VKA = Vref, IK = 10 mA TA = 25°C 2472.47 22.495 495 2522.52 2472.47 22.495 495 2522.52 22.483 483 22.495 495 22.507 507 TA = Tlow totT Thigh 2442.44 − 2552.55 22.453 453 − 22.537 537 22.475 475 22.495 495 22.515 515

Reference Input Voltage Deviation Over DVref − 7.0 30 − 3.0 17 − 3.0 17 mV Temperature Range (Figure 1, Notes 4, 5) VKA= Vref, IK = 10 mA Ratio of Change in Reference Input Voltage to DV mV/V ref Change in Cathode to Anode Voltage DV IK = 10 mA (Figure 2), KA DVKA = 10 V to Vref − −1.4 −2.7 − −1.4 −2.7 − −1.4 −2.7 DVKA = 36 V to 10 V − −1.0 −2.0 − −1.0 −2.0 − −1.0 −2.0

Reference Input Current (Figure 2) Iref mA IK = 10 mA, R1 = 10 k, R2 = ∞ TA = 25°C − 1.8 4.0 − 1.8 4.0 − 1.1 2.0 TA = Tlow to Thigh (Note 4) − − 6.5 − − 5.2 − − 4.0

Reference Input Current Deviation Over DIref − 0.8 2.5 − 0.4 1.2 − 0.8 2.5 mA Temperature Range (Figure 2, Note 4) IK = 10 mA, R1 = 10 k, R2 = ∞

Minimum Cathode Current For Regulation Imin − 0.5 1.0 − 0.5 1.0 − 0.5 1.0 mA VKA = Vref (Figure 1)

Off−State Cathode Current (Figure 3) Ioff − 20 1000 − 20 1000 − 0.23 500 nA VKA = 36 V, Vref = 0 V

Dynamic Impedance (Figure 1, Note 6) |ZKA| − 0.22 0.5 − 0.22 0.5 − 0.14 0.3 W VKA = Vref, DIK = 1.0 mA to 100 mA f ≤ 1.0 kHz

4. Tlow = −40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM, TL431BIDM, NCV431AIDMR2, NCV431AIDR2 =0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM = +125°C TL431BV, NCV431AIDMR2, NCV431AIDR2 5. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies.

Vrefmax DVref=Vrefmax −Vrefmin DTA=T2−T1 Vrefmin

T1 T2 D V AmbientTemperature ǒ ref Ǔ 6 _ X10 V @25 C D V x106 ppm ref ref The average temperature coefficient of the reference input voltage, aV is defined as: V + + ref ref _C D T D T (V @25_C) A A ref

aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)

Example : DV + 8.0 mV and slope is positive, ref 0.008 x 106 V @25_C + 2.495 V, DT + 70_C a V + + 45.8 ppmń_C ref A ref 70 (2.495)

D V 6. The dynamic impedance Z is defined as |Z | + KA When the device is programmed with two external resistors, R1 and R2, (refer KA KA D I K to Figure 2) the total dynamic impedance of the circuit is defined as: |Z Ȁ| [ |Z | ǒ 1 ) R1 Ǔ KA KA R2 7. NCV431AIDMR2, NCV431AIDR2 Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and change control.

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Input VKA Input V Input VKA KA IK Ioff IK R1 Iref

Vref R2 V + V
ǒ
1 ) R1
Ǔ ) I
S
R1 KA ref R2 ref

Vref

Figure 1. Test Circuit for VKA = Vref Figure 2. Test Circuit for VKA > Vref Figure 3. Test Circuit for Ioff

150 800 VKA=Vref VKA=Vref ° TA=25°C TA=25 C

100 Input V µ 600 Input VKA IMin KA I IK K 50 400

0 200 ,CATHODECURRENT(mA) ,CATHODECURRENT( A)

K −50 I K 0 I

−100 −200 −2.0 −1.0 0 1.0 2.0 3.0 −1.0 0 1.0 2.0 3.0

VKA,CATHODEVOLTAGE(V) VKA,CATHODEVOLTAGE(V) Figure 4. Cathode Current versus Figure 5. Cathode Current versus Cathode Voltage Cathode Voltage

2600 3.0 Input VKA

2580 µ IK VKA=Vref VrefMax=2550mV 2.5 2560 Vref IK=10mA 2540 2.0 2520 V Typ=2495mV 2500 ref 1.5 2480 IK=10mA 2460 1.0 Input VKA 10k Iref IK 2440 V Min=2440mV ref 0.5 2420 ,REFERENCEINPUTCURRENT( A) ref ref I V2400 ,REFERENCEINPUTVOLTAGE(mV) 0 −55 −25 05025 75 100 125 −55 −25 0 25 50 75 100 125

TA,AMBIENTTEMPERATURE(°C) TA,AMBIENTTEMPERATURE(°C) Figure 6. Reference Input Voltage versus Figure 7. Reference Input Current versus Ambient Temperature Ambient Temperature

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0 1.0k

IK=10mA T =25°C A 100 −8.0

10 −16 V =36V Input VKA KA V =0V IK 1.0 ref R1 Input VKA Ioff −24 R2 Vref 0.1 ,REFERENCEINPUTVOLTAGE(mV) ref ,OFF−STATECATHODECURRENT(nA) V off ∆ −32 I 0.01 0 10 20 30 40 −55 −25 0 25 5075 100 125

VKA,CATHODEVOLTAGE(V) TA,AMBIENTTEMPERATURE(5C) Figure 8. Change in Reference Input Figure 9. Off−State Cathode Current Voltage versus Cathode Voltage versus Ambient Temperature

100 0.320 ° 1.0k TA=25 C D VKA=Vref

Output I =1.0mAto100mA Ω Ω K D I 0.300 IK=1.0mAto100mA 50 K f≤1.0kHz − + Output 10 GND 0.280 1.0
k IK 50 − 0.260 + GND

1.0 0.240 |,DYNAMICIMPEDANCE( ) |,DYNAMICIMPEDANCE( ) KA KA 0.220 |Z |Z

0.1 0.200 1.0k 10k 100k1.0M 10M −55 −25 0 25 5075 100 125

f,FREQUENCY(MHz) TA,AMBIENTTEMPERATURE(°C) Figure 10. Dynamic Impedance Figure 11. Dynamic Impedance versus Frequency versus Ambient Temperature

60 80 Output I 50 15
k K 9.0mF 230 60 40 8.25
k √ GND 30 40 VKA=Vref I =10mA 20 K TA=25°C Input Output 10 IK=10mA T =25°C 20 IK

A NOISEVOLTAGE(nV/ Hz) ,OPENLOOPVOLTAGEGAIN(dB) 0 VOL A −10 0 1.0k 10k 100k 1.0M 10M 10100 1.0k 10k 100k f,FREQUENCY(MHz) f,FREQUENCY(Hz)

Figure 12. Open−Loop Voltage Gain Figure 13. Spectral Noise Density versus Frequency

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140 T =25°C 3.0 A Input Unstable Programmed ° Area V (V) TA=25 C Monitor 120 KA C 220 Output A Vref Output B 5.0 2.0 Pulse 100 C 10 Generator 50 D 15 f=100kHz 80 1.0 GND 60 Stable Stable D 0 VOLTAGESWING(V) 40 B B 5.0

Input ,CATHODECURRENT(mA) 20 A A K

0 I 0 04.0 8.0 12 16 20 1.0nF10nF 100nF 1.0mF 10mF 100mF m t,TIME( s) CL,LOADCAPACITANCE Figure 14. Pulse Response Figure 15. Stability Boundary Conditions

150 150

I I K K 10k V+ V+ CL CL

Figure 16. Test Circuit For Curve A Figure 17. Test Circuit For Curves B, C, And D of Stability Boundary Conditions of Stability Boundary Conditions

TYPICAL APPLICATIONS

V+ V V+ Vout out

R1 R1

R2 R2

V +
ǒ1 ) R1Ǔ
V out R2 ref V +
ǒ1 ) R1Ǔ
V out R2 ref Figure 18. Shunt Regulator Figure 19. High Current Shunt Regulator

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V+ Vout MC7805 R1 V+In Out Vout Common R1

R2 R2

V +
ǒ1 ) R1Ǔ
V out R2 ref V +
ǒ1 ) R1Ǔ
V out ref R2 V
min + V ) V out ref be V
min + V ) 5.0V out ref Figure 20. Output Control for a Figure 21. Series Pass Regulator Three−Terminal Fixed Regulator

R CL V+ Isink V+ Iout

V I + ref Sink R S V I + ref out R CL RS

Figure 22. Constant Current Source Figure 23. Constant Current Sink

V+ Vout V+ Vout R1 R1

R2 R2

V +
ǒ1 ) R1Ǔ
V out(trip) R2 ref V +
ǒ1 ) R1Ǔ
V out(trip) R2 ref Figure 24. TRIAC Crowbar Figure 25. SRC Crowbar

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V+ Vout V+ l R1 R3

Vout

Vin R2 R4

Vin Vout L.E.D.indicatoris‘on’whenV+isbetweenthe Vth=Vref < V V+ upperandlowerlimits. ref > Vref ≈ 2.0 V Lower
Limit +
ǒ1 ) R1Ǔ
V R2 ref

Upper
Limit +
ǒ1 ) R3Ǔ
V R4 ref Figure 26. Voltage Monitor Figure 27. Single−Supply Comparator with Temperature−Compensated Threshold

25V 38V 1N5305 2.0mA 330 Tl=330to8.0W

5.0k 50k 500k 5.0M 10k T I + 1% 1% 1% 1% Calibrate 470mF W 8.0W 10k 360k V 100kW W 25V W V 1.0M 1.0mF 1.0k V − V LM11 * Range Vout Volume + 0.05mF *Thermalloy 47k −5.0V Tone R *THM6024 X W 56k 10k 25k R + V
D


Range *Heatsinkon x out V *LPPackage

Figure 28. Linear Ohmmeter Figure 29. Simple 400 mW Phono Amplifier

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150mH@2.0A V =10Vto20V in TIP115 Vout=5.0V Iout=1.0A 1.0k 4.7k 4.7k 1N5823

MPSA20 0.01mF 100k + m 2200 F + 4.7k 470mF

0.1mF 2.2k 10 51k

Figure 30. High Efficiency Step−Down Switching Converter

Test Conditions Results

Line Regulation Vin = 10 V to 20 V, Io = 1.0 A 53 mV (1.1%)

Load Regulation Vin = 15 V, Io = 0 A to 1.0 A 25 mV (0.5%)

Output Ripple Vin = 10 V, Io = 1.0 A 50 mVpp P.A.R.D.

Output Ripple Vin = 20 V, Io = 1.0 A 100 mVpp P.A.R.D.

Efficiency Vin = 15 V, Io = 1.0 A 82%

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APPLICATIONS INFORMATION

The TL431 is a programmable precision reference which P2 + 1 + 1 + 60 kHz 2p R C 2p * 10 M * 0.265 pF is used in a variety of ways. It serves as a reference voltage P2 P2 in circuits where a non−standard reference voltage is needed. Other uses include feedback control for driving an Z1 + 1 + 1 + 500 kHz 2p R C 2p *15.9k*20pF optocoupler in power supplies, voltage monitor, constant Z1 P1 current source, constant current sink and series pass regulator. In each of these applications, it is critical to In addition, there is an external circuit pole defined by the maintain stability of the device at various operating currents load: and load capacitances. In some cases the circuit designer can estimate the stabilization capacitance from the stability P + 1 L 2p R C boundary conditions curve provided in Figure 15. However, L L these typical curves only provide stability information at Also, the transfer dc voltage gain of the TL431 is: specific cathode voltages and at a specific load condition. Additional information is needed to determine the G + G R GoR capacitance needed to optimize phase margin or allow for M GM L process variation. Example 1: A simplified model of the TL431 is shown in Figure 31. I +10 mA, R + 230 W,C + 0. Define the transfer gain. When tested for stability boundaries, the load resistance is C L L 150 W. The model reference input consists of an input The DC gain is: transistor and a dc emitter resistance connected to the device anode. A dependent current source, Gm, develops a current G + G R GoR + whose amplitude is determined by the difference between M GM L the 1.78 V internal reference voltage source and the input (2.138)(1.0 M)(1.25 m)(230) + 615 + 56 dB transistor emitter voltage. A portion of Gm flows through compensation capacitance, C . The voltage across C + 8.25 k + + P2 P2 Loop gain G ) 218 47 dB drives the output dependent current source, Go, which is 8.25 k 15 k connected across the device cathode and anode. The resulting transfer function Bode plot is shown in Figure 32. The asymptotic plot may be expressed as the Model component values are: following equation: Vref = 1.78 V Gm = 0.3 + 2.7 exp (−IC/26 mA) jf ǒ1 ) Ǔ where IC is the device cathode current and Gm is in mhos 500 kHz Av + 615 Go = 1.25 (V 2) mmhos. jf jf cp ǒ1 ) Ǔǒ1 ) Ǔ 8.0 kHz 60 kHz Resistor and capacitor typical values are shown on the The Bode plot shows a unity gain crossover frequency of ± ± model. Process tolerances are 20% for resistors, 10% for approximately 600 kHz. The phase margin, calculated from ± capacitors, and 40% for transconductances. the equation, would be 55.9 degrees. This model matches the An examination of the device model reveals the location Open−Loop Bode Plot of Figure 12. The total loop would of circuit poles and zeroes: have a unity gain frequency of about 300 kHz with a phase margin of about 44 degrees. P1 + 1 + 1 + 7.96 kHz 2p R C 2p * 1.0 M * 20 pF GM P1

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VCC

RL

C Input L 3 15k Cathode 9.0mF R Go P2 m Ref 10M 1.0 mho Vref 1 1.78 V GM CP1 + C Rref R 20pF P2 GM 0.265pF 500k − 16 1.0M RZ1 8.25k 15.9k

Anode 2

Figure 31. Simplified TL431 Device Model

TL431OPEN−LOOPVOLTAGEGAINVERSUSFREQUENCY Note that the transfer function now has an extra pole 60 formed by the load capacitance and load resistance. 50 Note that the crossover frequency in this case is about 250 kHz, having a phase margin of about −46 degrees. 40 Therefore, instability of this circuit is likely. 30 TL431OPEN−LOOPBODEPLOTWITHLOADCAP 20 80 10

0 60

−10 Av,OPEN−LOOPVOLTAGEGAIN(dB) 40 −20 101 102 103 104 105 106 107 f,FREQUENCY(Hz) 20 Figure 32. Example 1 Circuit Open Loop Gain Plot

Example 2. Av,OPEN−LOOPGAIN(dB) 0 IC = 7.5 mA, RL = 2.2 kW, CL = 0.01 mF. Cathode tied to reference input pin. An examination of the data sheet −20 stability boundary curve (Figure 15) shows that this value of 101 102 103 104 105 106 load capacitance and cathode current is on the boundary. f,FREQUENCY(Hz) Define the transfer gain. Figure 33. Example 2 Circuit Open Loop Gain Plot The DC gain is: With three poles, this system is unstable. The only hope G + G R GoR + for stabilizing this circuit is to add a zero. However, that can M GM L only be done by adding a series resistance to the output (2.323)(1.0 M)(1.25 m)(2200) + 6389 + 76 dB capacitance, which will reduce its effectiveness as a noise The resulting open loop Bode plot is shown in Figure 33. filter. Therefore, practically, in reference voltage The asymptotic plot may be expressed as the following applications, the best solution appears to be to use a smaller equation: value of capacitance in low noise applications or a very jf large value to provide noise filtering and a dominant pole ǒ1 ) Ǔ 500 kHz rolloff of the system. Av + 615 jf jf jf ǒ1 ) Ǔǒ1 ) Ǔǒ1 ) Ǔ 8.0 kHz 60 kHz 7.2 kHz

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ORDERING INFORMATION Device Operating Temperature Range Package Code Shipping Information† Tolerance TL431ACD SOIC−8 1.0% TL431ACDG SOIC−8 1.0% (Pb−Free) TL431BCD SOIC−8 98 Units / Rail 0.4% TL431BCDG SOIC−8 0.4% (Pb−Free) TL431CD 2.2% SOIC−8SOIC−8 TL431ACDR2 1.0% TL431ACDR2G SOIC−8 1.0% (Pb−Free) TL431BCDR2 SOIC−8 0.4% TL431BCDR2G SOIC−8 2500 Units / Tape & Reel 0.4% (Pb−Free) TL431CDR2 SOIC−8 2.2% TL431CDR2G SOIC−8 2.2% (Pb−Free) TL431ACDMR2 1.0% Micro8Micro8 TL431BCDMR2 0.4% TL431BCDMR2G Micro8 0.4% (Pb−Free) 4000 Units / Tape & Reel TL431CDMR2 Micro8 2.2% TL431CDMR2G Micro8 2.2% (Pb−Free) TL431ACP 1.0% TL431BCP PDIP−8 0.4% 0°Cto70C to 70°C TL431CP 50 Units / Rail 2.2% TL431CPG PDIP−8 2.2% (Pb−Free) TL431ACLP TO−92 (TO−226) 1.0% TL431ACLPG TO−92 (TO−226) 1.0% (Pb−Free) TL431BCLP TO−92 (TO−226) 0.4% TL431BCLPG TO−92 (TO−226) 2000 Units / Bag 0.4% (Pb−Free) TL431CLP TO−92 (TO−226) 2.2% TL431CLPG TO−92 (TO−226) 2.2% (Pb−Free) TL431ACLPRA TO−92 (TO−226) 1.0% TL431ACLPRAG TO−92 (TO−226) 1.0% (Pb−Free) TL431BCLPRA TO−92 (TO−226) 0.4% TL431BCLPRAG TO−92 (TO−226) 0.4% (Pb−Free) TL431CLPRA TO−92 (TO−226) 2000 Units / Tape & Reel 2.2% TL431CLPRAG TO−92 (TO−226) 2.2% (Pb−Free) TL431ACLPRE TO−92 (TO−226) 1.0% TL431ACLPREG TO−92 (TO−226) 1.0% (Pb−Free) TL431BCLPRE TO−92 (TO−226) 0.4% †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

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ORDERING INFORMATION Device Operating Temperature Range Package Code Shipping Information† Tolerance TL431BCLPREG TO−92 (TO−226) 2000 Units / Tape & Reel 0.4% (Pb−Free) TL431ACLPRP TO−92 (TO−226) 1.0% TL431ACLPRPG TO−92 (TO−226) 1.0% (Pb−Free) TL431BCLPRM 0°C to 70°C TO−92 (TO−226) 0.4% TL431BCLPRMG TO−92 (TO−226) 2000 Units / Fan−Fold 0.4% (Pb−Free) TL431CLPRP TO−92 (TO−226) 2.2% TL431CLPRPG TO−92 (TO−226) 2.2% (Pb−Free) TL431AID SOIC−8 1.0% TL431AIDG SOIC−8 1.0% (Pb−Free) TL431BID SOIC−8 0.4% TL431BIDG SOIC−8 98 Units / Rail 0.4% (Pb−Free) TL431ID SOIC−8 2.2% TL431IDG SOIC−8 2.2% (Pb−Free) TL431AIDR2 SOIC−8 1.0% TL431AIDR2G SOIC−8 1.0% (Pb−Free) TL431BIDR2 SOIC−8 0.4% TL431BIDR2G SOIC−8 2500 Units / Tape & Reel 0.4% (Pb−Free) TL431IDR2 SOIC−8 2.2% TL431IDR2G SOIC−8 2.2% (Pb−Free) TL431AIDMR2 1.0% Micro8Micro8 TL431BIDMR2 0.4% −40°Cto85C to 85°C TL431BIDMR2G Micro8 0.4% (Pb−Free) 4000 Units / Tape & Reel TL431IDMR2 Micro8 2.2% TL431IDMR2G Micro8 2.2% (Pb−Free) TL431AIP PDIP−8 1.0% TL431AIPG PDIP−8 1.0% (Pb−Free) 50 Units / Rail TL431BIP 0.4% PDIPPDIP−8−8 TL431IP 2.2% TL431AILP 1.0% TO−92TO−92 (TO (TO−226)−226) TL431BILP 0.4% TL431BILPG TO−92 (TO−226) 0.4% (Pb−Free) 2000 Units / Box TL431ILP TO−92 (TO−226) 2.2% TL431ILPG TO−92 (TO−226) 2.2% (Pb−Free) TL431AILPRA TO−92 (TO−226) 1.0% TL431AILPRAG TO−92 (TO−226) 2000 Units / Tape & Reel 1.0% (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

http://onsemi.com 14 TL431, A, B Series, NCV431A

ORDERING INFORMATION Device Operating Temperature Range Package Code Shipping Information† Tolerance TL431BILPRA TO−92 (TO−226) 0.4% TL431BILPRAG TO−92 (TO−226) 0.4% (Pb−Free) 2000 UnitsUnits / TaTapepe & R Reeleel TL431ILPRA TO−92 (TO−226) 2.2% TL431ILPRAG −40°C to 85°C TO−92 (TO−226) 2.2% (Pb−Free) TL431AILPRM 1.0% TL431AILPRP TO−92 ()(TO−226) 2000 Units / Ammo Pack 1.0% TL431ILPRP 2.2% TL431BVD SOIC−8 0.4% 98 UnitsUnits / RailRail TL431BVDR2 SOIC−8 0.4% TL431BVDMR2 Micro8 4000 Units / Tape & Reel 0.4% −4040°CCto125 to 125°C TL431BVLP TO−92 (TO−226) 2000 Units / Box 0.4%

TL431BVP PDIP−8 50 Units / Rail 0.4% NCV431AIDMR2 Micro8 4000 Units / Tape & Reel 1% NCV431AIDR2 SOIC−8 2500 Units / Tape & Reel 1% †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

MARKING DIAGRAMS

SOIC−8 Micro8 PDIP−8 TO−92 (TO−226) D SUFFIX CASE 846A CASE 626 CASE 29 CASE 751 8 8 8 xx xx xx xx ALYW AYW AWL YYWW 1 1 1

123

xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

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PACKAGE DIMENSIONS

TO−92 (TO−226) LP SUFFIX NOTES: A B 1. DIMENSIONINGANDTOLERANCINGPERANSI PLASTIC PACKAGE Y14.5M,1982. CASE 29−11 2. CONTROLLINGDIMENSION:INCH. 3. CONTOUROFPACKAGEBEYONDDIMENSIONR R ISSUE AL ISUNCONTROLLED. 4. LEADDIMENSIONISUNCONTROLLEDINPAND P BEYONDDIMENSIONKMINIMUM. L SEATING INCHES MILLIMETERS PLANE K DIM MIN MAX MIN MAX A 0.175 0.205 4.45 5.20 B 0.170 0.210 4.32 5.33 C 0.125 0.165 3.18 4.19 D 0.016 0.021 0.407 0.533 XX D G 0.045 0.055 1.15 1.39 G H 0.095 0.105 2.42 2.66 J 0.015 0.020 0.39 0.50 H J K 0.500 −−− 12.70 −−− L V 0.250 −−− 6.35 −−− C N 0.080 0.105 2.04 2.66 SECTION X−X P −−− 0.100 −−− 2.54 1 R 0.115 −−− 2.93 −−− N V 0.135 −−− 3.43 −−− N

PDIP−8 P SUFFIX NOTES: PLASTIC PACKAGE 1. DIMENSIONLTOCENTEROFLEADWHEN FORMEDPARALLEL. 8 5 CASE 626−05 2. PACKAGECONTOUROPTIONAL(ROUNDOR ISSUE L SQUARECORNERS). 3. DIMENSIONINGANDTOLERANCINGPERANSI −B− Y14.5M,1982. 14 MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.40 10.16 0.370 0.400 B F 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 D 0.38 0.51 0.015 0.020 NOTE 2 −A− F 1.02 1.78 0.040 0.070 L G 2.54BSC 0.100BSC H 0.76 1.27 0.030 0.050 J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 C L 7.62BSC 0.300BSC M −−− 10__ −−− 10 N 0.76 1.01 0.030 0.040 −T− J SEATING N PLANE M D K H G 0.13(0.005)M T A M B M

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PACKAGE DIMENSIONS

Micro8 DM SUFFIX PLASTIC PACKAGE CASE 846A−02 ISSUE F NOTES: −A− 1. DIMENSIONINGANDTOLERANCINGPERANSI Y14.5M,1982. 2. CONTROLLINGDIMENSION:MILLIMETER. 3. DIMENSIONADOESNOTINCLUDEMOLDFLASH, PROTRUSIONSORGATEBURRS.MOLDFLASH, −B− PROTRUSIONSORGATEBURRSSHALLNOT K EXCEED0.15(0.006)PERSIDE. 4. DIMENSIONBDOESNOTINCLUDEINTERLEAD FLASHORPROTRUSION.INTERLEADFLASHOR PROTRUSIONSHALLNOTEXCEED0.25(0.010) PERSIDE. 5. 846A−01OBSOLETE,NEWSTANDARD846A−02. PIN 1 ID G MILLIMETERS INCHES D 8 PL DIM MIN MAX MIN MAX 0.08(0.003)M T B S A S A 2.90 3.10 0.114 0.122 B 2.90 3.10 0.114 0.122 C −−− 1.10 −−− 0.043 D 0.25 0.40 0.010 0.016 SEATING G 0.65BSC 0.026BSC −T− PLANE H 0.05 0.15 0.002 0.006 C J 0.13 0.23 0.005 0.009 0.038(0.0015) K 4.75 5.05 0.187 0.199 L 0.40 0.70 0.016 0.028 L H J

SOLDERING FOOTPRINT*

1.04 0.38 8X 8X 0.041 0.015

3.20 4.24 5.28 0.126 0.167 0.208

0.65 6X mm SCALE 8:1 ǒ Ǔ 0.0256 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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SOIC−8 D SUFFIX PLASTIC PACKAGE CASE 751−07 ISSUE AE NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER A ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 8 5 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25(0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR 1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL 4 IN EXCESS OF THE D DIMENSION AT K MAXIMUM MATERIAL CONDITION. −Y− 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX C N X 45_ A 4.80 5.00 0.189 0.197 SEATING B 3.80 4.00 0.150 0.157 PLANE C 1.35 1.75 0.053 0.069 −Z− D 0.33 0.51 0.013 0.020 0.10(0.004) G 1.27 BSC 0.050 BSC M H 0.10 0.25 0.004 0.010 H D J J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 ____ 8 0 8 0.25(0.010) M Z Y S X S N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52 0.060

7.0 4.0 0.275 0.155

0.6 1.270 0.024 0.050

mm SCALE 6:1 ǒ Ǔ inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

Micro8 is a trademark of International Rectifier.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: http://onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Order Literature: http://www.onsemi.com/litorder Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 For additional information, please contact your Email: [email protected] Phone: 81−3−5773−3850 local Sales Representative. http://onsemi.com TL431/D 18