Appendix 1 HOW CCD IMAGERS ARE MADE
Total Page：16
File Type：pdf, Size：1020Kb
Appendix 1 HOW CCD IMAGERS ARE MADE This appendix gives an overview of a possible route which can be followed to make a CCD imager. The fabrication technology is purely an example and the vehicle used to describe the various steps is also a hypothetical device. CCD processes proceed from complicated, MOS-based technologies and processes. The complexity is a result of the relatively large number of technological steps and the consecutive relatively large throughput time in the production facilities. Fabrication involves several implantatron steps and the deposition of several layers of, for instance, silicon oxide, silicon nitride, polycrystalline silicon and at least one layer of metallization. If the imager has to be used in color applications, color filters layers have also to be added. Microlenses are another possible option. The minimum number of masks needed in the production trajectory is about 10 to 12, but, for very highly sophisticated devices (such as HDTV imagers with color filters), as many as 25 masking steps are no longer an exception. Throughput times for CCD imagers processes range from a fortnight to several weeks. In other words, there are probably as many different fabrication processes as there are CCD designs because the technology is quite often optimized with the main application and the device architecture in mind. The architecture on which this overview is based is that of a full-frame device highly suited to describing a minimal route. Figure A1 .1 shows a top view of the device under study. The full-frame imager has a light-sensitive part, a horizontal output register and an output amplifier connected to the floating diffusion. All these regions are designated in the illustration. The cross section of interest is indicated by the dotted line A’-A. Starting from point A’, the cross section passes first through the light-sensitive area, then through the horizontal output register and floating diffusion, and finally through the reset transistor. In the remaining part of this appendix, the individual technological steps of the fabrication process will be described, successively and their consequences for the CCD itself will be illustrated along the cross section A’-A. Some characteristics of the full-frame device under study : - the technology is based on a triple-polysilicon gate process; - a single level of metal is used, both for the interconnects and for the light shield; - vertical antiblooming has to be catered for by a single p-well implant; - CCD transport has to take place in a buried CCD channel; 318 APPENDIX 1 FIGURE A1.1. Illustration of the full-frame imager which is used as the technology vehicle to describe the fabrication process of a charge-coupled device. -the CCD has to be capable of making color images by color separation on-chip with complementary colors; - the light-sensitive array has be provided with microlenses (this specification item is only for the sake of completeness because, as will be explained later, it has only theoretical value). Figure A1 .2 shows the codings of the various regions used to build up the CCD imager. These codings will be retained in the remaining part of this section. The following are some general semiconductor fabrication techniques which are also widely used in the CCD fabrication process are : - lithography : photoresist is applied to the silicon wafers using spin-on deposition methods. After a short curing cycle the photoresist is exposed to UV light through a mask and subsequently developed. Positive photoresist will remain in the nonexposed areas of the wafer after developing and will disappear from the exposed areas during the developing process; - implantation : a well-defined number of ions are implanted using a well-defined amount of implantation energy; HOW CCD IMAGERS ARE MADE 319 FIGURE A1.2. Coding of the various regions of the CCD. - etching techniques : material can be removed from the wafer by wet chemical etching (isotropic etch) or by dry etching, which can be a combination of chemical and physical removal of the material (isotropic or anisotropic); - deposition techniques : several methods exist to provide the wafers with a uniform coating of thin films : spin-on deposition, sputtering, low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, and evaporation; - annealing steps : heating the wafers to a well-defined temperature in a conditioned atmosphere (inert, oxidizing, reducing) for a well-defined time. Any hypothetical full-frame imager can be fabricated using a more or less complex combination of the above techniques and a complete set of masks. 320 APPENDIX 1 A1 .1. Substrate preparation To achieve "perfect" CCD imagers, the most important requirement is to start with "perfect" silicon wafers. Any impurity or crystal defect in the wafer which can interact with the active region in which the CCD is made, can cause pixel defects or dark-current non- uniformities. Another very tight parameter of the wafer specification is the concentration and uniformity of the doping. To meet the first condition for defect-free active regions, the wafers undergo a series of very closely controlled annealing procedures before the actual processing starts. The annealing processes can in some cases be carried out on the vendor’s premisses. The aim of these steps is twofold : first, to make the top layer of the wafer free from oxygen, thus creating the so-called denuded zone and, second, to create oxygen precipitates at the center of the wafer. This renders the active layer of the wafer free from impurities because the oxygen precipitates at the center of the wafer attract and getter any contaminant. The starting wafer material may be of the n+ type with a 10 µm thick epitaxial n- layer grown on it. The latter process is characterized by excellent control of the doping concentration and uniformity. When the wafers enter the clean room, they are coded, cleaned, and thermally oxidized. The result at this point is shown in Figure A1.3 : the n-type substrate with a thin thermal silicon oxide layer on both sides of the wafer. FIGURE A1.3. Preparation of the substrate before starting the first masking step. HOW CCD IMAGERS ARE MADE 321 A1.2. Implantation of the p well In the case of vertical antiblooming, definition of the p well is quite crucial, especially in the light-sensitive part of the device. As explained in section 6.3.3, the doping profile of the p well should be more or less sinusoidal shaped to create a saddle point in the center of the pixel. The exact location in depth of this saddle point defines the antiblooming effect. To achieve the desired doping profile, the p well is not uniformly implanted in the image section but into a striped pattern in which the stripes are parallel to the CCD channels and the direction of charge transfer. These stripes are defined in the photoresist which is spin- coated and processed prior to the implantation. The photoresist is used locally as a masking step against boron ions. Outside the light-sensitive areas, where anti-blooming is not concerned, the p well is uniformly implanted. The situation at this point is shown in Figure A1.4 : the pattern in the photoresist is chosen such that the implantation through the holes (or stripes) in the imaging section can result in the sinusoidal doping profile. The energy and the dose of the implanted boron ions are both low : less than 100 keV and around 10¹²/cm², respectively. FIGURE A1.4. Implantation of the boron ions to define the p well. 322 APPENDIX 1 A1.3. Drive-in of the p well After the implantation of the p well the wafers are annealed to diffuse the implanted boor ions deeper into the silicon. Outdiffusion of the ions takes place not only in depth but also laterally. In general, the length of the lateral diffusion (also called underdiffusion) is about 75 % of the depth of the in-depth outdiffusion. Note that this temperature step is for sure not the last one in the overall fabrication process of charge-coupled devices. The p well will outdiffuse even further during the temperature steps which still have to follow this annealing step. During determination of the flow chart (= the sequence of the various fabrication steps which follow in the clean room), the technologist has to take into account the temperature budget along the entire fabrication route to arrive the ultimate definition of the p well. The annealing step at this point in the flow chart is only part of the temperature budget as a whole, although this phase of the process takes place at very high temperatures (e.g. > 1100°C) and over a very long time (e.g. 10 hours). The result at this point is shown in Figure A1 .5 : the photoresist has been removed, and the wafers cleaned and stored at higher temperatures to drive in the implanted boron ions. Note that the implanted stripes in the image section have already diffused so far sideways that a more or less continuous p well has also been generated in the image section. FIGURE A 1.5. Situation after the drive-in anneal of the p well. HOW CCD IMAGERS ARE MADE 323 A1.4. Implantation of the CCD channel The second masking step is concerned with implantation of the CCD channels. As will be shown in the next masking stage, the actual definition of the channels is a combined effect of this implant and the next one. implantation is done through a single opening in the photoresist : the CCD channels in the imaging area, the horizontal output register, and even the reset transistor, all form part of a single implanted channel area.