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Systemverilog Reference SystemVerilog Reference Product Version 9.2 July 2010 © 1995-2010 Cadence Design Systems, Inc. All rights reserved worldwide. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. 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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the University of Colorado nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SystemVerilog Reference Contents 1 Overview of SystemVerilog . 15 Availability of Constructs within Simulators . 15 SystemVerilog in Simulation . 15 SystemVerilog VPI Extensions . 15 SystemVerilog Assertions . 16 SystemVerilog Coverage . 16 SystemVerilog with AMS . 16 SystemVerilog Examples . 16 Language Support . 17 Getting Help . 17 About Online Help . 17 Getting Help on Commands to Run Tools . 19 Getting Help on Tool Messages . 19 Other Documentation . 20 Customer Support . 20 2 Compiling SystemVerilog Constructs . 23 Using ncvlog . 23 Using the irun Utility . 23 SystemVerilog and the PLI tf_nodeinfo() Interface . 24 3 List of Supported Constructs . 25 4 Convenience Enhancements. 31 Literal Value Assignments . 31 July 2010 3 Product Version 9.2 SystemVerilog Reference Matching End Names . 31 Time Unit and Time Precision . 33 .name Implicit Port Connection . 34 Dot Star (.*) Implicit Port Connection . 35 5 Data Types. 37 Data Types Overview . 37 Overview of Verilog Data Types . 38 Primitive Data Types . 38 User-Defined Data Types . 39 logic Data Type . 40 bit Data Type . 41 byte, shortint, int, and longint Data Types . 42 Chandle Data Type . 43 Strings . 43 String Operators . 44 String Methods . 45 Strings and System Tasks . 48 Using Strings with Classes . 48 Using Strings with Packages . 49 Using Strings within begin...end Blocks . 50 Declaring a Fixed Array of Strings . 50 Declaring Arrays and Queues of Strings . 51 Using Elements of a Dynamic Array of Strings . 52 Using Strings as Parameters and localparams . 53 Using Out-of-Module References to Strings . 54 Limitations on Strings . 55 typedef Declaration . 56 Limitations on Typedefs . 56 Creating a New Data Type Definition . 57 Handling Data Type Visibility . 59 enum Data Type . 60 Limitations on Enumerations . 61 Declaring an Enumeration . 62 July 2010 4 Product Version 9.2 SystemVerilog Reference Specifying Enumeration Constants . 63 Treating Enumeration Objects as Bit Vectors . 64 Enumeration Type Checking . 65 Enumeration Type Methods . ..
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