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SystemVerilog Reference Contents 1 Overview of SystemVerilog . 15 Availability of Constructs within Simulators . 15 SystemVerilog in Simulation . 15 SystemVerilog VPI Extensions . 15 SystemVerilog Assertions . 16 SystemVerilog Coverage . 16 SystemVerilog with AMS . 16 SystemVerilog Examples . 16 Language Support . 17 Getting Help . 17 About Online Help . 17 Getting Help on Commands to Run Tools . 19 Getting Help on Tool Messages . 19 Other Documentation . 20 Customer Support . 20 2 Compiling SystemVerilog Constructs . 23 Using ncvlog . 23 Using the irun Utility . 23 SystemVerilog and the PLI tf_nodeinfo() Interface . 24 3 List of Supported Constructs . 25 4 Convenience Enhancements. 31 Literal Value Assignments . 31 July 2010 3 Product Version 9.2 SystemVerilog Reference Matching End Names . 31 Time Unit and Time Precision . 33 .name Implicit Port Connection . 34 Dot Star (.*) Implicit Port Connection . 35 5 Data Types. 37 Data Types Overview . 37 Overview of Verilog Data Types . 38 Primitive Data Types . 38 User-Defined Data Types . 39 logic Data Type . 40 bit Data Type . 41 byte, shortint, int, and longint Data Types . 42 Chandle Data Type . 43 Strings . 43 String Operators . 44 String Methods . 45 Strings and System Tasks . 48 Using Strings with Classes . 48 Using Strings with Packages . 49 Using Strings within begin...end Blocks . 50 Declaring a Fixed Array of Strings . 50 Declaring Arrays and Queues of Strings . 51 Using Elements of a Dynamic Array of Strings . 52 Using Strings as Parameters and localparams . 53 Using Out-of-Module References to Strings . 54 Limitations on Strings . 55 typedef Declaration . 56 Limitations on Typedefs . 56 Creating a New Data Type Definition . 57 Handling Data Type Visibility . 59 enum Data Type . 60 Limitations on Enumerations . 61 Declaring an Enumeration . 62 July 2010 4 Product Version 9.2 SystemVerilog Reference Specifying Enumeration Constants . 63 Treating Enumeration Objects as Bit Vectors . 64 Enumeration Type Checking . 65 Enumeration Type Methods . ..