Ltc3225/Ltc3225-1

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LTC3225/LTC3225-1 150mA Supercapacitor Charger FEATURES DESCRIPTION n Low Noise Constant Frequency Charging of Two The LTC®3225/LTC3225-1 are programmable supercapaci- Series Supercapacitors tor chargers designed to charge two supercapacitors in n Automatic Cell Balancing Prevents Capacitor series to a selectable ﬁ xed output voltage (4.8V/5.3V for Overvoltage During Charging the LTC3225 and 4V/4.5V for the LTC3225-1) from input n Programmable Charge Current (Up to 150mA) supplies as low as 2.8V to 5.5V. Automatic cell balancing n Selectable 2.4V or 2.65V Regulation per Cell prevents overvoltage damage to either supercapacitor. No (LTC3225) balancing resistors are required. n Selectable 2V or 2.25V Regulation per Cell Low input noise, low quiescent current and low external (LTC3225-1) parts count (one ﬂ ying capacitor, one bypass capacitor at n Automatic Recharge V and one programming resistor) make the LTC3225/ n I = 20μA in Standby Mode IN VIN LTC3225-1 ideally suited for small battery-powered n I < 1μA When Input Supply is Removed COUT applications. n No Inductors n Tiny Application Circuit (2mm × 3mm DFN Package, Charge current level is programmed with an external All Components <1mm High) resistor. When the input supply is removed, the LTC3225/ LTC3225-1 automatically enter a low current state, drawing APPLICATIONS less than 1μA from the supercapacitors. The LTC3225/LTC3225-1 are available in a 10-lead 2mm n Current Limited Applications with High Peak Power × 3mm DFN package. Loads (LED Flash, PCMCIA Tx Bursts, HDD Bursts, L, LT, LTC and LTM are registered trademarks and ThinSOT is a trademark of Linear GPRS/GSM Transmitter) Technology Corporation. All other trademarks are the property of their respective owners. n Backup Supplies

TYPICAL APPLICATION Charging Proﬁ le with 30% Mismatch in Output Capacitance, CTOP < CBOT

VOUT VIN SHDN VIN COUT 4.8V/5.3V (LTC3225) 2.8V/3V TO 5.5V 5V/DIV 2.2μF 0.6F 4V/4.5V (LTC3225-1) + C LTC3225 CX 1μF LTC3225-1 0.6F IVIN 300mA/DIV C– GND 100k

ON/OFF SHDN PGOOD VCOUT 2V/DIV

OUTPUT VSEL PROGRAMMING PROG 3225 TA01a VTOP-VBOT 200mV/DIV 12k LTC3225 5 SEC/DIV 3225 TA01b VSEL = VIN RPROG = 12k CTOP = 1.1F CBOT = 1.43F CTOP INITIAL VOLTAGE = 0V CBOT INITIAL VOLTAGE = 0V

3225fb 1 LTC3225/LTC3225-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1)

VIN, COUT to GND ...... –0.3V to 6V TOP VIEW

SHDN, VSEL ...... –0.3V to VIN + 0.3V + C 1 10 COUT C Short-Circuit Duration ...... Indeﬁ nite – OUT C 2 9 VIN IVIN Continuous (Note 2) ...... 350mA CX 3 11 8 GND IOUT Continuous (Note 2) ...... 175mA SHDN 4 7 PROG Operating Temperature Range (Note 3).... –40°C to 85°C PGOOD 5 6 VSEL

Storage Temperature Range ...... –65°C to 125°C DDB PACKAGE 10-LEAD (3mm s 2mm) PLASTIC DFN

TJMAX = 125°C, θJA = 76°C/W EXPOSED PAD (PIN 11) MUST BE SOLDERED TO LOW IMPEDANCE GND PLANE (PIN 8) ON PCB

ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3225EDDB#TRMPBF LTC3225EDDB#TRPBF LCYR 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC3225EDDB-1#TRMPBF LTC3225EDDB-1#TRPBF LFFS 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C TRM = 500 pieces. Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. Consult LTC Marketing for information on lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, CIN = 2.2μF, CFLY = 1μF, unless otherwise specifi ed (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LTC3225 l VIN-UVLO Input Supply Undervoltage Lockout VSEL = VIN 2.65 2.75 2.85 V l High-to-Low Threshold VSEL = 0 2.4 2.5 2.6 V

VIN-UVLO-HYS Input Supply Undervoltage Lockout VSEL = VIN 150 mV Hysteresis VSEL = 0 140 mV l VIN Input Voltage Range VSEL = VIN 3 5.5 V l VSEL = 0V 2.8 5.5 V l VCOUT Charge Termination Voltage VSEL = VIN 5.2 5.3 5.4 V l Sleep Mode Threshold (Rising Edge) VSEL = 0V 4.7 4.8 4.9 V

VCOUT-HYS Output Comparator Hysteresis 100 mV l VTOP/BOT Maximum Voltage Across Each of the VSEL = VIN 2.75 V l Supercapacitors After Charging VSEL = 0V 2.5 V LTC3225-1 l VIN-UVLO Input Supply Undervoltage Lockout VSEL = VIN 2.25 2.35 2.45 V l High-to-Low Threshold VSEL = 0 2.0 2.1 2.2 V

VIN-UVLO-HYS Input Supply Undervoltage Lockout VSEL = VIN 150 mV Hysteresis VSEL = 0 140 mV

3225fb 2 LTC3225/LTC3225-1

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, CIN = 2.2μF, CFLY = 1μF, unless otherwise specifi ed (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS l VIN Input Voltage Range VSEL = VIN 2.8 5.5 V l VSEL = 0 2.8 5.5 V l VCOUT Charge Termination Voltage VSEL = VIN 4.4 4.5 4.6 V l Sleep Mode Threshold (Rising Edge) VSEL = 0 3.9 4.0 4.1 V

VCOUT-HYS Output Comparator Hysteresis 100 mV l VTOP/BOT Maximum Voltage Across Each of the VSEL = VIN 2.35 V l Supercapacitors After Charging VSEL = 0 2.1 V LTC3225/LTC3225-1 l IQ-VIN No Load Operating Current at VIN IOUT = 0mA 20 40 μA l ISHDN-VIN Shutdown Current SHDN = 0V, VOUT = 0V 0.1 1 μA l ICOUT COUT Leakage Current VOUT = 5.6V, SHDN = 0V 1 3 μA l VOUT = 5.6V, Charge Pump in Sleep Mode 2 4 μA VOUT = 5.6V, SHDN Connected to VIN with 1 μA Input Supply Removed

IVIN Input Charge Current VIN = 3.6V, RPROG = 12k, CTOP = CBOT 306 mA

VIN = 3.6V, RPROG = 60k, CTOP = CBOT 55 mA

IOUT Output Charge Current VIN = 3.6V, RPROG = 12k, CTOP = CBOT, 125 150 175 mA VOUT = 4.5V (LTC3225), VOUT = 3.7V (LTC3225-1)

VIN = 3.6V, RPROG = 60k, CTOP = CBOT, 26 mA VOUT = 4.5V (LTC3225), VOUT = 3.7V (LTC3225-1) l VPGOOD PGOOD Low Output Voltage IPGOOD = –1.6mA 0.4 V l IPGOOD-LEAK PGOOD High Impedance Leakage Current VPGOOD = 5V 10 μA l VPG PGOOD Low-to-High Threshold Relative to Output Voltage Threshold 92 94 96 % l VPG-HYS PGOOD Threshold Hysteresis Relative to Output Voltage Threshold 0.25 1.2 2.5 %

ROL Effective Open-Loop Output Impedance VIN = 3.6V, VOUT = 4.5V (LTC3225) 8 Ω (Note 4) VIN = 3.6V, VOUT = 3.7V (LTC3225-1) 9 l fOSC CLK Frequency 0.6 0.9 1.5 MHz

VSEL, SHDN l VIH Input High Voltage 1.3 V l VIL Input Low Voltage 0.4 V l IIH Input High Current –1 1 μA l IIL Input Low Current –1 1 μA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: The LTC3225/LTC3225-1 are tested under pulsed load conditions may cause permanent damage to the device. Exposure to any Absolute such that TJ ≈ TA. The LTC3225/LTC3225-1 are guaranteed to meet Maximum Rating condition for extended periods may affect device performance speciﬁ cations from 0°C to 85°C. Speciﬁ cations over the reliability and lifetime. –40°C to 85°C operating temperature range are assured by design, Note 2: Based on long-term current density limitations. characterization and correlation with statistical process controls. Note 4: Output not in regulation; ROL ≡ (2 • VIN – VOUT)/IOUT

3225fb 3 LTC3225/LTC3225-1 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, CFLY = 1μF, CIN = 2.2μF, CTOP = CBOT , unless otherwise speciﬁ ed)

IOUT vs RPROG IOUT vs VOUT (RPROG = 12k) Efﬁ ciency vs VIN 160 180 100 VIN = 3.6V 90 140 VOUT = 4.5V (LTC3225) 160 80 120 140 70 120 100 LTC3225 60 100 (mA)

80 (mA) 50 LTC3225-1 OUT 80 OUT I 60 I 40 EFFICIENCY (%) 60 30 40 CTOP = CBOT ILOAD = 100mA 40 20 CTOP = CBOT VIN = 2.8V 20 V = V 20 VIN = 3.6V 10 SEL IN V = 0 VIN = 5.5V SEL 0 0 0 10 20 3040 50 60 0 0.5 131.52 2.5 3.5 4 4.5 5 2.5 3 3.5 44.5 5 5.5 RPROG (kΩ) VOUT (V) VIN (V)

3225 G01 3225 G02 3525 G03 Charge Pump Open-Loop Output Extra Input Current vs Output No-Load Input Current vs Resistance vs Temperature Current (IVIN – 2 • IOUT) Supply Voltage (2VIN – VCOUT)/IOUT 7 30 10.0 VIN = 3.6V VIN = 3.6V CHARGE PUMP IS ON 9.5 25 TA = 85°C 6 VOUT = 3.7V V = 5V 9.0 (LTC3225-1) OUT T = 25°C 20 A 5 8.5

(mA) T = –40°C V = 4.5V A IN OUT (Ω) VOUT = 4.5V (μA) 15 8.0

V = 3.7V OL

OUT IN (LTC3225) I R 4 7.5 EXTRA I 10 7.0 3 VOUT = 4.2V 5 6.5

2 0 6.0 20 40 60 80100 120 140 160 2.5 3 3.5 4 4.5 5 5.5 –40 –15 1035 60 85 IOUT (mA) VIN (V) TEMPERATURE (°C)

3225 G04 3225 G05 3225 G06

Charging Proﬁ le with Unequal Oscillator Frequency vs Initial Output Capacitor Voltage Supply Voltage Input Ripple and Input Current (Initial VTOP = 1.3V, VBOT = 1V) 0.94 SHDN 5V/DIV V 0.93 IN 20mV/DIV IVIN 300mA/DIV TA = 25°C 0.92 IVIN VCOUT 200mA/DIV 0mA 2V/DIV TA = –40°C 0.91 VTOP-VBOT TA = 85°C 500mV/DIV 0.90 FREQUENCY (MHz) 3225 G08 3225 G09 RPROG = 12k 200ns/DIV LTC3225 2 SEC/DIV VSEL = VIN 0.89 RPROG = 12k CTOP = CBOT = 1.1F C INITIAL VOLTAGE = 1.3V 0.88 TOP C INITIAL VOLTAGE = 1V 2.5 3 3.5 4 4.5 5 5.5 BOT VIN (V)

3225 G07

3225fb 4 LTC3225/LTC3225-1 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, CFLY = 1μF, CIN = 2.2μF, CTOP = CBOT , unless otherwise speciﬁ ed)

Charging Profi le with Unequal Charging Profi le with 30% Charging Profi le with 30% Initial Output Capacitor Voltage Mismatch in Output Capacitance Mismatch in Output Capacitance (Initial VTOP = 1V, VBOT = 1.3V) (CTOP > CBOT) (CTOP < CBOT)

SHDN SHDN SHDN 5V/DIV 5V/DIV 5V/DIV

IVIN IVIN IVIN 300mA/DIV 300mA/DIV 300mA/DIV

VCOUT VCOUT VCOUT 2V/DIV 2V/DIV 2V/DIV

V -V V -V TOP BOT VTOP-VBOT TOP BOT 200mV/DIV 500mV/DIV 200mV/DIV 3225 G11 3225 G12 LTC3225 2 SEC/DIV 3225 G10 LTC3225 5 SEC/DIV LTC3225 5 SEC/DIV VSEL = VIN VSEL = VIN VSEL = VIN RPROG = 12k RPROG = 12k RPROG = 12k CTOP = CBOT = 1.1F CTOP = 1.43F CTOP = 1.1F CTOP INITIAL VOLTAGE = 1V CBOT = 1.1F CBOT = 1.43F CBOT INITIAL VOLTAGE = 1.3V CTOP INITIAL VOLTAGE = 0V CTOP INITIAL VOLTAGE = 0V CBOT INITIAL VOLTAGE = 0V CBOT INITIAL VOLTAGE = 0V

PIN FUNCTIONS + C (Pin 1): Flying Capacitor Positive Terminal. A 1μF X5R VSEL (Pin 6): Output Voltage Selection Input. A logic + or X7R ceramic capacitor should be connected from C low at VSEL sets the regulated COUT to 4.8V (LTC3225) – to C . or 4V (LTC3225-1); a logic high sets the regulated COUT C– (Pin 2): Flying Capacitor Negative Terminal. to 5.3V (LTC3225) or 4.5V (LTC3225-1). Do not fl oat the VSEL pin. CX (Pin 3): Midpoint of Two Series Supercapacitors. This PROG (Pin 7): Charge Current Programming Pin. A resis- pin voltage is monitored and forced to track COUT (CX = tor connected between this pin and GND sets the charge COUT/2) during charging to achieve voltage balancing of the top and bottom supercapacitors. current. (See Applications Information section). SHDN (Pin 4): Active Low Shutdown Input. A low on SHDN GND (Pin 8, Exposed Pad Pin 11): Charge Pump Ground. puts the LTC3225/LTC3225-1 in low current shutdown These pins must be soldered directly to PCB ground. The mode. Do not fl oat the SHDN pin. exposed pad must be soldered to a low impedance PCB ground for rated thermal performance. PGOOD (Pin 5): Open-Drain Output Status Indicator. Upon start-up, this open-drain pin remains low until the output VIN (Pin 9): Power Supply for the LTC3225/LTC3225-1. VIN should be bypassed to GND with a low ESR ceramic voltage, VOUT, is within 6% (typical) of its fi nal value. Once capacitor of more than 2.2μF. VOUT is valid, PGOOD becomes Hi-Z. If VOUT falls 7.2% (typical) below its correct regulation level, PGOOD is COUT (Pin 10): Charge Pump Output Pin. Connect COUT to pulled low. PGOOD may be pulled up through an external the top plate of the top supercapacitor. COUT provides charge resistor to an appropriate reference level. This pin is Hi-Z current to the supercapacitors and regulates the fi nal volt- in shutdown mode. age to 4.8V/5.3V (LTC3225) or 4V/4.5V (LTC3225-1).

3225fb 5 LTC3225/LTC3225-1 SIMPLIFIED BLOCK DIAGRAM

CFLY

9 1 2 4 + – VIN VIN C C SHDN

SOFT-START AND UVLO THERMAL SHUTDOWN CONTROL PROTECTION

3000i

1.2V POR COUT 10 CTOP CHARGE CX RUN 3 PUMP GND CBOT 8 i PROG CLK 7

RPROG RUN/STOP R1

OSCILLATOR –

C1 R2 +

V – 2% REF POR

1.2V PGOOD VREF 5 1.088V (LTC3225) + 1.067V (LTC3225-1) C2 VREF – 6% VSEL 6 – VREF – 7.2%

3225 F01 Figure 1

OPERATION The LTC3225/LTC3225-1 are dual cell supercapacitor char- Normal Charge Cycle gers. Their unique topology maintains a constant output Operation begins when the SHDN pin is pulled above 1.3V. voltage with programmable charge current. Their ability The COUT pin voltage is sensed and compared with a preset to maintain equal voltages on both cells while charging voltage threshold using an internal resistor divider and protects the supercapacitors from damage that is possible a comparator. The preset voltage threshold is selectable with other charging methods, without the use of external with the VSEL pin. If the voltage at the COUT pin is lower balancing resistors. The LTC3225/LTC3225-1 include an than the preset voltage threshold, the oscillator is enabled. to a internal switched capacitor charge pump to boost VIN The oscillator operates at a typical frequency of 0.9MHz. regulated output voltage. A unique architecture maintains When the oscillator is enabled, the charge pump operates relatively constant input current for the lowest possible charging up COUT. Each time the charge pump starts up input noise. The basic charger circuit requires only three from shutdown, the input current drawn by the internal external components. charge pump ramps up at approximately 20mA/μs until it reaches a level which is determined by RPROG. 3225fb 6 LTC3225/LTC3225-1 OPERATION Once the output voltage is charged to the preset volt- Shutdown Mode age threshold, the part shuts down the internal charge Asserting SHDN low causes the LTC3225/LTC3225-1 to pump and enters into a low current state. In this state, enter shutdown mode. With the SHDN pin connected to the LTC3225/LTC3225-1 consume only about 20μA V and the input supply removed or grounded, less than from the input supply. The current drawn from C is IN OUT 1μA is consumed from the output, allowing the superca- approximately 2μA. pacitors to remain charged.

Automatic Cell Balancing If the input supply is present at VIN and the SHDN pin is Due to manufacturing tolerances, capacitance and leakage grounded, the LTC3225/LTC3225-1 draw approximately current can vary from supercapacitor to supercapacitor. 1μA of supply current. With the voltage at the COUT pin Without the automatic cell balancing scheme used in the discharged to 0V, this current drops to less than 1μA. Since LTC3225/LTC3225-1, the voltages across the supercapaci- the SHDN pin is a high impedance CMOS input, it should tors could differ from each other and potentially overvoltage never be allowed to fl oat. a cell. This can affect the performance and lifetime of a Output Voltage Programming supercapacitor. The LTC3225/LTC3225-1 have a V input pin that allows The LTC3225/LTC3225-1 constantly monitor the volt- SEL the user to set the output threshold voltage to either 4.8V age across both supercapacitors while charging. When or 5.3V for the LTC3225 and 4V or 4.5V for the LTC3225-1 the voltage across the supercapacitors is equal, both by forcing a low or high at the V pin respectively. capacitors are charged with equal currents. If the voltage SEL across one supercapacitor is lower than the other, the Output Status Indicator (PGOOD) lower supercapacitor’s charge current is increased and the higher supercapacitor’s charge current is decreased. During shutdown, the PGOOD pin is high impedance. When The greater the difference between the supercapacitor the charge cycle starts, an internal N-channel MOSFET voltages, the greater the difference in charge current per pulls the PGOOD pin to ground. When the output voltage, capacitor. The charge currents can increase or decrease VOUT, is within 6% (typical) of its fi nal value, the PGOOD as much as 50% to balance the voltage across the su- pin becomes high impedance, but charge current continues percapacitors. When the cell voltages are balanced, the to fl ow until VOUT crosses the charge termination voltage. supercapacitors are charged at a rate of approximately: When VOUT drops 7% below the charge termination voltage, the PGOOD pin again pulls low. 1 ICOUT = •IVIN 2 Current Limit/Thermal Protection If the leakage currents or capacitances of the two superca- The LTC3225/LTC3225-1 have built-in current limit as well pacitors are mismatched enough that varying the charge as overtemperature protection. If the PROG pin is shorted current is not suffi cient to balance their voltages, the to ground, a protection circuit automatically shuts off the LTC3225/LTC3225-1 stop charging the capacitor with the internal charge pump. At higher temperatures, or if the higher voltage until they are again balanced. This feature input voltage is high enough to cause excessive self-heat- protects either capacitor from experiencing an overvoltage ing of the part, the thermal shutdown circuitry shuts down condition. Attempting to equalize the voltages using parallel the charge pump once the junction temperature exceeds resistors wastes power, discharges the supercapacitors, approximately 150°C. It will enable the charge pump once and takes time to equalize the voltages. A 30% capacitance the junction temperature drops back to approximately mismatch leads to a 30% initial voltage difference after 135°C. The LTC3225/LTC3225-1 are able to cycle in and charging. It takes hours to equalize the voltages across out of thermal shutdown indefi nitely without latch-up or 1F supercapacitors using 10k resistors. damage until the overcurrent condition is removed.

3225fb 7 LTC3225/LTC3225-1 APPLICATIONS INFORMATION Programming Charge Current Charging Time Estimation The charge current is programmed with a single resistor The estimated charging time with equal initial voltages connecting the PROG pin to ground. The program resistor across the two supercapacitors is given by the equation: and the input/output charge currents are calculated using C •V( –V ) the following equations: t = OUT COUT INI CHRG I 3600V OUT IVIN = RPROG where COUT is the series output capacitance, VCOUT is the I voltage threshold set by the VSEL pin, VINI is the initial I = VIN (with matched output capacitors) voltage at the C pin and I is the output charge OUT 2 OUT OUT current given by: 1800V An RPROG resistor value of 2k or less (i.e., short circuit) I = OUT R causes the LTC3225/LTC3225-1 to enter overcurrent PROG shutdown mode. This mode prevents damage to the part by shutting down the internal charge pump. When the charging process starts with unequal initial voltages across the supercapacitors, only the capacitor with Power Effi ciency the lower voltage level is charged; the other capacitor is The power effi ciency (η) of the LTC3225/LTC3225-1 is not charged until the voltages equalize. This extends the similar to that of a linear regulator with an effective input charging time slightly. Under the worst-case condition, voltage of twice the actual input voltage. In an ideal regulat- whereby one capacitor is fully depleted while the other ing voltage doubler the power effi ciency is given by: remains fully charged due to signifi cant leakage current P V •I V mismatch, the charging time is about 1.5 times longer η = OUT = OUT OUT = OUT than normal. 2xIDEAL P V •2I 2V IN IN OUT IN Thermal Management At moderate to high output power the switching losses For higher input voltages and maximum output current, and quiescent current of the LTC3225/LTC3225-1 are there can be substantial power dissipation in the LTC3225/ negligible and the above expression is valid. For example, LTC3225-1. If the junction temperature increases above with V = 3.6V, I = 100mA and V regulated to 5.3V, IN OUT OUT approximately 150°C, the thermal shutdown circuitry auto- the measured effi ciency is 71.2% which is in close agree- matically deactivates the output. To reduce the maximum ment with the theoretical 73.6% calculation. junction temperature, a good thermal connection to the PC board is recommended. Connecting the GND pin (Pin 8) Effective Open-Loop Output Resistance (ROL) and the Exposed Pad (Pin 11) of the DFN package to a The effective open-loop output resistance (ROL) of a charge ground plane under the device on two layers of the PC pump is an important parameter that describes the strength board can reduce the thermal resistance of the package of the charge pump. The value of this parameter depends and PC board considerably. on many factors including the oscillator frequency (fOSC), value of the fl ying capacitor (CFLY), the non-overlap time, the internal switch resistances (RS) and the ESR of the external capacitors.

3225fb 8 LTC3225/LTC3225-1 APPLICATIONS INFORMATION

VIN Capacitor Selection its voltage can reverse upon start-up of the LTC3225/ LTC3225-1. Low ESR ceramic capacitors should always The type and value of C controls the amount of ripple IN be used for the fl ying capacitor. present at the input pin (VIN). To reduce noise and ripple, it is recommended that low equivalent series resistance The fl ying capacitor controls the strength of the charge (ESR) multilayer ceramic chip capacitors (MLCCs) be pump. In order to achieve the rated output current, it is used for CIN. Tantalum and aluminum capacitors are not necessary to use at least 0.6μF of capacitance for the recommended because of their high ESR. fl ying capacitor. The input current to the LTC3225/LTC3225-1 is relatively The effective capacitance of a ceramic capacitor varies with constant during both the input charging phase and the temperature and voltage in a manner primarily determined output charging phase but drops to zero during the clock by its formulation. For example, a capacitor made of X5R non-overlap times. Since the non-overlap time is small or X7R material retains most of its capacitance from (~40ns) these missing “notches” result in only a small –40°C to 85°C whereas a Z5U or Y5V type capacitor loses perturbation on the input power supply line. Note that a considerable capacitance over that range. X5R, Z5U and higher ESR capacitor, such as a tantalum, results in higher Y5V capacitors may also have a poor voltage coeffi cient input noise. Therefore, ceramic capacitors are recom- causing them to lose 60% or more of their capacitance mended for their exceptional ESR performance. Further when the rated voltage is applied. Therefore, when com- input noise reduction can be achieved by powering the paring different capacitors, it is often more appropriate to LTC3225/LTC3225-1 through a very small series inductor compare the amount of achievable capacitance for a given as shown in Figure 2. case size rather than comparing the specifi ed capacitance value. For example, over rated voltage and temperature A 10nH inductor will reject the fast current notches, conditions, a 4.7μF 10V Y5V ceramic capacitor in a 0805 thereby presenting a nearly constant current load to the case may not provide any more capacitance than a 1μF 10V input power supply. For economy, the 10nH inductor can X5R or X7R capacitor available in the same 0805 case. In be fabricated on the PC board with about 1cm (0.4") of fact, over bias and temperature range, the 1μF 10V X5R PC board trace. or X7R provides more capacitance than the 4.7μF 10V Flying Capacitor Selection Y5V capacitor. The capacitor manufacturer’s data sheet should be consulted to determine what value of capacitor Warning: Polarized capacitors such as tantalum or alumi- is needed to ensure minimum capacitance values are met num should never be used for the fl ying capacitor since over operating temperature and bias voltage.

10nH 9 VIN VIN LTC3225 0.1μF 2.2μF LTC3225-1 8, 11 GND

3225 F02

Figure 2. 10nH Inductor Used for Input Noise Reduction

3225fb 9 LTC3225/LTC3225-1 APPLICATIONS INFORMATION Table 1 contains a list of ceramic capacitor manufacturers also be generated if the fl ying capacitors are far from the and how to contact them. part (i.e. the loop area is large). To prevent capacitive energy transfer, a Faraday shield may be used. This is a Table 1. Capacitor Manufacturers grounded PC trace between the sensitive node and the AVX www.avx.com LTC3225/LTC3225-1 pins. For a high quality AC ground it Kemet www.kemet.com should be returned to a solid ground plane that extends Murata www.murata.com all the way to the LTC3225/LTC3225-1. Taiyo Yuden www.t-yuden.com Vishay www.vishay.com Table 2. Supercapacitor Manufacturers TDK www.component.tdk.com CAP-XX www.cap-xx.com NESS CAP www.nesscap.com Layout Considerations Maxwell www.maxwell.com Due to the high switching frequency and high transient Bussmann www.cooperbussmann.com currents produced by the LTC3225/LTC3225-1, careful AVX www.avx.com board layout is necessary for optimum performance. An Illinois Capacitor www.illcap.com unbroken ground plane and short connections to all the Tecate Group www.tecategroup.com external capacitors improves performance and ensures proper regulation under all conditions. Charging a Single Supercapacitor The voltages on the fl ying capacitor pins C+ and C– have The LTC3225/LTC3225-1 can also be used to charge a very fast rise and fall times. The high dV/dt values on single supercapacitor by connecting two series-connected these pins can cause energy to capacitively couple to matched ceramic capacitors with a minimum capacitance adjacent printed circuit board traces. Magnetic fi elds can of 100μF in parallel with the supercapacitor as shown in Figure 3.

LTC3225 LTC3225-1 10 COUT VOUT 3 C1 CX CSUP 8, 11 C2 GND

3225 F03 C1 = C2 ≥ 100μF

Figure 3. Charging a Single Supercapacitor

3225fb 10 LTC3225/LTC3225-1 TYPICAL APPLICATION 5V Supercapacitor Back-Up Supply

Q2 Si4421DY

LTM4616 V 1.8V IN V V 5V IN1 OUT1 C6 VIN2 FB1 100μF C5 R3 Q1 22μF 4.78k GND I Si4421DY THM1 1.2V VOUT2 C7 C8 FB2 100μF 100μF R2 10k VIN COUT 3225 TA02 C2 LTC4412 ITHM2 + 10F V SENSE C CX IN GND R2 C1 LTC3225 C3 GND GATE 1μF LTC3225-1 10F 470k C– GND CTL STAT

C4 SHDN 2.2μF VSEL PROG

R1 12k

3225fb 11 LTC3225/LTC3225-1 PACKAGE DESCRIPTION

DDB Package 10-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1722 Rev Ø)

0.64 0.05 R = 0.115 p 3.00 0.10 0.40 0.10 (2 SIDES) p TYP p (2 SIDES) R = 0.05 TYP 6 10 0.70 p0.05 2.55 p0.05 2.00 0.10 1.15 0.05 PIN 1 BAR p p (2 SIDES) PIN 1 TOP MARK R = 0.20 OR (SEE NOTE 6) 0.25 45 PACKAGE 0.64 p 0.05 s o OUTLINE (2 SIDES) CHAMFER 5 1 (DDB10) DFN 0905 REV Ø 0.25 0.05 0.25 0.05 p 0.200 REF 0.75 p0.05 p 0.50 BSC 0.50 BSC 2.39 p0.05 2.39 p0.05 (2 SIDES) (2 SIDES) 0 – 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD

NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

3225fb 12 LTC3225/LTC3225-1

REVISION HISTORY (Revision history begins at Rev B)

REV DATE DESCRIPTION PAGE NUMBER B 6/10 Updated Note 3 in Electrical Characteristics section. 2, 3 Updates to Pins 8 and 11 in Pin Functions. 5 Update to text in Layout Considerations section. 10 Updated Typical Application and Related Parts. 14

3225fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 13 LTC3225/LTC3225-1 TYPICAL APPLICATION 12V Supercapacitor Back-Up Supply

D1 LT3740 CSHD6-40C HIGH EFFICIENCY DOWN CONVERTER DPAK V CHARGER 3 * V OUT IN + 1.8V 12V VIN VOUT V C 10A IN OUT + C1 LT3740 LTC3225/ 47μF LTC3225-1 GND GND 25V C2 C+ CX DCAP 1μF GND GND 10V C– GND 10A R6 D2 M4 1k CMSH3-20 Si4410DY M2 VBIAS IRF7424 3.3V C5 10μF D3 GND CMSH3-20 CHARGER 2 * VIN COUT LTC3225/ D4 LTC3225-1 CMSH3-20 C3 C+ CX 1μF 10V C– GND 1 8 VM VCC LTC2915 R7 1 8 2 7 PGND OUT R5 SEL1 SEL2 10k M3 1k 3 6 2 LTC4441-1 7 M1 TOL/MR RT R1 SGND DRV Si4410DY 2k CC IRF7424 4 5 3 6 R3 GND RST IN V CHARGER 1 IN 332k R2 4 5 C7 V C EN/SHDN FB IN OUT C6 100k 10μF LTC3225/ 0.1μF R4 LTC3225-1 84.5k C4 C+ CX 1μF – 10V C GND

3225 TA03 * REQUIRES PIN 8 (GND) AND EXPOSED PAD TO BE CONNECTED TO A THERMAL PAD ISOLATED FROM THE SYSTEM GROUND.

RELATED PARTS PART NUMBER DESCRIPTION COMMENTS

LTC1751-3.3/LTC1751-5 Micropower 5V/3.3V Doubler Charge Pumps IQ = 20μA, Up to 100mA Output, MS-8 Package LTC3200 Constant Frequency Doubler Charge Pump Low Noise, 5V Output or Adjustable

LTC3203/LTC3203B/ 500mA Low Noise High Effi ciency Dual Mode VIN: 2.7V to 5.5V, 3mm × 3mm 10-Lead DFN Package LTC3203B-1/LTC3203-1 Step-Up Charge Pumps LTC3204/LTC3204B-3.3/ Low Noise Regulating Charge Pumps Up to 150mA (LTC3204-5), Up to 50mA (LTC3204-3.3) LTC3204-5 LTC3221/LTC3221-3.3/ Micropower Regulated Charge Pump Up to 60mA Output LTC3221-5 LTC3240-3.3/LTC3240-2.5 Step-Up/Step-Down Regulated Charge Pumps Up to 150mA Output ® LT 3420/LT3420-1 1.4A/1A Photofl ash Capacitor Charger with Charges 220μF to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V, Automatic Top-Off ISD < 1μA, 10-Lead MS Package LT3468/LT3468-1/ 1.4A/1A/0.7A, Photofl ash Capacitor Charger VIN: 2.5V to 16V, Charge Time = 4.6 Seconds for the LT3468 (0V to 320V, LT3468-2 100μF, VIN = 3.6V), ISD < 1μA, ThinSOT™ Package LTC3484-0/LTC3484-1/ 1.4A/0.7A/1A, Photofl ash Capacitor Charger VIN: 1.8V to 16V, Charge Time = 4.6 Seconds for the LT3484-0 (0V to 320V, LTC3484-2 100μF, VIN = 3.6V), ISD < 1μA, 2mm × 3mm 6-Lead DFN Package LT3485-0/LT3485-1/ 1.4A/0.7A/1A/2A Photofl ash Capacitor Charger VIN: 1.8V to 10V, Charge Time = 3.7 Seconds for the LT3485-0 (0V to 320V, LT3485-2/LT3485-3 with Output Voltage Monitor and Integrated 100μF, VIN = 3.6V), ISD < 1μA, 3mm × 3mm 10-Lead DFN Driver IGBT LT3750 Capacitor Charger Controller Charges Any Size Capacitor, 10-Lead MS Package LT3751 Capacitor Controller with Regulation Charges Any Size Capacitor, 4mm × 5mm QFN-20 Package

3225fb Linear Technology Corporation LT 0610 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 14 ● ● (408) 432-1900 FAX: (408) 434-0507 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008