Introduction to Field Programmable Gate Arrays Fpgas Outline

Introduction to Field Programmable Gate Arrays FPGAs Outline

 Q. What does FPGA stand for?

 FPGA Architecture  Common characteristics  Specialised blocks

 FPGA Design Flow  Hardware Description Languages  Design Tools

 FPGAs Applications  Particle Physics  Computing

 Trends and Future of FPGAs The Design Warrior’s Guide to FPGAs Courtesy of John Coughlan Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) What does FPGA stand for?

 Field Programmable Gate Array

 Field : “in the field”

 Programmable : “Re-Configurable” Change Logic Functions

 Gate Array : reference to ASIC internal architecture

 Field Programmable Gate Array

 (Very) Large Scale Integrated Circuit

 Digital Logic

 Programmed after manufacture rather than unchangeable Application Specific Integrated Circuit ASIC

 First appeared in 1980’s. Took off in last decade.

 Standard IC manufacturing process

 Following Moore’s Law

 Essential Components in modern HEP Electronics (& Industry!)  Data Acquisition (Millions Channels)  Triggers  Computer Interfaces VME

 Field Programmable Gate Array  Configurable (Programmable) General Logic Blocks  Configurable Interconnects  Plus Special Purpose Blocks (Embedded Processors)  Configured (multiple times) to perform variety of tasks (HEP)

Simple Logic Block ‘Islands’ in a ‘Sea’ of Interconnects 10,000 … 100,000+ (Massively Parallel HEP)

 FPGAs appeared in the 1980’s. Took off in last decade.

 Bridge gap between simple Programmable Logic and semi custom ASICs (Application Specific Integration Circuits).

 Simple Logic (used to “glue” other ICs together)

 Reprogrammable (UV light, electrically eraseable)

 Cheap

 Easy to Program

 Many different variations

 Eg. Implement Logic as ‘Sum of Products’ Terms

PLDs

SPLDs CPLDs OR array l l l Programmable

PROMs PLAs PALs GALs etc.

 Large Complex Functions

 Customised for Extremes of Speed, Low Power, Radiation Hard (HEP)

 (Very) Expensive (in small quantities) @ 90 nm ~ $1M mask set

 (Very) Hard to Design.

 Long Design cycles.

 Not Reprogrammable. High Risk

 Semi Custom Gate Arrays.

ASICs

Gate Structured Standard Full Arrays ASICs Cell Custom

Increasing complexity The Design Warrior’s Guide to FPGAs Courtesy of John Coughlan Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) FPGAs best of both worlds…

 Large Complex Functions

 Programmability, Flexibility.

 Massively Parallel Architecture

 Fast Turnaround Designs

 Mass produced. Cheap

 Prototype ASICs

 Power Hungry

 Logic Elements  Lookup Table  Flip Flops  Multiplexers

 Memory Resources  SRAM blocks

 Routing Resources  Hierarchy Programmable Channels between Logic Elements

 Configurable I/O  Interfaces to the real world. Logic Levels. Fast Serial I/O

 Massively Parallel Architecture (HEP)

 Clocked Logic Design

 CMOS based using SRAM cells for configuration

Required function Truth table  Lookup Table LUTs (Combinatorial Logic) AND abc y a OR 0 0 0 0  & Multiplexers b 0 0 1 1 | y c 0 1 0 0  Flip-Flops (Clocked Registered Logic) 0 1 1 1 y = (a & b) | c 1 0 0 0  Options configured by SRAM cells 1 0 1 1 1 1 0 1 1 1 1 1

16-bit SR 16x1 RAM a 4-input LUT b y c mux d flip-flop q e clock clock enable set/reset

 SRAM blocks

 Data Buffers (HEP) Columns of embedded RAM blocks  FIFOs Arrays of programmable  Code logic blocks

 Recently Embedded Micro-Processors in Fabric  Hard Cores e.g. RISC PowerPC  Soft Cores  Peripherals Timers, GPIO

 Run Operating System e.g. Linux

 Combine Micro-Processor uP uP & Massively Parallel Logic

uP uP  Dual Design Flows  Firmware HDL  Software C (a) One embedded core (b) Four embedded cores

 Several hundred of I/O pins

 All flavours of Logic Levels e.g. LVDS, TTL

 High Speed Serial Transceivers (up to 10? Gbps) (HEP)

 Ethernet MAC Cores

 Ethernet MAC COREs inside FPGA

 Drive Data via Serialiser I/O and Optical Transceiver chip

 Direct to Network Card in PC.

 2 IP Nodes on Network.

 Small DAQ systems

Dev Board V2 Pro FPGA Rocket IO MGTs Gigabit Ethernet Prog’ Data SFP RAID 0 Generator Gb Opto Transceiver

Tx1 Tx2 Quixtream ® PC Tx3 Tx4 UDP core Gb NIC Rx1 Prog’ Data Generator

Trigger

 Field Programmable Gate Array  Configurable (Programmable) General Logic Blocks  Configurable Interconnects

 Bit File contains the Configuration Information

Programmable interconnect

Programmable logic blocks

 SRAM cells holding configuration are Volatile Memory

 Lose configuration when board power is turned off.

 Keep Bit Pattern describes the Logic Functions in non-Volatile Memory e.g. ROM or Compact Flash card

 Reprogramming takes ~ secs

 Uses JTAG Boundary Scan

 High level Description of Logic Design  Schematic  Hardware Description Language

 Compile into Netlist. Low (Logic Gates) level description.

 Schematic Gate-level Target Netlist to FPGA Fabric capture netlist

BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q;  Mapping and Packing WIRE SET, N_DATA, CLEAR; GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR,  Placing and Routing OUT1=Q, OUT2=N_Q); END CIRCUIT=TEST; Mapping  Tools Generate the Bit File Packing

Place-and- Route Timing analysis  Simulation and timing report

 Timing Analysis Fully-routed physical Gate-level netlist (CLB-level) netlist for simulation

SDF (timing info) for simulation

 Schematic Capture of Logic Design.

 Useful at Top level.

 Create Netlist. Text file with signal connections.

Schematic Gate-level capture netlist

BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; WIRE SET, N_DATA, CLEAR;

GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q);

END CIRCUIT=TEST;

Logic Place-and- Simulator Route

BEGIN CIRCUIT=TEST Functional Extraction and verification timing analysis INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; Detect and fix problems WIRE SET, N_DATA, CLEAR; Detect and fix problems GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q);

END CIRCUIT=TEST;

 Behavioural / Register Transfer Level Description  Program Statements. Loops. If Statements …etc

 Describing Mixture of Combinatorial and Sequential Logic and Signals between.

 Engineers call it Firmware Behavioral Loops (Algorithmic) Processes  VHDL (VHSIC Hardware Description Language)  Very High Speed Integrated Circuit RTL Functional  VERILOG (US) Boolean

Gate  Synthesis (Compilation) Structural  Generate Netlist Switch

 Logic Simulation Tools  Create Computer model of Logic  Feed Test Vector signals in and compare output with expected pattern

 Virtual Logic Analysers  Capture signals in real time whilst FPGA is running logic

JTAG (from external virtual logic analyzer program or another internal logic analyzer block)

Signals we wish Virtual Logic to monitor Analyzer Embedded RAM Block

Control Logic

Start/Stop conditions to JTAG (to external virtual logic trigger on analyzer program or another internal logic analyzer block) The Design Warrior’s Guide to FPGAs Courtesy of John Coughlan Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) 15 Years Evolution

 SRAM based FPGA devices following Moore’s Law  200 x Logic  40 x Faster  Logic Element cost ~ 1$ in 1990 ; $0.002 in 2004

1000x

XC4000 & Spartan

100x Virtex-4

CLB Capacity Virtex-II & Speed Virtex-II Pro Power per MHz Virtex & Price Virtex-E

ITRS Roadmap 10x

Spartan-2

XC4000 Spartan-3

1x '91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04 Year The Design Warrior’s Guide to FPGAs Courtesy of John Coughlan Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Trends

 State of Art is 65nm on 300 mm wafers

 Top of range 100,000+ Logic Elements

 1,000 pins (Ball Grid Arrays)

 Same cost  1995 : 500 Logic Elements  2000 : 10,000 Logic Elements  2005 : 50,000 Logic Elements

 Challenges  Power. Leakage currents.  Signal Integrity  Design complexity

$2.1B$2.6B $4.1B $2.6B $2.3B $2.6B $3.1B 100%

31% 33% 34% 32% 31% 32% 32% 80%

60% 18% 17% 24% 20% 32% 28% 39%

40% 50% 51% Market Share (%) Market Share 49% 44% 38% 35% 20% 30%

0% Calendar year 1998 1999 2000 2001 2002 2003 2004

Xilinx Altera All Others

 FPGAs in Standard CMOS Process

 Not Designed for Very Rad Hard environments

 Not used in Front End Electronics (inside Detectors)

 Single Event Upsets

 SRAM Reconfigure

 Design Logic Triple Redundancy

 Are used in low level Rad environments (outside Detectors)

 In satellites

 On Mars

 High Performance Computing  CRAY XD1 : OPTERON + FPGA

 Vendor

 Resources Logic

 Memory

 I/O pins

 Packaging

 Device Families

 Vendor Tools, IP Cores

 Special Purpose blocks e.g. CPUs

 Speed Grade

 Cost

 FPGA Package is a little PCB

 Ball Grid Arrays

 Assembly is a critical Manufacturing Step

 Signal Integrity Issues

 Digital Signal Processing Functions  FIR Filters  Digital Radio

 Advantage over DSP chips Massively Parallel System

Multiplier Adder Accumulator

A[n:0]

B[n:0] ++ Y[(2n - 1):0]

MAC