DOCSLIB.ORG

STM32 More Than a Core

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
STM32 More Than a Core 2804003-Cantrell.qxp 3/7/2008 10:45 AM Page 80 SILICON UPDATE by Tom Cantrell More Than a Core While examining 32-bit microcontrollers last month, Tom decided that the STMicroelectronics STM32 was worth a second look. With the new ARM Cortex M3 core, good peripherals, integration, and energy efficiency, this could be just the MCU for your next project. Having covered the territory last debates have become less relevant, thought these shining stars would month (“More Bits, Less Filling,” especially for blue-collar embedded burn out so fast? Circuit Cellar 212, 2008), it’s not my apps. Maybe it’s just battle fatigue, The microprocessor was barely born intention to get stuck on the topic of having seen so many architectures before it headed into battle. Early 8-bit 32-bit MCUs. Believe me, there’s march off to war. Remember way back skirmishes foreshadowed the epic plenty of other neat stuff going on in the mainframe years (1960–1970s) struggle between the Intel ’x86 and with FPGAs, wireless, sensors, and when companies like Univac, the then Motorola 68K, a battle that other wonders of the silicon age. Burroughs, and Honeywell challenged counted a myriad of upstart architec- Nevertheless, if you have anything to IBM with “better” architectures? All tures as collateral casualties. May the do with embedded systems, you need dead and gone. 88K, i860, Clipper, 29K, and all of the to stay up to speed with the latest hot Then there were the fabulous mini- others rest in peace. rod chips or you’ll get left behind. computers such as the Data General True believers are entitled to pitch In some ways these fast and furious Nova and the Digital Equipment VAX. their favorite architecture and poo-poo MCUs remind me of the brand new Like teenagers, they seemed invinci- the others. Taking nothing away from Tesla Motors high-performance elec- ble. “Nova” indeed. Who would have Cortex M3, the fact is that all of the tric vehicle just now hitting the streets. It’s got the efficiency and ICode green aspects of a golf cart, but can Flash interface Flash smoke the tires when you punch it. DCode memory Cortex-M3 The big difference is that the 32-bit System MCUs don’t cost an arm and a leg, but in fact are a luxury any designer SRAM can afford. DMA So this month, you’re invited to Ch. 1 AHB system bus Bridge 1 look over my shoulder as I pop the Ch. 2 Bridge 2 APB2 APB1 hood on the STMicroelectronics STM32 (see Figure 1). You’ll recall Ch. 7 GPIOA USART1 USART2 WWDG GPIOB SPI1 USART3 CAN from last time that its main claim to GPIOC ADC1 SPI2 BKP fame is the use of the new ARM GPIOD ADC2 I2C1 PWR GPIOE TIM1 I2C2 TIM2 Cortex M3 core. Sure, that’s newswor- EXTI AFIO USB TIM3 thy, but there’s more to the STM32 IWDG TIM4 than that. WORLD BEYOND CORE DMA Request Indeed, over the years, I’ve come to Figure 1—The ARM Cortex M3 core is the attention-getter in the new STM32 MCU from STMicroelectronics. But the conclusion that “core wars” there’s more to an MCU than a processor core, including lots of flash memory, fast SRAM, and a bunch of I/O. 80 Issue 213 April 2008 CIRCUIT CELLAR® www.circuitcellar.com 2804003-Cantrell.qxp 3/7/2008 10:45 AM Page 81 Package pins 36 36 48 48 48 64 64 64 100 100 Flash 32 KB 64 KB 32 KB 64 KB 128 KB 32 KB 64 KB 128 KB 64 KB 128 KB SRAM 10 (6) KB 20 (10) KB 10 (6) KB 20 (10) KB 20 (16) KB 10 (6) KB 20 (10) KB 20 (16) KB 20 (10) KB 20 (16) KB General-purpose 2 3 2 3 3 2 3 3 3 3 timers Advanced control 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) timer SPI 1 1 1 2 2 1 2 2 2 2 I2C 1 1 1 2 2 1 2 2 2 2 USART 2 2 2 3 3 2 3 3 3 3 Full-speed USB 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 2.0 CAN 2.0B 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 12-bit 1-µs A/D 2 (1) × 10 ch 2 (1) × 10 ch 2 (1) × 10 ch 2 (1) × 10 ch 2 (1) × 10 ch 2 (1) × 16 ch 2 (1) × 16 ch 2 (1) × 16 ch 2 (1) × 16 ch 2 (1) × 16 ch General-purpose 26 26 37 37 37 51 51 51 80 80 I/Os CPU Frequency 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz Table 1—STMicroelectronics blasts off the starting line with a full complement of 20 STM32 parts, divided equally between “Performance” and “Access” lines. In this table, the “Access” line features are shown in parenthesis where they differ from the “Performance” line. Another difference is that both lines come standard with a –40° to 85°C tempera- ture range, but the “Performance” parts also have an extended temperature range (–40° to 105°C) option. major 32-bit MCUs (including the can lead to the awkward situation a curse if the I/O traffic clogs available ARM7 and ARM9 chips ST also offers) where more “megahertz” means less bus bandwidth and demands a lot of are fully capable of getting the job performance. It’s no surprise that handholding by the processor. The done in most applications. most 32-bit MCUs devote silicon to STM32 avoids that pitfall with multi- Look at a die photo of any 32-bit the cause of getting around the flash ple on-chip I/O busses to boost band- flash MCU and what you’ll find is a bottleneck. The STM32 is no excep- width and a powerful seven-channel little processor core stuck in the cor- tion, using a 64-bit wide flash bus in DMA controller that offloads the ner, dwarfed by surrounding memory conjunction with two 64-bit prefetch processor of I/O grunt work. and I/O silicon. The fact is, while the buffers to hide the flash latency. Even Another way to boost bus band- architecture chosen for the core may though this simple prefetch scheme is width is to demand less of it in the be the sizzle, it’s the implementation relatively unobtrusive, there may be first place. As I went through the of an entire chip that’s the steak. times when you’d prefer to turn it off, specs, I was impressed with the way which the STM32 allows you to do. the STM32 uses “smart” I/O devices FLASH FOR CASH If you really need max MIPS, take that take care of their own dirty laun- Sure architecture has an impact on advantage of the fact that the STM32 dry rather than bugging the processor performance, but so do a lot of other allows execution of code from the on- to do it for them. things starting with bus bandwidth. chip SRAM at full speed. You can use Even the simple stuff such as serial The differences (relatively minor actu- the SRAM as a “programmer directed and parallel I/O is pretty fancy these ally) in the way competing architec- cache,” preloading it with perform- days. Every STM32 I/O line is indi- tures choose to deal with instructions ance-critical routines such as DSP vidually programmable as input (pull- and data don’t matter nearly as much inner loops and interrupt handlers. up and pull-down options) or output as how fast a particular chip can actu- Just remember that a MIPS rating is (push/pull or open collector with out- ally do it. only half the story. You can crank put drive strength options). I/O lines In the blue-collar space these chips through all of the instructions you are also 5-V tolerant and can target, we’re generally talking about non- want, but nothing useful happens source/sink a whopping 25 mA, with cache implementations. That means flash until data makes its way to and from the not unexpected caveat that total (i.e., instruction fetch) bandwidth is a crit- the pins. As a practical matter, the on- chip power is limited to 150 mA. A ical limiting factor. The STM32 comes in chip I/O devices are just as important measure of port-remapping capability two flavors, “Access” and “Performance,” as the processor core itself in achiev- enables juggling peripheral pin with a major difference being that the for- ing peak system performance. assignments to best fit a particular mer runs up to 36 MHz and the latter to application. 72 MHz (see Table 1). Just keep in mind I/O U As I’ve noted before, the traditional that higher clock rates require 0, 1, or 2 I/O throughput starts with the num- RISC load/store architecture is prob- flash wait states for clock rates up to ber and performance of the on-chip I/O lematic for “atomic” bit operations 24, 48, and 72 MHz, respectively. devices themselves. The STM32 has a because an interrupt might occur If something isn’t done, wait states lot of fast I/O, but that can actually be between the load and the store.
Load more

Recommended publications
  • Arm Cortex-R52
    Arm Cortex-R52 Product Brief Benefits Overview 1. Software Separation The Cortex-R52 is the most advanced processor in the Cortex-R family delivering real-time Robust hardware-enforced software performance for functional safety. As the first Armv8-R processor, Cortex-R52 introduces separation provides confidence that support for a hypervisor, simplifying software integration with robust separation to protect software functions can’t interfere with safety-critical code, while maintaining real-time deterministic operation required in high each other. For safety-related tasks, dependable control systems. this can mean less code needs to be certified, saving time, cost and effort. Cortex-R52 addresses a range of applications such as high performance domain controllers for vehicle powertrain and chassis systems or as a safety island providing 2. Multiple OS upportS protection in complex ADAS and Autonomous Drive systems. Virtualization support gives developers flexibility, readily allowing consolidation Safety Ready of applications using multiple operating systems within a single CPU. This eases Arm Cortex-R52 is part of Arm’s Safety Ready portfolio, a collection of Arm IP that the addition of functionality without have been through various and rigorous levels of functional safety systematic flows growing the number of electronic and development. control units. Learn more at www.arm.com/safety 3. Real-Time Performance High-performance multicore clusters of Cortex-R52 CPUs deliver real-time responsiveness for deterministic systems with the lowest Cortex-R latency. 1 Specifications Architecture Armv8-R Arm and Thumb-2. Supports DSP instructions and a configurable Floating-Point Unit either with Instruction Set single-precision or double precision and Neon.
    [Show full text]
  • ARM Architecture
    ARM Architecture Comppgzuter Organization and Assembly ygg Languages Yung-Yu Chuang with slides by Peng-Sheng Chen, Ville Pietikainen ARM history • 1983 developed by Acorn computers – To replace 6502 in BBC computers – 4-man VLSI design team – Its simp lic ity comes from the inexper ience team – Match the needs for generalized SoC for reasonable power, performance and die size – The first commercial RISC implemenation • 1990 ARM (Advanced RISC Mac hine ), owned by Acorn, Apple and VLSI ARM Ltd Design and license ARM core design but not fabricate Why ARM? • One of the most licensed and thus widespread processor cores in the world – Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras – ARM7: GBA, iPod – ARM9: NDS, PSP, Sony Ericsson, BenQ – ARM11: Apple iPhone, Nokia N93, N800 – 90% of 32-bit embedded RISC processors till 2009 • Used especially in portable devices due to its low power consumption and reasonable performance ARM powered products ARM processors • A simple but powerful design • A whlhole filfamily of didesigns shiharing siilimilar didesign principles and a common instruction set Naming ARM •ARMxyzTDMIEJFS – x: series – y: MMU – z: cache – T: Thumb – D: debugger – M: Multiplier – I: EmbeddedICE (built-in debugger hardware) – E: Enhanced instruction – J: Jazell e (JVM) – F: Floating-point – S: SthiiblSynthesizible version (source code version for EDA tools) Popular ARM architectures •ARM7TDMI – 3 pipe line stages (ft(fetc h/deco de /execu te ) – High code density/low power consumption – One of the most used ARM-version (for low-end systems) – All ARM cores after ARM7TDMI include TDMI even if they do not include TDMI in their labels • ARM9TDMI – Compatible with ARM7 – 5 stages (fe tc h/deco de /execu te /memory /wr ite ) – Separate instruction and data cache •ARM11 ARM family comparison year 1995 1997 1999 2003 ARM is a RISC • RISC: simple but powerful instructions that execute within a single cycle at high clock speed.
    [Show full text]
  • OMAP-L138 DSP+ARM9™ Development Kit Low-Cost Development Kit to Jump-Start Real-Time Signal Processing Innovation
    OMAP-L138 DSP+ARM9™ Development Kit Low-cost development kit to jump-start real-time signal processing innovation Texas Instruments’ OMAP-L138 development kit is a new, robust low-cost development board designed to spark innovative designs based on the OMAP-L138 processor. Along with TI’s new included Linux™ Software Development Kit (SDK), the OMAP-L138 development kit is ideal for power- optimized, networked applications including industrial control, medical diagnostics and communications. It includes the OMAP-L138 baseboard, SD cards with a Linux demo, DSP/BIOS™ kernel and SDK, and Code Composer Studio™ (CCStudio) Integrated Development Environment (IDE), a power supply and cord, VGA cable and USB cable. Technical details • SATA port (3 Gbps) Key features and benefi ts The OMAP-L138 development kit is based • VGA port (15-pin D-SUB) • OMAP-L138 DSP+ARM9 software and on the OMAP-L138 DSP+ARM9 processor, a • LCD port (Beagleboard-XM connectors) development kit to jump-start real-time low-power applications processor based on • 3 audio ports signal processing innovation an ARM926EJ-S and a TMS320C674x DSP • Reduces design work with downloadable core. It provides signifi cantly lower power • 1 line in and duplicable board schematics and than other members of the TMS320C6000™ • 1 line out design fi les platform of DSPs. The OMAP-L138 processor • 1 MIC in • Fast and easy development of applica- enables developers to quickly design and • Composite in (RCA jack) tions requiring fi ngerprint recognition and develop devices featuring robust operating • Leopard Imaging camera sensor input (32- face detection with embedded analytics systems support and rich user interfaces with pin ZIP connector) • Low-power OMAP-L138 DSP+ a fully integrated mixed-processor solution.
    [Show full text]
  • Μc/OS-II™ Real-Time Operating System
    μC/OS-II™ Real-Time Operating System DESCRIPTION APPLICATIONS μC/OS-II is a portable, ROMable, scalable, preemptive, real-time ■ Avionics deterministic multitasking kernel for microprocessors, ■ Medical equipment/devices microcontrollers and DSPs. Offering unprecedented ease-of-use, ■ Data communications equipment μC/OS-II is delivered with complete 100% ANSI C source code and in-depth documentation. μC/OS-II runs on the largest number of ■ White goods (appliances) processor architectures, with ports available for download from the ■ Mobile Phones, PDAs, MIDs Micrium Web site. ■ Industrial controls μC/OS-II manages up to 250 application tasks. μC/OS-II includes: ■ Consumer electronics semaphores; event flags; mutual-exclusion semaphores that eliminate ■ Automotive unbounded priority inversions; message mailboxes and queues; task, time and timer management; and fixed sized memory block ■ A wide-range of embedded applications management. FEATURES μC/OS-II’s footprint can be scaled (between 5 Kbytes to 24 Kbytes) to only contain the features required for a specific application. The ■ Unprecedented ease-of-use combined with an extremely short execution time for most services provided by μC/OS-II is both learning curve enables rapid time-to-market advantage. constant and deterministic; execution times do not depend on the number of tasks running in the application. ■ Runs on the largest number of processor architectures with ports easily downloaded. A validation suite provides all documentation necessary to support the use of μC/OS-II in safety-critical systems. Specifically, μC/OS-II is ■ Scalability – Between 5 Kbytes to 24 Kbytes currently implemented in a wide array of high level of safety-critical ■ Max interrupt disable time: 200 clock cycles (typical devices, including: configuration, ARM9, no wait states).
    [Show full text]
  • SEGGER — the Embedded Experts It Simply Works!
    SEGGER — The Embedded Experts It simply works! Buyout licensing for Embedded Studio No license server, no hardware dongle Monheim, Germany – November 26 th, 2018 It only takes two minutes to install: With unlimited evaluaton and the freedom to use the sofware at no cost for non-commercial purposes, SEGGER has always made it easy to use Embedded Studio. In additon to this and by popular demand from developers in larger corporatons, SEGGER introduces a buyout licensing opton that makes things even easier. The new buyout opton allows usage by an unlimited number of users, without copy protecton, making it very easy to install and use the sofware anywhere: In the ofce, on the road, at customer's site or at home. No license server, no hardware dongle. Developers can fully concentrate on what they do and like best and what they are paid for: Develop sofware rather than deal with copy protecton issues. Being available for Windows, macOS and Linux, it reduces the dependencies on any third party. It is the perfect choice for mid-size to large corporatons with strict licensing policies. In additon to that, Embedded Studio's source code is available. "We are seeing more and more companies adoptng Embedded Studio as their Development Environment of choice throughout their entre organizaton. Listening to our customers, we found that this new opton helps to make Embedded Studio even more atractve. Easier is beter", says Rolf Segger, Founder of SEGGER. Get more informaton on the new SEGGER Embedded Studio at: www.segger.com/embedded-studio.html ### About Embedded Studio SEGGER — The Embedded Experts It simply works! Embedded Studio is a leading Integrated Development Environment (IDE) made by and for embedded sofware developers.
    [Show full text]
  • ARM Roadmap Spring 2017
    ARM Roadmap Spring 2017 Robert Boys [email protected] Version 9.0 Agenda . Roadmap . Architectures ARM1™ die . Issues . What is NEW ! . big.LITTLE™ . 64 Bit . Cortex®-A15 . 64 BIT . DynamIQ 3 © ARM 2017 In the Beginning… . 1985 32 years ago in a barn.... 12 engineers . Cash from Apple and VLSI . IP from Acorn Computers . Proof of concept . No patents, no independent customers, product not ready for mass market. A barn, some energy, experience and belief: “We’re going to be the Global Standard” 4 © ARM 2017 The Cortex Processor Roadmap in 2008 Application Real-time Microcontroller Cortex-A9 Cortex-A8 ARM11 Cortex-R4F ARM9 Cortex-R4 ARM7TDMI ARM7 Cortex-M3 SC300 Cortex-M1 5 © ARM 2017 5 Cortex-A73 ARM 2017 Processor Roadmap Cortex-A35 Cortex-A32 Cortex-A72 Cortex-A57 ARM 7, 9, 11 Cortex-A17 Application Cortex-A53 Cortex-A15 Real-time Not to scale to Not Cortex-A9 (Dual) Microcontroller Cortex-A9 (MPCore) Cortex-A8 Cortex-A7 ARM11(MP) Cortex-A5 MMU ARM926EJ-S Cortex-R52 No MMU Cortex-R8 200+ MHz Cortex-R7 ARM9 Cortex-R5 Cortex-R4 Cortex-M7 200+ MHz Cortex-M33 ARM7TDM 72 – 150 + MHz Cortex-M4 Cortex-M3 ARM7I SC300 Cortex-M23 DesignStart™ Cortex-M1 SC000 Cortex-M0+ Cortex-M0 6 © ARM 2017 6 Versions, cores and architectures ? Family Architecture Cores ARM7TDMI ARMv4T ARM7TDMI(S) ARM9 ARM9E ARMv5TE ARM926EJ-S, ARM966E-S ARM11 ARMv6 (T2) ARM1136(F), 1156T2(F)-S, 1176JZ(F), ARM11 MPCore™ Cortex-A ARMv7-A Cortex-A5, A7, A8, A9, A12, A15, A17 Cortex-R ARMv7-R Cortex-R4(F), Cortex-R5, R7, R8 … Cortex-M ARMv7-M Cortex-M3, M4, M7 (M7 is ARMv7-ME) ARMv6-M Cortex-M1, M0, M0+ NEW ! ARMv8-A 64 Bit: Cortex-A35/A53/57/A72 Cortex-A73 Cortex-A32 NEW ! ARMv8-R 32 Bit: Cortex-R52 NEW ! ARMv8-M 32 Bit: Cortex-M23 & M33 TrustZone® 7 © ARM 2017 What is New ? DynamIQ ! .
    [Show full text]
  • J-Flash User Guide of the Stand-Alone Flash Programming Software
    J-Flash User guide of the stand-alone flash programming software Document: UM08003 Software Version: 7.50 Date: July 1, 2021 A product of SEGGER Microcontroller GmbH www.segger.com 2 Disclaimer Specifications written in this document are believed to be accurate, but are not guaranteed to be entirely free of error. The information in this manual is subject to change for functional or performance improvements without notice. Please make sure your manual is the latest edition. While the information herein is assumed to be accurate, SEGGER Microcontroller GmbH (SEG- GER) assumes no responsibility for any errors or omissions. SEGGER makes and you receive no warranties or conditions, express, implied, statutory or in any communication with you. SEGGER specifically disclaims any implied warranty of merchantability or fitness for a particular purpose. Copyright notice You may not extract portions of this manual or modify the PDF file in any way without the prior written permission of SEGGER. The software described in this document is furnished under a license and may only be used or copied in accordance with the terms of such a license. © 2004-2018 SEGGER Microcontroller GmbH, Monheim am Rhein / Germany Trademarks Names mentioned in this manual may be trademarks of their respective companies. Brand and product names are trademarks or registered trademarks of their respective holders. Contact address SEGGER Microcontroller GmbH Ecolab-Allee 5 D-40789 Monheim am Rhein Germany Tel. +49-2173-99312-0 Fax. +49-2173-99312-28 E-mail: [email protected] Internet: www.segger.com J-Flash User Guide (UM08003) © 2004-2018 SEGGER Microcontroller GmbH 3 Manual versions This manual describes the current software version.
    [Show full text]
  • Nexus Based Multi-Core Debug
    Nexus Based Multi-Core Debug Dr. Neal Stollon MIPS Technologies / First Silicon Solutions [email protected] Rich Collins Freescale Semiconductor [email protected] Impact of Debug Strategy Copyright © 2003 Novas Software, Inc. Yes! but. half of what??? Copyright © 2003 Novas Software, Inc. Prototype silicon to production Debug cost can get even bigger for new sets release is 6-9 months. of debug problems for multi-core designs Much of cost of debug driven by architecture limitations and debug learning curve But what if SoC internals are more visible, accessible? Debug implementations become standardized ? SoC Debug Evolution ICE BDM JTAG Embedded Multi-Core Embedded (Scan, BIST Processor / System Debug Run Control) Logic Trace 50K Platform SoC (Multi-Core) 20K SoC Debug- (RISC+IP Nexus +RAM) Difficulty 8K ASICS System FPGA Domain (gates/pins) (PLD+RISC IP) Embedded 2.5K Systems Single FPGAs 1K processor 1980s 1990s 2000s The New Frontier Embedded Debug Complexity keeps increasing • Gates increase geometrically - Pins increase linearly • Significant debug difficulties for leading architectures • More complex debug needs better Instrumentation What is Nexus? • Nexus is a standard for industry level instrumentation with real time interface for embedded system debug • “Nexus” is synonymous with the IEEE-ISTO 5001 std. • Supported by over 20 Member Companies • Specification freely available at http://www.nexus5001.org • Nexus is a toolbox of defined ways for processor debug: • Defines JTAG and Auxiliary bus debug interfaces • Defines simple
    [Show full text]
  • Chapter 1 Microcontrollers
    Chapter 1 Microcontrollers: Yesterday, Today, and Tomorrow 1.1 Defining Microcontrollers It is said that from the definition everything true about the con- cept follows. Therefore, at the outset let us take a brief review of how the all-pervasive microcontroller has been defined by various technical sources. A microcontroller (or MCU) is a computer-on-a-chip used to con- trol electronic devices. It is a type of microprocessor emphasizing self-sufficiency and cost-effectiveness, in contrast to a general-purpose microprocessor (the kind used in a PC). A typical microcontroller con- tains all the memory and interfaces needed for a simple application, whereas a general purpose microprocessor requires additional chips to provide these functions. .(Wikipedia [1]) A highly integrated chip that contains all the components compris- ing a controller. Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers. Unlike a general-purpose computer, which also includes all of these components, a microcontroller is designed for a very specific task – to control a particular system. As a result, the parts can be simplified and reduced, which cuts down on production costs. (Webopedia [2]) A {microprocessor} on a single {integrated circuit} intended to ope- rate as an {embedded} system. As well as a {CPU}, a microcontroller typically includes small amounts of {RAM} and {PROM} and timers and I/O ports. .(Define That [3]) A single chip that contains the processor (the CPU), non-volatile memory for the program (ROM or flash), volatile memory for input and output (RAM), a clock and an I/O control unit.
    [Show full text]
  • ARM Microcontrollers for Space Applications
    ARM Microcontrollers for Space Applications Emre Ozer, R&D Nov 4, 2010 1 Outline .What does ARM do? .ARM CPU Portfolio .ARM Embedded CPUs and Microcontrollers .ARM in Space/Aerospace 2 What does ARM do? . Designs and Licenses IP Software 3 The ARM Business Model . Global leader in the development of semiconductor IP . R&D outsourcing for semiconductor companies . Innovative business model yields high margins . Upfront license fee – flexible licensing models . Ongoing royalties – typically based on a percentage of chip price . Technology reused across multiple applications . Long-term, scalable growth markets Base of over 660 licenses Grows by 60-90 every year More than 220 potential royalty payers ~4 billion ARM technology based chips each year 4 ARM Connected Community – 700+ Connect, Collaborate, Create – accelerating innovation 5 ARM Classic CPU Portfolio . Classic, market-proven processor technology . 220+ partners ARMv6 x1-4 ARM11™ MPCore™ . 660+ licenses ARM1176JZ(F)-S™ ARM1156T2(F)-S™ . 18Bu+ shipped ARM1136J(F)-S™ ARMv5 ARM968E-S™ ARM926EJ-S™ ARM946E-S™ ARM7EJ-S™ ARMv4 ARM922T™ SC100™ ARM7TDMI(S)™ 6 ARM Cortex Advanced Processors Architectural innovation, compatibility across diverse application spectrum . ARM Cortex-A family: x1-4 Cortex-A9 . Applications processors for smartphone, ...2GHz mobile computing, infrastructure, consumer Cortex-A8 electronics, netbooks and servers x1-4 Cortex-A5 ARM Cortex-R family: . Cortex-R4(F) . Embedded processors for real-time signal processing, hard drives and Cortex-M4 SC300™ mission-critical
    [Show full text]
  • ARM Low-Power Processors and Architectures
    ARM Low-power Processors and Architectures Dan Millett Verification Enablement Processor Division 1 Agenda . Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines System Design Development Tools 2 ARM Ltd . Founded in November 1990 . Spun out of Acorn Computers . Initial funding from Apple, Acorn and VLSI . Designs the ARM range of RISC processor cores . Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers . ARM does not fabricate silicon itself . Also develop technologies to assist with the design- in of the ARM architecture . Software tools, boards, debug hardware . Application software . Bus architectures . Peripherals, etc 3 ARM’s Activities Connected Community Development Tools Software IP Processors memory System Level IP: Data Engines SoC Fabric 3D Graphics Physical IP 4 ARM Connected Community – 700+ 5 5 Huge Range of Applications IR Fire Detector Exercise Utility Intelligent Machines Energy Efficient Appliances Intelligent toys Meters Vending Tele-parking Equipment Adopting 32-bit ARM Microcontrollers 6 How many ARM’s Do You Have? Mobile phones Smartphones Mobile Computers Digital TVs Ultra Low Cost Ultra Low Cost Ultra Low Cost ~100% 3x 100% 5x 100% 35% market share market share market share market share Disk Drives PC Peripherals Cars Microcontrollers Ultra Low Cost Ultra Low Cost Ultra Low Cost Ultra Low Cost ~75% 40% 5x 50% 35% market share market share market share market share 7 Huge Opportunity For ARM Technology 25+ 100+ billion billion cores accumulated
    [Show full text]
  • Cubesat Processor Radiation Efforts
    National Aeronautics and Space Administration NEPP Electronic Technology Workshop June 17-19, 2014 Cubesat Processor Radiation Efforts Steven M. Guertin Jet Propulsion Laboratory / California Institute of Technology Pasadena, CA This work was performed at the Jet Propulsion Laboratory, California Institute of Technology, Under contract with the National Aeronautics and Space Administration (NASA) This work was funded by the NASA Electronic Parts and Packaging Program (NEPP) Copyright 2014 California Institute of Technology. Government Sponsorship is acknowledged. To be presented by Steven M. Guertin at the 5th NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop June 17-19, 2014, NASA GSFC, Greenbelt, MD. <#> National Aeronautics and Space Administration Outline • Motivation • Microcontrollers – Current Cubesat Devices – Selection Efforts – MSP430 SEE and TID – PIC SEE and TID • Microprocessors – Expected Use Soon – Selection – Snapdragon Efforts – Atom • Future Work To be presented by Steven M. Guertin at the 5th NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop June 17-19, 2014, NASA GSFC, Greenbelt, MD. 2 National Aeronautics and Space Administration Key Issues • Common paradigm of Cubesat processing – Small – Low Power – Microcontroller-like – A couple common processors/microcontrollers • Looking forward – We expect that processing desire will increase – Instruments may become more computation intensive – Primary processors may migrate for more computation • Approach for improving mission assurance – Determine mission assurance issues for current-generation microcontrollers/microprocessors– focus on SEL/gross SEE, and TID (Primarily LEO and GEO/GCR environments) – Build repository of knowledge for devices for future use To be presented by Steven M. Guertin at the 5th NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop June 17-19, 2014, NASA GSFC, Greenbelt, MD.
    [Show full text]