Insider's Guide STM32

The Insider’s Guide To The STM32 ARM®Based Microcontroller An Engineer’s Introduction To The STM32 Series Version 1.8 www.hitex.com Published by Hitex (UK) Ltd. ISBN: 0-9549988 8 First Published February 2008 Second Edition February 2009 Hitex (UK) Ltd. Sir William Lyons Road University Of Warwick Science Park Coventry, CV4 7EZ United Kingdom Credits Author: Trevor Martin Illustrator: Sarah Latchford Editors: Michael Beach, Alison Wenlock Cover: Wolfgang Fuller Acknowledgements The author would like to thank Matt Saunders and David Lamb of ST Microelectronics for their assistance in preparing this book. © Hitex (UK) Ltd., 22/10/2009 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical or photocopying, recording or otherwise without the prior written permission of the Publisher. Contents Contents 1. Introduction 4 1.1 So What Is Cortex?.....................................................................................4 1.2 A Look At The STM32 ................................................................................5 1.2.1 Sophistication .............................................................................................7 1.2.2 Safety .........................................................................................................7 1.2.3 Security.......................................................................................................7 1.2.4 Software Development ...............................................................................7 1.2.5 The STM32 Family .....................................................................................8 2. Cortex Overview 11 2.1 ARM Architectural Revision ......................................................................11 2.2 Cortex Processor And Cortex CPU...........................................................12 2.3 Cortex CPU ..............................................................................................12 2.3.1 Pipeline.....................................................................................................12 2.3.2 Programmer’s Model ................................................................................12 2.3.3 CPU Operating Modes..............................................................................15 2.3.4 Thumb-2 Instruction Set ...........................................................................16 2.3.5 Memory Map.............................................................................................17 2.3.6 Unaligned Memory Accesses ...................................................................18 2.3.7 Bit Banding ...............................................................................................18 2.4 Cortex Processor......................................................................................20 2.4.1 Busses......................................................................................................20 2.4.2 Bus Matrix.................................................................................................20 2.4.3 System Timer ...........................................................................................21 2.4.4 Interrupt Handling .....................................................................................21 2.4.5 Nested Vector Interrupt Controller ............................................................22 2.5 Power Modes............................................................................................28 2.5.1 Entering Low Power Mode........................................................................28 2.5.2 CoreSight Debug Support.........................................................................28 2.6 Cortex Microcontroller Software Interface Standard .................................31 3. Getting It Working 34 3.1 Package Types and Footprints .................................................................34 3.2 Power Supply ...........................................................................................34 3.3 Reset Circuit .............................................................................................35 3.4 Oscillators.................................................................................................36 3.4.1 High Speed External Oscillator.................................................................36 3.4.2 Low Speed External Oscillator..................................................................36 3.4.3 Clock Output.............................................................................................36 3.4.4 Boot Pins And Field Programming............................................................36 3.4.5 Boot Modes ..............................................................................................37 3.4.6 Debug Port ...............................................................................................37 4. STM32 System Architecture 39 4.1 Memory Layout.........................................................................................40 4.2 Maximising Performance ..........................................................................41 4.2.1 Phase Locked Loop..................................................................................42 4.2.2 FLASH Buffer ...........................................................................................43 4.2.3 Direct Memory Access..............................................................................43 5. Peripherals 49 © Hitex (UK) Ltd. Page 1 Contents 5.1 General Purpose Peripherals ...................................................................49 5.1.1 General Purpose IO..................................................................................49 5.1.2 External Interrupts ....................................................................................51 5.1.3 ADC..........................................................................................................52 5.1.4 Digital To Analogue Converter..................................................................58 5.1.5 General Purpose And Advanced Timers ..................................................60 5.1.6 RTC And Backup Registers......................................................................67 5.1.7 Backup Registers And Tamper Pin...........................................................67 5.1.8 Cyclic Redundancy Check Calculation Unit..............................................68 5.2 Connectivity ..............................................................................................68 5.2.1 SPI............................................................................................................68 5.2.2 Inter-Integrated Circuit Sound I2S Peripheral ...........................................69 5.2.3 I2C............................................................................................................70 5.2.4 USART .....................................................................................................72 5.3 Can And USB Controller...........................................................................73 5.3.1 CAN Controller .........................................................................................73 5.4 USB ..........................................................................................................75 6. Low Power Operation 78 6.1 RUN Mode................................................................................................78 6.1.1 Prefetch Buffer And Half-Cycle Mode.......................................................78 6.2 Low Power Modes ....................................................................................79 6.2.1 SLEEP ......................................................................................................79 6.2.2 STOP Mode..............................................................................................80 6.3 Standby ....................................................................................................81 6.4 Backup Region Power Consumption ........................................................81 6.5 Debug Support .........................................................................................81 7. Safety Features 83 7.1 Reset Control............................................................................................83 7.2 Power Voltage Detect...............................................................................83 7.3 Clock Security System..............................................................................84 7.4 Watchdogs................................................................................................85 7.4.1 Windowed Watchdog................................................................................85 7.4.2 Independent Watchdog.............................................................................86 7.5 Peripheral Features ..................................................................................87 7.5.1 GPIO Port Locking....................................................................................87 7.5.2 Analogue Watchdog .................................................................................87 7.5.3 Break Input ...............................................................................................87 8. Memory Regions 89 8.1 The FLASH Module ..................................................................................89

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