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Introducing 3D Xpoint™ Memory

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Introducing 3D Xpoint™ Memory Rigel V I S I O N O F P R O C E S S O R – M E M O R Y S Y S T E M S MICRO 48 J. Thomas Pawlowski, Chief Technologist, Fellow [email protected] ©2015 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. December 8, 2015 Statements regarding products, including regarding their features, availability, functionality, or compatibility, Title Slide - White are provided for informational purposes only and do not modify the warranty, if any, applicable to any product. Drawings may not be to scale. Micron, the Micron logo, and all other Micron trademarks are the Alternate layout property of Micron Technology, Inc. All other trademarks are the property of their respective owners. for first slide in the deck. Memory diversity . 3D XPoint™ Memory . Some scaling observations . Changing Relationships . Unabated performance . Micron Automata Processor pressure . Abstraction and Future . Memory Technologies Systems . Emerging Memory . 11 Key Points Agenda Two-column layout, © 2015 Micron Technology, Inc. December 8, 2015 to be used with any number of items. Memory Diversity December 8, 2015 White Segue Diversified Memory Markets Automotive Storage Graphics / Consumer Networks Server Mobile Personal Computing IMM Title Only Includes only the title and subtitle, with a large open © 2015 Micron Technology, Inc. December 8, 2015 space in the middle of the slide. Smartphones and Tablets Enterprise and Cloud Micron Portfolio Micron Portfolio Server Modules 4-32Gb LPDDR4 • Up to 128GB module densities • DDR4 solutions driving higher performance • Multiple package options • Load Reduced options for higher system capacity • 4x provides 4GB density Enterprise SSD • LPDDR4 2x bandwidth LPDDR3 • Enabled with high performance MLC NAND • LPDDR4 35% power savings over LPDDR3 • Expanding portfolio of SAS and PCIe eMMC 5.x • Partnerships enable efficient go to market • Small package options NVDIMM • Integrated DRAM/NAND Module • 3x random Read/Write performance • Outstanding latency and bandwidth • 2x sequential Read/Write performance • Excellent endurance capability • Wide temperature range tolerance and high Hybrid Memory Cube reliability • Best-in-class bandwidth solution eMCP + LPDDR3 • 70% less energy per bit • Industry leading reliability • Attractive package/density options 3D XPoint • 2x bandwidth over eMCP+LP2 • First new memory technology in over 25 years Title Only • Quick time-to-market for system qualification • 1,000x faster than NAND efforts Includes only the • 10x higher density than conventional memory title and subtitle, with a large open © 2015 Micron Technology, Inc. December 8, 2015 space in the middle of the slide. Networking Client Micron Portfolio Micron Portfolio On-Board Memory DRAM Modules • Up to 16Gb per package • Error correction for data integrity • Various package options • VLP and custom form factors • Soldered-on-board for thin profile • Leading-edge and legacy options • DDR4, DDR3L and LPDDR3/4 RLDRAM Client Modules • Low latency • Up to 16GB density • Fast random access • Thin form factor • Specialized x9, x18, and x36 configurations • 1.35V DDR3L at 10% lower power than standard DDR3 • DDR4 memory Hybrid Memory Cube • Best-in-class bandwidth solution Serial NOR • Dependable BIOS • Provides the bandwidth of as many as 144 • Secure Boot DDR3 components Client SSD eUSB • Vs. HDD: Superior $/IOPS and IOPS/watt • Faster boot and bandwidth • Firmware and OS management • Lower dB, ns, W, oz, cu.in. • User tracking data Title Only • Encryption, security Includes only the title and subtitle, • 100x performance with a large open © 2015 Micron Technology, Inc. December 8, 2015 space in the middle of the slide. Some Scaling Observations December 8, 2015 White Segue DRAM Array and Logic Transistors per square mm . Suggests using 1.339x / 1 year memory wafers 1.793x / 2 year 2x / 2.4 years more extensively 1.316x / 1 year than logic, 1.733x / 2 year widening gap 2x / 2.5 year . Logic transistor curve based only on Intel Logic production start dates transistor density to maintain harmony growing at of methodologies slower rate (excluding Dates rounded down on-die SRAM) to year – Note that this Title and Content The primary layout does not show COST Source: JTPawlowski, Micron used for standard slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts. Most Dense Use of Logic Technology is Memory 22nm 14nm 6T HDC SRAM Intel 190.1 F2 Intel 14.5Mb/mm2 254.6 F2 6T LVC SRAM IBM dens-perf 297.5 F2 Intel 300 F2 6T HPC SRAM Intel 360.2 F2 8T SRAM Intel 5.1Mb/ mm2 eDRAM IBM 53.7 F2 IBM 89.1 F2 Intel Macro 17.5Mb/mm2 59.9 F2 IBM Macro 18.7Mb/mm2 • Source: various ISSCC and VLSI Symposium Proceedings • Intel 14nm SRAMs • Compare to DRAM now constant 6-7F2 • SRAM scaling poorly • eDRAM appears worse – watch future scaling Some density and energy benefit for now Title and Content The primary layout • DRAM is challenging but scaling far better than used for standard SRAM and eDRAM slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts. Intel HC SRAM and IBM eDRAM Cell Scaling Area [nm2] vs. Node [nm] . SRAM 2x relative size since 90nm, eDRAM 2.7x since 45nm, macros scaling worse . Contrast: smallest nFET 255 F2 available in 14nm: 89 F2 Intel 25F2 Micron 4F2 Title and Content The primary layout used for standard slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts. Memory Growing As Percentage Area in Logic Chips Title and Content The primary layout Much of this area can be displaced by cheaper process technology used for standard slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts. Unabated Performance Pressure December 8, 2015 White Segue • Micron 3D NAND . Source: ISSCC 2015 Trends – Logic chips only Title and Content The primary layout used for standard . Memory transistor count dwarfs logic (8Gb DRAM ~10B, latest NAND ~400B) slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts. Lately ~6% / year • Source: ISSCC 2015 Trends Title Only Includes only the title and subtitle, with a large open © 2015 Micron Technology, Inc. December 8, 2015 space in the middle of the slide. Single Core IPC Gain vs. Introduction Year for Intel Xeon Family IPC average gain 5.8% / year . Compiled from Wikipedia and other Title and Content The primary layout internet articles Sep used for standard 2015 by JTPawlowski slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts. 100 GPCPU 90 Core Count grows at 19% / year 80 with high variability 70 60 GPGPU Core Count grew at 42% / year But now slowing to 32% / year (JTP estimates) • ISSCC 2015 Trends, plus: 2014 Cavium 48 core, 2015 EZChip/Tilera 100 core, Title and Content Knights Landing ~72 Atom cores, Phytium 64 ARM cores. The primary layout used for standard • Off the chart: Kalray and REX 256 cores, GPUs e.g. Nvidia TitanX 3,360 cores slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts. Impressive Gains in Memory Throughput System Throughput a.u. vs. Time HMC has 41X throughput of equal bit-count of DIMMs, 2016 RLDRAM3 1.06 f RLDRAM2 x 1.06 IPC 4 DIMMs x 3 DIMMs 1.19 core count 2 DIMMs Title Only Includes only the title and subtitle, Source: JTPawlowski, Micron with a large open © 2015 Micron Technology, Inc. December 8, 2015 space in the middle of the slide. Memory Technologies December 8, 2015 White Segue In-Package Memory Bandwidth Efficiency Form Factor • Unprecedented memory bandwidth keeps pace with multiple CPU cores Memory Stack • Increased savings in energy/bit • TSV technology with logic layer allows roadmap to higher performance and lower energy • Compelling RAS features Controller / SoC Functionality . >31 Cores Title and Content The primary layout Integrated Fabric used for standard Processor Package slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts. The Innovative Hybrid Memory Cube Revolutionary Approach Unparalleled Performance . Evolutionary DRAM roadmaps hit . Provides 15X the bandwidth of limitations of bandwidth and a DDR3 module power efficiency . Uses 70% less energy per bit than existing memory . Micron introduces a new class of technologies memory: Hybrid Memory Cube . Reduces the memory footprint . Unique combination of DRAMs on by nearly 90% compared to Logic addresses the memory wall, today’s RDIMMs scalability and RAS How did we do it? Key Applications . Micron-designed logic controller . Data packet processing, data packet . High speed link to CPU buffering, and storage applications . Massively parallel “Through Silicon Title Only . Enterprise and high performance Via” connection to DRAM Includes only the title and subtitle, computing applications with a large open © 2015 Micron Technology, Inc. December 8, 2015 space in the middle of the slide. Impacts of DRAM Process Complexity Complexity comparison for enablement • Large increase in number of process steps to enable shrink of ~100% bits/wafer increase • Conversion Capital Expenditure scales with number of steps 50nm 30nm 30nm 20nm • Significant reduction in wafer output per existing cleanroom area Number of Number of non-Litho Steps Cleanroom Space Mask Levels per Critical Mask Level per Wafer Out >35% >110% >80% ~10% ~15% ~40% Title and Content The primary layout used for standard 50nm 30nm 20nm 50nm 30nm 20nm 50nm 30nm 20nm slides. The placeholder can be © 2015 Micron Technology, Inc. December 8, 2015 used to create text, tables, or charts.
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