DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 Mhz Check for Samples: DS90CR217

DS90CR217 www.ti.com SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz Check for Samples: DS90CR217 1FEATURES DESCRIPTION The DS90CR217 transmitter converts 21 bits of 2• 20 to 85 MHz Shift Clock Support CMOS/TTL data into three LVDS (Low Voltage • 50% Duty Cycle on Receiver Output Clock Differential Signaling) data streams. A phase-locked • Best-in-Class Set & Hold Times on TxINPUTs transmit clock is transmitted in parallel with the data • Low Power Consumption streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and • ±1V Common-Mode Range (Around +1.2V) transmitted. At a transmit clock frequency of 85 MHz, • Narrow Bus Reduces Cable Size and Cost 21 bits of TTL data are transmitted at a rate of 595 • Up to 1.785 Gbps Throughput Mbps per LVDS data channel. Using a 85 MHz clock, • Up to 223 Mbytes/sec Bandwidth the data throughput is 1.785 Gbit/s (223 Mbytes/sec). • 345 mV (typ) Swing LVDS Devices for Low EMI The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and • PLL Requires No External Components cable size problems associated with wide, high-speed • Rising Edge Data Strobe TTL interfaces. • Compatible with TIA/EIA-644 LVDS Standard • Low Profile 48-Lead TSSOP Package Block Diagram Figure 1. DS90CR217 See Package Number DGG0048A 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. DS90CR217 SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 www.ti.com Connection Diagrams Figure 2. Typical Application These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90CR217 DS90CR217 www.ti.com SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 Absolute Maximum Ratings (1)(2)(1) Supply Voltage (VCC) −0.3V to +4V CMOS/TTL Input Voltage −0.5V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 4 sec.) +260°C Maximum Package Power Dissipation @ +25°C DGG0048A (TSSOP) Package: DS90CR217 1.98 W Package Derating DS90CR217 16 mW/°C above +25°C ESD Rating (HBM, 1.5kΩ, 100pF) > 7kV (EIAJ, 0Ω, 200pF) > 700V Latch Up Tolerance @ 25°C > ±300mA (1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation. Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −10 +25 +70 °C Receiver Input Range 0 2.4 V Supply Noise Voltage (VCC) 100 mVPP Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit s CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA −0.7 −1.5 V 9 IIN Input Current VIN = 0.4V, 2.5V or VCC +1.8 +15 μA VIN = GND −10 0 μA IOS Output Short Circuit Current VOUT = 0V −60 −120 mA LVDS DRIVER DC SPECIFICATIONS VOD Differential Output Voltage RL = 100Ω 250 290 450 mV ΔV Change in V between Complimentary Output OD OD 35 mV States Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS90CR217 DS90CR217 SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit s (1) VOS Offset Voltage 1.12 1.25 1.37 V 5 5 ΔV Change in V between Complimentary Output OS OS 35 mV States IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω −3.5 −5 mA IOZ Output TRI-STATE Current PWR DWN = 0V, VOUT = 0V or VCC ±1 ±10 μA TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case (with RL = 100Ω, f = 33 MHz 28 42 mA Loads) C = 5 pF, L f = 40 MHz 29 47 mA Worst Case Pattern (Figure 3 and Figure 4) f = 66 MHz 34 52 mA f = 85 MHz 39 57 mA ICCTZ Transmitter Supply Current Power Down PWR DWN = Low Driver Outputs in TRI-STATE 10 55 μA under Powerdown Mode (1) VOS previously referred as VCM. Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time (Figure 4) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 4) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 5) 1.0 6.0 ns TPPos0 Transmitter Output Pulse Position for Bit0 (Figure 12) f = 85 MHz −0.20 0 0.20 ns TPPos1 Transmitter Output Pulse Position for Bit1 1.48 1.68 1.88 ns TPPos2 Transmitter Output Pulse Position for Bit2 3.16 3.36 3.56 ns TPPos3 Transmitter Output Pulse Position for Bit3 4.84 5.04 5.24 ns TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6.72 6.92 ns TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8.40 8.60 ns TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10.08 10.28 ns TCIP TxCLK IN Period (Figure 7) 11.76 T 50 ns TCIH TxCLK IN High Time (Figure 7) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 7) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN (Figure 7) f = 85 MHz 2.5 ns THTC TxIN Hold to TxCLK IN (Figure 7) 0 ns TCCD TxCLK IN to TxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 8) 3.8 6.3 ns TPLLS Transmitter Phase Lock Loop Set (Figure 9) 10 ms TPDD Transmitter Powerdown Delay (Figure 11) 100 ns TJIT TxCLK IN Cycle-to-Cycle Jitter 2 ns 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90CR217 DS90CR217 www.ti.com SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 AC Timing Diagrams Figure 3. “Worst Case” Test Pattern Figure 4. DS90CR217 (Transmitter) LVDS Output Load and Transition Times Figure 5. D590CR217 (Transmitter) Input Clock Transition Time Measurements at VDIFF = 0V TCCS measured between earliest and latest LVDS edges TxCLK Differential Low→High Edge Figure 6. DS90CR217 (Transmitter) Channel-to-Channel Skew Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DS90CR217 DS90CR217 SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 www.ti.com Figure 7. DS90CR217 (Transmitter) Setup/Hold and High/Low Times Figure 8. DS90CR217 (Transmitter) Clock In to Clock Out Delay Figure 9. DS90CR217 (Transmitter) Phase Lock Loop Set Time Figure 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR217) 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90CR217 DS90CR217 www.ti.com SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 Figure 11. Transmitter Powerdown Delay Figure 12. Transmitter LVDS Output Pulse Position Measurement Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS90CR217 DS90CR217 SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 www.ti.com APPLICATIONS INFORMATION Table 1. DS90CR217 PIN DESCRIPTIONS — CHANNEL LINK TRANSMITTER Pin Name I/O No. Description TxIN I 21 TTL level input. TxOUT+ O 3 Positive LVDS differential data output. TxOUT− O 3 Negative LVDS differential data output. TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DWN I 1 TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at power down. See Applications Information section. VCC I 4 Power supply pins for TTL inputs. GND I 5 Ground pins for TTL inputs. PLL VCC I 1 Power supply pins for PLL. PLL GND I 2 Ground pins for PLL. LVDS VCC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and shorter cable lengths (< 2m), the media electrical performance is less critical. For higher speed/long distance applications the media's performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at distances as great as 5 meters and with the maximum data transfer of 1.785 Gbit/s.

Load more