DOCSLIB.ORG

Analytical Evaluation of Energy and Throughput for Multilevel Caches

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Analytical Evaluation of Energy and Throughput for Multilevel Caches Analytical Evaluation of Energy and Throughput for Multilevel Caches Muhammad Yasir Qadri, Klaus D. McDonald-Maier School of Computer Science and Electronic Engineering University of Essex, Colchester CO4 3SQ, UK Email: [email protected], [email protected] Abstract--With the increase of processor-memory II. RELATED WORK performance gap, it has become important to gauge the performance of cache architectures so as to evaluate their This section presents the related research findings impact on energy requirement and throughput of the in the area of cache performance estimation and its system. Multilevel caches are found to be increasingly usage for various applications. prevalent in the high-end processors. Additionally, the Lim et al. [5] have proposed a set of equations to recent drive towards multicore systems has necessitated estimate accurately worst case time analysis (WCTA) the use of multilevel cache hierarchies for shared memory for RISC processors. Their models detail the architectures. This paper presents simplified and pipelining, instruction cache and data cache effects on accurate mathematical models to estimate the energy consumption and the impact on throughput for multilevel real-timeliness of the system. Another reference of caches for single core systems. timing models is the work by Peuto et al. [6], in which the authors proposed an instruction timing model Keywords-cache mathematical models; energy; accounting cache effects. Taha et al. [7] presented an throughput; multilevel-cache instruction throughput model of Superscalar processors. Their model include parameters such as I. INTRODUCTION superscalar width, depth of pipeline, instruction fetch Cache memories were primarily introduced to mechanism (in-order/out-of-order), branch predictor, bridge the gap between processor and memory central issue window width, number of functional units performance. With the processors operating at their latencies and throughputs, re-order buffer width remarkable speeds and DRAM speeds operating at and cache size and latency etc. Their model resulted in fraction of that, multilevel cache hierarchies provided a errors up to 5.5% when compared to the SimpleScalar viable solution to keep up the trend of the Dave simulator [8]. Wada et al. [9] proposed detailed circuit House’s revision of Moore’s law predicting that level analytical access time model for on-chip cache computer performance will double every 18 months memories. The model takes inputs such as number of [1]. The mathematical models presented in this paper tag/data array per word/bit line etc. On comparing with analyze the energy consumption and throughput for SPICE results the model gives 20% error for an 8 ns multilevel data cache using PowerPC750, and access time cache memory. UltraSPARC-II processors. The throughput model was Simunic et al. [10] proposed analytical models for validated using SIMICS full system simulator and energy estimation in embedded systems. The per cycle energy model using per cycle energy consumption energy model presented in their work comprises statistics presented in the processor datasheet. The components such as energy consumption of processor, models are multilevel extension of the single level memory, interconnects and pins, DC-to-DC converters models presented by the authors in [2-4]. The aim of and level two (L2) cache. The model validation was this research is to propose simplified mathematical performed using integrated simulator of ARM SDK models for multilevel cache so in the future [11]. This was found to be within 5% of the hardware multiprocessor configurations could be evaluated using measurements for the same operating frequency. The them, in a resource constrained environment such as models presented in their work holistically analyze the the system itself. embedded system power and do not estimate energy The rest of this paper is divided into five sections. consumption for individual components of a processor. In the following section related work is discussed. The Kamble et al. in [12] also presented detailed cache energy and throughput models for multilevel cache are energy model. The analytical models for conventional introduced in section 3. In the fourth section the caches were found to be accurate to within 2% error. models are validated using a two level cache hierarchy, However, the technique over–predicts the power and the final section presents the conclusion. dissipations of low–power caches by as much as 30%. 1 Revisiting the models in [13] the authors found them to a full system simulation tool. The simulator is targeted be accurate within 20% for low power caches upon to provide accurate timing profile, but presently does comparing with their designed simulator CAche Power not support energy profiling of the target platforms. Estimator (CAPE) for the simulated execution of Austin et al. [8] presented SimpleScalar another full several SPEC95 benchmarks. Li et al. [14] proposed a system virtualization platform. The tool uses an full system energy model comprising of cache, main execution-driven simulation technique that reproduces memory, and software energy components. Their work a device’s internal operation. Exploiting SimpleScalar also details a framework to assess and optimize energy interface, Brooks et al. [20] developed a tool called dissipation of embedded systems. Tiwari et al. [15] Wattch for architectural level power analysis. It proposed an instruction level energy model estimating maintains accuracy within 10% as compared to results energy consumed in individual pipeline stages. An of circuit level power analysis tools. A further addition identical methodology was applied in [16] by the to this was done by Flores et al. [21] by proposing authors to study the effects of cache enabling and Sim-PowerCMP for chip multiprocessors. The tool disabling. estimates both dynamic and leakage power for CMP A simulator for analyzing cache energy dissipation architectures based on a Linux x86 model of RSIM called CAche Power Estimator (CAPE) was developed [22] presented by Hughes et al. by Kamble et al. based on the mathematical models they proposed [12, 13]. Based on these models another III. THE CACHE ENERGY AND THROUGHPUT MODELS tool named INCAPE was developed by Korkmaz et al. This section presents the energy and throughput [17]. This simulator is capable of estimating energy models for a two-level cache hierarchy. dissipation for complete memory hierarchy including multilevel cache system. Another widely referred, open A. Energy Model source tool is CACTI (cache access and cycle time If , , and is the energy consumed by model) [18] by HP Laboratories Inc. It provides instruction, data and level 2 (L2) cache operations, thorough, near accurate memory access time and is the Energy consumed by the instructions energy estimates. However it is not a trace driven which do not require data memory access, and simulator, so energy consumption resulting in number the leakage energy of the processor, then the total of hits or misses is not accounted for a particular energy consumption of the code in Joules [J] can application. Magnusson et al. [19] presented SIMICS, be defined as, (1) Where, L1 Instruction Cache (2) (3) (4) L1 Data Cache (5) (6) (7) (8) L2 Cache (9) (10) (11) (12) 2 In the above equations , , and calculated by multiplying the number of memory denote the read, write and miss penalty energy accesses with their read and write cycles energy. of the corresponding cache x (i.e. instruction, data or The idle mode leakage energy of the processor L2 cache). The read and write cycle energy per cache can be calculated as access is denoted by and . The , (13) number of data read and write transactions of the cache (including all hits and miss) is denoted by and . Furthermore , , where [Sec] is the total time for which processor denote the L2 cache’s instruction fetch, data read and was idle. data write transactions respectively. The processor’s B. Throughput Model per cycle energy consumption is denoted by ; If , , and is the time taken in instruction, , , and denote the data and level 2 (L2) cache operations, and the read/write miss penalty (in terms of number of cycles) time taken in execution of cache access instructions and their corresponding miss rates. The energy [Sec], and the time taken in consumed in L2 cache to data and code memory is read, write and miss penalty for cache x; then the denoted by and that could also be total time taken by an application could be estimated as (14) Furthermore, L1 Instruction Cache (15) (16) (17) L1 Data Cache (18) (19) (20) (21) L2 Cache (22) (23) (24) (25) and, (26) 3 where , is the time taken per cache TABLE II. CACHE SIMULATOR DATA read and write cycle and is the processor cycle CACTI Data time in seconds [sec]. L1 I-Cache PowerPC750 UltraSPARC II TABLE I. PROCESSOR PARAMETERS Cache Size [KBytes] 32 Cache Size [KBytes] 16 Line Size [Bytes] 32 Line Size [Bytes] 32 Parameter Value Number of Lines 1024 Number of Lines 512 R/W Ports 1 R/W Ports 1 Processor PowerPC750 UltraSPARC II Associativity 8 Associativity 2 Execution mode In-order In-order Miss Penalty[cycles] 7 Miss Penalty[cycles] 10 Clock frequency [MHz] 373.5 168 Read ports 0 Read ports 0 Cycle Time [ns] 2.68 5.95 Write ports 0 Write ports 0 Fabrication Technology [μm] 0.2 0.35 Access Time [ns] 1.82 Access Time [nSec] 2.91 V [V] 2.2 3.3 Cycle Time [ns] 1.04 Cycle Time [nSec] 1.58 dc Read Energy [nJ] 0.725 Read Energy [nJ] 0.49 Operating current IDD [A] 2 9.4 Energy per Cycle [nJ] 11.8 185 MontaVista Operating System Fedora Core 3 L1 D-Cache Linux 2.1 PowerPC750 UltraSPARC II Cache Size [KBytes] 32 Cache Size [KBytes] 16 Line Size [Bytes] 32 Line Size [Bytes] 32 IV. MODEL VALIDATION Number of Lines 1024 Number of Lines 512 To validate the accuracy of the proposed models, R/W Ports 1 R/W Ports 1 Associativity 8 Associativity 2 Virtutech’s SIMICS full system simulator was used to Miss Penalty[cycles] 7 Miss Penalty[cycles] 10 simulate two processor models i.e.
Load more

Recommended publications
  • When Is a Microprocessor Not a Microprocessor? the Industrial Construction of Semiconductor Innovation I
    Ross Bassett When is a Microprocessor not a Microprocessor? The Industrial Construction of Semiconductor Innovation I In the early 1990s an integrated circuit first made in 1969 and thus ante­ dating by two years the chip typically seen as the first microprocessor (Intel's 4004), became a microprocessor for the first time. The stimulus for this piece ofindustrial alchemy was a patent fight. A microprocessor patent had been issued to Texas Instruments, and companies faced with patent infringement lawsuits were looking for prior art with which to challenge it. 2 This old integrated circuit, but new microprocessor, was the ALl, designed by Lee Boysel and used in computers built by his start-up, Four-Phase Systems, established in 1968. In its 1990s reincarnation a demonstration system was built showing that the ALI could have oper­ ated according to the classic microprocessor model, with ROM (Read Only Memory), RAM (Random Access Memory), and I/O (Input/ Output) forming a basic computer. The operative words here are could have, for it was never used in that configuration during its normal life­ time. Instead it was used as one-third of a 24-bit CPU (Central Processing Unit) for a series ofcomputers built by Four-Phase.3 Examining the ALl through the lenses of the history of technology and business history puts Intel's microprocessor work into a different per­ spective. The differences between Four-Phase's and Intel's work were industrially constructed; they owed much to the different industries each saw itselfin.4 While putting a substantial part ofa central processing unit on a chip was not a discrete invention for Four-Phase or the computer industry, it was in the semiconductor industry.
    [Show full text]
  • Outline ECE473 Computer Architecture and Organization • Technology Trends • Introduction to Computer Technology Trends Architecture
    Outline ECE473 Computer Architecture and Organization • Technology Trends • Introduction to Computer Technology Trends Architecture Lecturer: Prof. Yifeng Zhu Fall, 2009 Portions of these slides are derived from: ECE473 Lec 1.1 ECE473 Lec 1.2 Dave Patterson © UCB Birth of the Revolution -- What If Your Salary? The Intel 4004 • Parameters – $16 base First Microprocessor in 1971 – 59% growth/year – 40 years • Intel 4004 • 2300 transistors • Initially $16 Æ buy book • Barely a processor • 3rd year’s $64 Æ buy computer game • Could access 300 bytes • 16th year’s $27 ,000 Æ buy cacar of memory • 22nd year’s $430,000 Æ buy house th @intel • 40 year’s > billion dollars Æ buy a lot Introduced November 15, 1971 You have to find fundamental new ways to spend money! 108 KHz, 50 KIPs, 2300 10μ transistors ECE473 Lec 1.3 ECE473 Lec 1.4 2002 - Intel Itanium 2 Processor for Servers 2002 – Pentium® 4 Processor • 64-bit processors Branch Unit Floating Point Unit • .18μm bulk, 6 layer Al process IA32 Pipeline Control November 14, 2002 L1I • 8 stage, fully stalled in- cache ALAT Integer Multi- Int order pipeline L1D Medi Datapath RF @3.06 GHz, 533 MT/s bus cache a • Symmetric six integer- CLK unit issue design HPW DTLB 1099 SPECint_base2000* • IA32 execution engine 1077 SPECfp_base2000* integrated 21.6 mm L2D Array and Control L3 Tag • 3 levels of cache on-die totaling 3.3MB 55 Million 130 nm process • 221 Million transistors Bus Logic • 130W @1GHz, 1.5V • 421 mm2 die @intel • 142 mm2 CPU core L3 Cache ECE473 Lec 1.5 ECE473 19.5mm Lec 1.6 Source: http://www.specbench.org/cpu2000/results/ @intel 2006 - Intel Core Duo Processors for Desktop 2008 - Intel Core i7 64-bit x86-64 PERFORMANCE • Successor to the Intel Core 2 family 40% • Max CPU clock: 2.66 GHz to 3.33 GHz • Cores :4(: 4 (physical)8(), 8 (logical) • 45 nm CMOS process • Adding GPU into the processor POWER 40% …relative to Intel® Pentium® D 960 When compared to the Intel® Pentium® D processor 960.
    [Show full text]
  • 1. Definition of Computers Technically, a Computer Is a Programmable Machine
    1. Definition of computers Technically, a computer is a programmable machine. This means it can execute a programmed list of instructions and respond to new instructions that it is given. 2. What are the advantages and disadvantages of using computer? Advantages are : communication is improved, pay bill's online, people have access to things they would not have had before (for instance old people who cannot leave the house they can buy groceries online) Computers make life easier. The disadvantages are: scams, fraud, people not going out as much, we do not yet know the effects of computers and pregnancy or the emissions that computers make,. bad posture from sitting too long at a desk, repetitive strain injuries and the fact that most organizations expect everyone to own a computer. Year 1901 The first radio message is sent across the Atlantic Ocean in Morse code. 1902 3M is founded. 1906 The IEC is founded in London England. 1906 Grace Hopper is born December 9, 1906. 1911 Company now known as IBM on is incorporated June 15, 1911 in the state of New York as the Computing - Tabulating - Recording Company (C-T-R), a consolidation of the Computing Scale Company, and The International Time Recording Company. 1912 Alan Turing is born June 23, 1912. 1912 G. N. Lewis begins work on the lithium battery. 1915 The first telephone call is made across the continent. 1919 Olympus is established on October 12, 1919 by Takeshi Yamashita. 1920 First radio broadcasting begins in United States, Pittsburgh, PA. 1921 Czech playwright Karel Capek coins the term "robot" in the 1921 play RUR (Rossum's Universal Robots).
    [Show full text]
  • Class-Action Lawsuit
    Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys.
    [Show full text]
  • Intel Presentation Template Overview
    Intel 2016 Corporate Overview Updated September 2016 Intel is evolving. To a company that powers the data center and billions of smart, connected devices Intel’s Vision: If it’s smart and connected, it’s best with Intel. 2 Intel’s foundation: MOORE’S LAW History of Intel • 1968: Intel is founded by Robert Noyce and Gordon Moore • 1971: World’s first microprocessor • Now: Innovation that expands the reach and promise of computing 4 Executing to Moore’s Law Enabling new devices with higher functionality and complexity while controlling power, cost, and size Strained Silicon Hi-K Metal Gate 3D Transistors 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 5 Intel’s IDM Advantage Process Technology Intel Architecture Product Design Co-Optimized Process & Product Common Co-Optimized Architecture & Software Common Best Performance, Power, Security TOOLS Rapid Product Ramp GOALS Software Manufacturing Packaging 6 Intel is evolving Virtuous Cycle of Growth: our technology drives experiences 8 Intel delivers end to end solutions New Memory Client IOT Data Center Security Programmable Technologies Solutions Solutions 9 intel software: extensive Value Things Network Cloud/Data Center Wind River® Intel® Developer Zone Platform Security Simics Intel® Context Sensing Intel® CoFluent™ Technology Enabling Ecosystem Ecosystem Brillo OS …among others… Enabling 10 Intel is changing the world Corporate Responsibility at Intel Environmental Sustainability Supply Chain Responsibility Diversity & Inclusion Social Impact www.intel.com/responsibility www.intel.com/diversity 12 Barron’s. World’s Most Respected Companies Corporate Knights. Global 100 Most Sustainable Corporations Corporate Responsibility Magazine. 100 Best Corporate Citizens (17th year) Diversity MBA magazine.
    [Show full text]
  • Microprocessors in the 1970'S
    Part II 1970's -- The Altair/Apple Era. 3/1 3/2 Part II 1970’s -- The Altair/Apple era Figure 3.1: A graphical history of personal computers in the 1970’s, the MITS Altair and Apple Computer era. Microprocessors in the 1970’s 3/3 Figure 3.2: Andrew S. Grove, Robert N. Noyce and Gordon E. Moore. Figure 3.3: Marcian E. “Ted” Hoff. Photographs are courtesy of Intel Corporation. 3/4 Part II 1970’s -- The Altair/Apple era Figure 3.4: The Intel MCS-4 (Micro Computer System 4) basic system. Figure 3.5: A photomicrograph of the Intel 4004 microprocessor. Photographs are courtesy of Intel Corporation. Chapter 3 Microprocessors in the 1970's The creation of the transistor in 1947 and the development of the integrated circuit in 1958/59, is the technology that formed the basis for the microprocessor. Initially the technology only enabled a restricted number of components on a single chip. However this changed significantly in the following years. The technology evolved from Small Scale Integration (SSI) in the early 1960's to Medium Scale Integration (MSI) with a few hundred components in the mid 1960's. By the late 1960's LSI (Large Scale Integration) chips with thousands of components had occurred. This rapid increase in the number of components in an integrated circuit led to what became known as Moore’s Law. The concept of this law was described by Gordon Moore in an article entitled “Cramming More Components Onto Integrated Circuits” in the April 1965 issue of Electronics magazine [338].
    [Show full text]
  • Demystifying Internet of Things Security Successful Iot Device/Edge and Platform Security Deployment — Sunil Cheruvu Anil Kumar Ned Smith David M
    Demystifying Internet of Things Security Successful IoT Device/Edge and Platform Security Deployment — Sunil Cheruvu Anil Kumar Ned Smith David M. Wheeler Demystifying Internet of Things Security Successful IoT Device/Edge and Platform Security Deployment Sunil Cheruvu Anil Kumar Ned Smith David M. Wheeler Demystifying Internet of Things Security: Successful IoT Device/Edge and Platform Security Deployment Sunil Cheruvu Anil Kumar Chandler, AZ, USA Chandler, AZ, USA Ned Smith David M. Wheeler Beaverton, OR, USA Gilbert, AZ, USA ISBN-13 (pbk): 978-1-4842-2895-1 ISBN-13 (electronic): 978-1-4842-2896-8 https://doi.org/10.1007/978-1-4842-2896-8 Copyright © 2020 by The Editor(s) (if applicable) and The Author(s) This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Open Access This book is licensed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made. The images or other third party material in this book are included in the book’s Creative Commons license, unless indicated otherwise in a credit line to the material.
    [Show full text]
  • Moore's Law Motivation
    Motivation: Moore’s Law • Every two years: – Double the number of transistors CprE 488 – Embedded Systems Design – Build higher performance general-purpose processors Lecture 8 – Hardware Acceleration • Make the transistors available to the masses • Increase performance (1.8×↑) Joseph Zambreno • Lower the cost of computing (1.8×↓) Electrical and Computer Engineering Iowa State University • Sounds great, what’s the catch? www.ece.iastate.edu/~zambreno rcl.ece.iastate.edu Gordon Moore First, solve the problem. Then, write the code. – John Johnson Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.2 Motivation: Moore’s Law (cont.) Motivation: Dennard Scaling • The “catch” – powering the transistors without • As transistors get smaller their power density stays melting the chip! constant 10,000,000,000 2,200,000,000 Transistor: 2D Voltage-Controlled Switch 1,000,000,000 Chip Transistor Dimensions 100,000,000 Count Voltage 10,000,000 ×0.7 1,000,000 Doping Concentrations 100,000 Robert Dennard 10,000 2300 Area 0.5×↓ 1,000 130W 100 Capacitance 0.7×↓ 10 0.5W 1 Frequency 1.4×↑ 0 Power = Capacitance × Frequency × Voltage2 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 Power 0.5×↓ Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.3 Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.4 Motivation Dennard Scaling (cont.) Motivation: Dark Silicon • In mid 2000s, Dennard scaling “broke” • Dark silicon – the fraction of transistors that need to be powered off at all times (due to power + thermal
    [Show full text]
  • Energy Behaviour of NUCA Caches in Cmps
    Energy behaviour of NUCA caches in CMPs Alessandro Bardine, Pierfrancesco Foglia, Julio Sahuquillo Francesco Panicucci, Marco Solinas Departmento de Ingeniería de Sistemas y Computadores Dipartimento di Ingegneria dell’Informazione Universidad Politécnica de Valencia Università di Pisa Valencia, Spain Pisa, Italy [email protected] {a.bardine, foglia, f.panicucci, marco.solinas}@iet.unipi.it Abstract—Advances in technology of semiconductor make into many independent banks usually interconnected by a nowadays possible to design Chip Multiprocessor Systems equipped switched network. In this model the access latency is with huge on-chip Last Level Caches. Due to the wire delay proportional to the physical distance of the banks from the problem, the use of traditional cache memories with a uniform requesting element (typically one core or a single cache access time would result in unacceptable response latencies. NUCA controller). The mapping between cache lines and banks can be (Non Uniform Cache Access) architecture has been proposed as a performed either in a static or dynamic way (namely S-NUCA viable solution to hide the adverse impact of wires delay on and D-NUCA); in the former, each line can exclusively reside in performance. Many previous studies have focused on the a single predetermined bank, while in the latter a line can effectiveness of NUCA architectures, but the study of the energy dynamically migrate from one bank to another. When adopting and power aspects of NUCA caches is still limited. the dynamic approach, blocks are mapped to a set of banks, In this work, we present an energy model specifically suited for NUCA-based CMP systems, together with a methodology to employ called bankset, and they are able to migrate among the banks the model to evaluate the NUCA energy consumption.
    [Show full text]
  • Integrated Circuit Design
    ICD Integrated Circuit Design Assessment Informal Coursework LEdit Gate Layout Integrated Circuit Design Examination Books Digital Integrated Circuits Iain McNally Jan Rabaey PrenticeHall lectures Principles of CMOS VLSI Design ACircuits and Systems Perspective Koushik Maharatna Neil Weste David Harris AddisonWesley lectures Notes Resources httpusersecssotonacukbimnotesicd History Integrated Circuit Design Iain McNally First Transistor John Bardeen Walter Brattain and William Shockley Bell Labs Content Integrated Circuits Proposed Introduction Geoffrey Dummer Royal Radar Establishment prototype failed Overview of Technologies Layout First Integrated Circuit Design Rules and Abstraction Jack Kilby Texas Instruments Coinventor Cell Design and Euler Paths First Planar Integrated Circuit System Design using StandardCells Robert Noyce Fairchild Coinventor Pass Transistor Circuits First Commercial ICs Storage Simple logic functions from TI and Fairchild PLAs Moores Law Gordon Moore Fairchild observes the trends in integration Wider View History History Moores Law Moores Law a Selffullling Prophesy Predicts exponential growth in the number of components per chip The whole industry uses the Moores Law curve to plan new fabrication facilities Doubling Every Year In Gordon Moore observed that the number of components per chip had Slower wasted investment doubled every year since and predicted that the trend would continue through to Must keep up with the Joneses Moore describes his initial growth predictions
    [Show full text]
  • Gordon E. Moore and His Legacy: Four Decades and Counting
    In partnership with Brinkmann Gordon E. Moore and His Legacy: Four Decades and Counting 0720-A102F © 2004, 2006 Brinkmann Instruments, Inc. by Krishnan Rajeshwar and Fred Roozeboom orty years is a long time but linear oscillator based on an integrated amazingly enough, innovations circuit (IC) containing a germanium F in mainstream silicon transistor, a resistor, and a capacitor), microelectronics have largely continued and Robert Noyce (inventor in 1959 of a to follow Gordon Moore’s prescient planar Si IC based on Hoerni’s diffusion predictions. The contributions of this process). Indeed, these halcyon days of Si remarkable individual, an ECS member microelectronics saw a bewildering series for 48 years and currently an emeritus of very important discoveries emanating member, have been well documented mainly from R&D groups in three in these magazine pages including a companies: Shockley Semiconductor, cover story for the spring 1997 issue Fairchild Semiconductor, and Intel. (see image at right). In May 2006, Gordon Moore had a pivotal role to play ECS announced the establishment in all these companies! of the Gordon E. Moore Medal for What is Moore’s law? What does Outstanding Achievement in Solid- it exactly predict? We can only very State Science and Technology. This briefly address these questions here was made possible by an endowment by returning to Moore’s original from Intel Corporation in honor of paper.1 When this paper first came its co-founder. “This award honors out in 1965, Si chips contained about Moore’s tremendous achievements in 60 distinct devices. By contrast, this field, which have had a strong and Intel’s Itanium chip crams 17 billion lasting influence on ECS, its members, transistors in a single chip.
    [Show full text]
  • Gordon E. Moore, Ph.D., Co-Founder Gordon Moore and His Wife Betty
    Gordon E. Moore, Ph.D., Co-Founder Gordon Moore and his wife Betty established the Gordon and Betty Moore Foundation in September 2000, which fosters path-breaking scientific discovery, environmental conservation, improvements in patient care and preservation of the special character of the San Francisco Bay Area. Gordon co-founded Intel in 1968, serving initially as executive vice president. He became president and chief executive officer in 1975 and held that post until elected chairman and chief executive officer in 1979. He remained CEO until 1987 and was named chairman emeritus in 1997, stepping down in 2006. Gordon is widely known for “Moore's Law,” which in 1965 he predicted that the number of components the industry would be able to place on a computer chip would double every year. In 1975, he updated his prediction to once every two years. Because of changing technology, the industry now states approximately every 18 months. “Moore’s Law” has become the guiding principle for the industry to deliver ever-more powerful semiconductor chips at proportionate decreases in cost. In practical terms, what this means is smaller, cheaper chips with more functionality that allows everything from a laptop computer; cell phones; AEDs; GPS; cleaner car emissions/skid control/antilock brakes; digital cameras, to medical devices that non-invasively see inside the body, and literally hundreds of thousands of other uses. Gordon earned a B.S. in chemistry from the University of California at Berkeley and a Ph.D. in chemistry and physics from the California Institute of Technology. He was born in San Francisco, California, on January 3, 1929.
    [Show full text]