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Introduction to Digital Logic with Laboratory Exercises This Book Is Licensed Under a Creative Commons Attribution 3.0 License Introduction to Digital Logic with Laboratory Exercises This book is licensed under a Creative Commons Attribution 3.0 License Introduction to Digital Logic with Laboratory Exercises James Feher Copyright © 2009 James Feher Editor-In-Chief: James Feher Associate Editor: Marisa Drexel Proofreaders: Jackie Sharman, Rachel Pugliese For any questions about this text, please email: [email protected] The Global Text Project is funded by the Jacobs Foundation, Zurich, Switzerland This book is licensed under a Creative Commons Attribution 3.0 License Introduction to Digital Logic with Laboratory Exercises 2 A Global Text Table of Contents Preface...............................................................................................................................................................7 0. Introduction.............................................................................................................................9 1. The transistor and inverter....................................................................................................10 The transistor..................................................................................................................................................10 The breadboard................................................................................................................................................11 The inverter.....................................................................................................................................................12 2. Logic gates..............................................................................................................................14 History of logic chips.......................................................................................................................................14 Logic symbols..................................................................................................................................................15 Logical functions.............................................................................................................................................16 3. Logic simplification................................................................................................................19 De Morgan's laws............................................................................................................................................19 Karnaugh maps...............................................................................................................................................20 Circuit design, construction and debugging..................................................................................................24 4. More logic simplification.......................................................................................................27 Additional K-map groupings..........................................................................................................................27 Input placement on K-map............................................................................................................................29 Don't care conditions......................................................................................................................................29 5. Multiplexer.............................................................................................................................32 Background on the “mux”..............................................................................................................................32 Using a multiplexer to implement logical functions......................................................................................32 6. Timers and clocks..................................................................................................................37 Timing in digital circuits.................................................................................................................................37 555 timer.........................................................................................................................................................37 Timers.............................................................................................................................................................37 Clocks..............................................................................................................................................................38 Timing diagrams.............................................................................................................................................39 7. Memory .................................................................................................................................44 Memory...........................................................................................................................................................44 SR latch...........................................................................................................................................................44 Flip-flops.........................................................................................................................................................45 8. State machines.......................................................................................................................49 What is a state machine?................................................................................................................................49 State transition diagrams...............................................................................................................................50 State machine design......................................................................................................................................51 Debounced switches........................................................................................................................................55 9. More state machines..............................................................................................................57 How many bits of memory does a state machine need?................................................................................57 What are unused states?.................................................................................................................................57 10. What's next?.........................................................................................................................64 Appendix A: Chip pinouts.........................................................................................................65 Appendix B: Resistors and capacitors......................................................................................69 Resistors..........................................................................................................................................................69 Capacitors.......................................................................................................................................................70 3 This book is licensed under a Creative Commons Attribution 3.0 License Appendix C: Lab notebook.........................................................................................................71 Appendix D: Boolean algebra....................................................................................................73 Appendix E: Equipment list......................................................................................................74 Digital trainer..................................................................................................................................................74 7400 series families........................................................................................................................................75 Appendix F: Solutions ...............................................................................................................76 Chapter 1 review exercises..............................................................................................................................76 Chapter 2 review exercises.............................................................................................................................78 Chapter 3 review exercises..............................................................................................................................81 Chapter 4 review exercises.............................................................................................................................87 Chapter 5 review exercises.............................................................................................................................90 Chapter 6 review exercises.............................................................................................................................95 Chapter 7 review exercises.............................................................................................................................98 Chapter 8 review exercises............................................................................................................................101 Chapter 9 review exercises...........................................................................................................................104
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