RT8152E/F

Single-Phase PWM Controller for CPU / GPU Core General Description Features

The RT8152E/F is a single phase PWM controller with l Single Phase PWM Controller with Integrated integrated MOSFET drivers. Moreover, it is compliant with MOSFET Driver IMVP6.5 Specification to fulfill its l Low-Gain Compensator with CCRCOT Topology mobile CPU core and Render core voltage regulator (Constant Current Ripple Constant On Time) requirements. The RT8152E/F adopts G-NAVP (Green- l 7-bit DAC Native AVP), which is a Richtek's proprietary topology l 0.8% DAC Accuracy derived from finite DC gain compensator constant on-time l 1.5% or 11.5mV System Accuracy mode, making it an easy setting PWM controller meeting l Fixed VBOOT (For CPU Core Only) all Intel AVP (Active Voltage Positioning) mobile CPU/ l Differential Remote Voltage Sensing Render requirements. The output voltage of the RT8152E/ l G-NAVP Topology (Green-Native AVP) F is set by 7-bit VID code. The built-in high accuracy DAC l Programmable Output Transition Slew Rate Control converts the VID code ranging from 0V to 1.5V with l System Thermal Compensated AVP 12.5mV per step. The system accuracy of the controller l Ringing Free Mode at Light Load Condition can reach 1.5%. The part supports VID on-the-fly and mode l Fast Transient Response change on-the-fly functions that are fully compliant with l IMVP6.5 Compatible States IMVP6.5 specification. It operates in single phase and l Power Good diode emulation modes. It can reach up to 90% efficiency l Clock Enable Output (For CPU Core Only) in different modes according to different loading conditions. l Thermal Throttling The droop load line can be easily programmed by setting l Current Monitor Output the DC gain of the error amplifier. With proper l Switching Frequency Up to 1MHz compensation, the load transient can achieve optimized l OVP, UVP, OCP, OTP, UVLO, NVP AVP performance. This chip controls soft-start and output l 32-Lead WQFN Package transition slew rate via a capacitor. It supports both DCR l RoHS Compliant and Halogen Free and sense resistor current sensing. The RT8152E/F provides power good and thermal throttling output signals Ordering Information RT8152 for IMVP6.5 Render core specification, and additional clock enabling for CPU core specification. It also features Package Type QW : WQFN-32L 5x5 (W-Type) complete fault protection functions including over voltage, Lead Plating System under voltage, negative voltage, over current and thermal G : Green (Halogen Free and Pb Free) shutdown. The RT8152E/F is available in WQFN-32L 5x5 VRON Power small foot print package. E : 1.05V F : 3.3V

Applications Note : l IMVP6.5 CPU / Render Core Voltage Regulator Richtek products are : l AVP Step-Down Converter } RoHS compliant and compatible with the current require- l Notebook / / Servers ments of IPC/JEDEC J-STD-020. } Suitable for use in SnPb or Pb-free soldering processes.

DS8152E/F-04 April 2011 www.richtek.com 1 RT8152E/F

Marking Information Pin Configurations RT8152EGQW (TOP VIEW) T 0 1 2 3 4 5 6

RT8152EGQW : Product Number T D D D D D D D I I I R I I I I V V V V V V V RT8152E YMDNN : Date Code V GQW 32 31302928 27 26 25 YMDNN NTC 1 24 BOOT OCSET 2 23 UGATE DPRSLPVR 3 22 PHASE VRON 4 21 PGND GND RT8152FGQW PGOOD 5 20 LGATE RT8152FGQW : Product Number CLKEN 6 19 PVDD VCC 7 18 GND RT8152F YMDNN : Date Code 33 SOFT 8 17 TON GQW YMDNN 9 1011 1213 14 15 16 T D N B P N N M E F _ E E N C M S S N S G O I V E M R C S C I WQFN-32L 5x5

Typical Application Circuit

VIN 5V to 25V RT8152E/F R1 7 17 R2 R3 5V VCC TON C5 C1 C3

19 PVDD R4 BOOT 24 C4 Q1 C2 31 23 VID0 VID0 UGATE R5 L1 30 22 VID1 VID1 PHASE VOUT Q2 VID2 29 VID2 20 R8 R6 C7 LGATE D1 R7 COUT 28 VID3 VID3 21 PGND C6 27 VID4 VID4 16 ISEN 26 VID5 VID5 ISEN_N 15 25 VID6 VID6 11 R13 C9 3 CMSET DPRSLPVR DPRSLPVR 4 12 VRON VRON VSEN FB 13 5 C12 C13 PWRGD PGOOD CPU VCC_SNS CLKEN 6 CLKEN 32 14 R18 R19 R20 R21 VRTT VRTT COMP VOUT R9 R10 R11 NTC1 9 VCCP RGND CPU VSS_SNS 3.3V C10 1 SOFT 8 R22 NTC 10 R14 R15 R16 2 CM CM VCC OCSET R12 C11 R17 NTC2 18, 33 (Exposed Pad) GND CPU VSS_SNS

Figure 1. CPU Core Voltage Regulator www.richtek.com DS8152E/F-04 April 2011 2 RT8152E/F

VIN 5V to 25V RT8152E/F R1 7 17 R2 R3 5V VCC TON C5 C1 C3

19 PVDD R4 BOOT 24 C4 Q1 C2 31 23 VID0 VID0 UGATE R5 L1 30 22 VID1 VID1 PHASE VOUT Q2 VID2 29 VID2 20 R8 R6 C7 LGATE D1 R7 COUT 28 VID3 VID3 21 PGND C6 27 VID VID4 16 4 ISEN 26 VID5 VID5 ISEN_N 15 25 VID6 VID6 11 R13 C9 3 CMSET DPRSLPVR DPRSLPVR 4 12 VRON VRON VSEN 6 CLKEN FB 13 C12 C13 5 PWRGD PGOOD GPU VCC_SNS 32 VRTT VRTT 14 R18 R19 R20 R21 COMP VOUT R9 R11 NTC1 9 VCCP RGND GPU VSS_SNS 3.3V C10 1 SOFT 8 R22 NTC 10 R14 R15 R16 2 CM CM VCC OCSET R12 C11 R17 NTC2 18, 33 (Exposed Pad) GND GPU VSS_SNS

Figure 2. Render Core Voltage Regulator

Functional Pin Description Pin No. Pin Name Pin Function Thermal Detection Input for VRTT Circuit. Connect this pin with a resistor divider 1 NTC from VCC using NTC on the top to set the thermal management threshold level. Over Current Protection Setting. Connect a resistor voltage divider from VCC to 2 OCSET ground, the joint of the resistor divider is connected to OCSET pin, with a voltage VOCSET, to set the over current threshold ILIM. 3 DPRSLPVR Deeper Sleep Mode Signal. 4 VRON Voltage Regulator Enabler. 5 PGOOD Power Good Indicator. Inverted Clock Enable. Pull high by a resistor for CPU core application. This 6 CLKEN open-drain pin is an output indicating the start of the PLL locking of the clock chip. Connect to GND for Render application. 7 VCC Chip Power. Soft-Start. This pin provides soft-start function and slew rate controller. The capacitance of the slew rate control C is restricted to be larger than 10nF. The 8 SOFT feedback voltage of the converter follows the ramping voltage on the SOFT pin during soft-start and other voltage transitions according to different mode of operation and VID change. To be continued DS8152E/F-04 April 2011 www.richtek.com 3 RT8152E/F

Pin No. Pin Name Pin Function Return Ground. This pin is the negative node of the differential remote 9 RGND voltage sensing. Current Monitor Output. This pin outputs a voltage proportional to the 10 CM output current. Current Monitor Output Gain Externally Setting. Connect this pin with one resistor to VSEN while CM pin is connected to ground with one another 11 CMSET resistor. In such way, current monitor output gain can be set by the ratio of these two resistors. Positive Voltage Sensing Pin. This pin is the positive node of the 12 VSEN differential voltage sensing. 13 FB Feedback. This is the negative input node of the error amplifier. 14 COMP Compensation. This pin is the output node of the error amplifier. 15 ISEN_N Negative input of the current sense. 16 ISEN Positive input of the current sense. 17 TON Connect this pin to VIN with one resistor. 18, Ground. The exposed pad must be soldered to a large PCB and GND 33 (Exposed Pad) connected to GND for maximum power dissipation. 19 PVDD Driver Power. 20 LGATE Lower Gate Drive. This pin drives the gate of the low side . 21 PGND Driver Ground. This pin is return node of the high side MOSFET driver. Connect this pin 22 PHASE to the high side MOSFET sources together with the low side MOSFET drains and the inductor. 23 UGATE Upper Gate Drive. This pin drives the gate of the high side MOSFETs. Bootstrap Power Input. This pin powers the high side MOSFET drivers. 24 BOOT Connect this pin to bootstrap capacitor. Voltage ID. DAC voltage identification inputs for IMVP6.5. VID6 to 25 to 31 The logic threshold is 30% of the VCCP as the maximum value for low VID0 state and 70% of the VCCP as the minimum value for the high state. Voltage Regulator Thermal Throttling. This open-drain output pin will be 32 VRTT pulled low when the preset temperature level is exceeded.

www.richtek.com DS8152E/F-04 April 2011 4 RT8152E/F

Table 1. IMVP6.5 VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output 0 0 0 0 0 0 0 1.5000V 0 1 0 0 0 0 1 1.0875V 0 0 0 0 0 0 1 1.4875V 0 1 0 0 0 1 0 1.0750V 0 0 0 0 0 1 0 1.4750V 0 1 0 0 0 1 1 1.0625V 0 0 0 0 0 1 1 1.4625V 0 1 0 0 1 0 0 1.0500V 0 0 0 0 1 0 0 1.4500V 0 1 0 0 1 0 1 1.0375V 0 0 0 0 1 0 1 1.4375V 0 1 0 0 1 1 0 1.0250V 0 0 0 0 1 1 0 1.4250V 0 1 0 0 1 1 1 1.0125V 0 0 0 0 1 1 1 1.4125V 0 1 0 1 0 0 0 1.0000V 0 0 0 1 0 0 0 1.4000V 0 1 0 1 0 0 1 0.9875V 0 0 0 1 0 0 1 1.3875V 0 1 0 1 0 1 0 0.9750V 0 0 0 1 0 1 0 1.3750V 0 1 0 1 0 1 1 0.9625V 0 0 0 1 0 1 1 1.3625V 0 1 0 1 1 0 0 0.9500V 0 0 0 1 1 0 0 1.3500V 0 1 0 1 1 0 1 0.9375V 0 0 0 1 1 0 1 1.3375V 0 1 0 1 1 1 0 0.9250V 0 0 0 1 1 1 0 1.3250V 0 1 0 1 1 1 1 0.9125V 0 0 0 1 1 1 1 1.3125V 0 1 1 0 0 0 0 0.9000V 0 0 1 0 0 0 0 1.3000V 0 1 1 0 0 0 1 0.8875V 0 0 1 0 0 0 1 1.2875V 0 1 1 0 0 1 0 0.8750V 0 0 1 0 0 1 0 1.2750V 0 1 1 0 0 1 1 0.8625V 0 0 1 0 0 1 1 1.2625V 0 1 1 0 1 0 0 0.8500V 0 0 1 0 1 0 0 1.2500V 0 1 1 0 1 0 1 0.8375V 0 0 1 0 1 0 1 1.2375V 0 1 1 0 1 1 0 0.8250V 0 0 1 0 1 1 0 1.2250V 0 1 1 0 1 1 1 0.8125V 0 0 1 0 1 1 1 1.2125V 0 1 1 1 0 0 0 0.8000V 0 0 1 1 0 0 0 1.2000V 0 1 1 1 0 0 1 0.7875V 0 0 1 1 0 0 1 1.1875V 0 1 1 1 0 1 0 0.7750V 0 0 1 1 0 1 0 1.1750V 0 1 1 1 0 1 1 0.7625V 0 0 1 1 0 1 1 1.1625V 0 1 1 1 1 0 0 0.7500V 0 0 1 1 1 0 0 1.1500V 0 1 1 1 1 0 1 0.7375V 0 0 1 1 1 0 1 1.1375V 0 1 1 1 1 1 0 0.7250V 0 0 1 1 1 1 0 1.1250V 0 1 1 1 1 1 1 0.7125V 0 0 1 1 1 1 1 1.1125V 1 0 0 0 0 0 0 0.7000V 0 1 0 0 0 0 0 1.1000V 1 0 0 0 0 0 1 0.6875V

To be continued DS8152E/F-04 April 2011 www.richtek.com 5 RT8152E/F

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output 1 0 0 0 0 1 0 0.6750V 1 1 0 0 0 0 1 0.2875V 1 0 0 0 0 1 1 0.6625V 1 1 0 0 0 1 0 0.2750V 1 0 0 0 1 0 0 0.6500V 1 1 0 0 0 1 1 0.2625V 1 0 0 0 1 0 1 0.6375V 1 1 0 0 1 0 0 0.2500V 1 0 0 0 1 1 0 0.6250V 1 1 0 0 1 0 1 0.2375V 1 0 0 0 1 1 1 0.6125V 1 1 0 0 1 1 0 0.2250V 1 0 0 1 0 0 0 0.6000V 1 1 0 0 1 1 1 0.2125V 1 0 0 1 0 0 1 0.5875V 1 1 0 1 0 0 0 0.2000V 1 0 0 1 0 1 0 0.5750V 1 1 0 1 0 0 1 0.1875V 1 0 0 1 0 1 1 0.5625V 1 1 0 1 0 1 0 0.1750V 1 0 0 1 1 0 0 0.5500V 1 1 0 1 0 1 1 0.1625V 1 0 0 1 1 0 1 0.5375V 1 1 0 1 1 0 0 0.1500V 1 0 0 1 1 1 0 0.5250V 1 1 0 1 1 0 1 0.1375V 1 0 0 1 1 1 1 0.5125V 1 1 0 1 1 1 0 0.1250V 1 0 1 0 0 0 0 0.5000V 1 1 0 1 1 1 1 0.1125V 1 0 1 0 0 0 1 0.4875V 1 1 1 0 0 0 0 0.1000V 1 0 1 0 0 1 0 0.4750V 1 1 1 0 0 0 1 0.0875V 1 0 1 0 0 1 1 0.4625V 1 1 1 0 0 1 0 0.0750V 1 0 1 0 1 0 0 0.4500V 1 1 1 0 0 1 1 0.0625V 1 0 1 0 1 0 1 0.4375V 1 1 1 0 1 0 0 0.0500V 1 0 1 0 1 1 0 0.4250V 1 1 1 0 1 0 1 0.0375V 1 0 1 0 1 1 1 0.4125V 1 1 1 0 1 1 0 0.0250V 1 0 1 1 0 0 0 0.4000V 1 1 1 0 1 1 1 0.0125V 1 0 1 1 0 0 1 0.3875V 1 1 1 1 0 0 0 0.0000V 1 0 1 1 0 1 0 0.3750V 1 1 1 1 0 0 1 0.0000V 1 0 1 1 0 1 1 0.3625V 1 1 1 1 0 1 0 0.0000V 1 0 1 1 1 0 0 0.3500V 1 1 1 1 0 1 1 0.0000V 1 0 1 1 1 0 1 0.3375V 1 1 1 1 1 0 0 0.0000V 1 0 1 1 1 1 0 0.3250V 1 1 1 1 1 0 1 0.0000V 1 0 1 1 1 1 1 0.3125V 1 1 1 1 1 1 0 0.0000V 1 1 0 0 0 0 0 0.3000V 1 1 1 1 1 1 1 0.0000V

www.richtek.com DS8152E/F-04 April 2011 6 RT8152E/F

Function Block Diagram CMSET ISEN_N BOOT UGATE PHASE PVDD LGATE PGND ISEN CM - + 10 Logic Driver Control TON On-Time FB CCRCOT Generator CM PWMCP - + OCP Setting Mode Selection - + DPRSLPVR OTP & Central Logic Power On Reset Offset Cancellation VRON OCSET - + - - + + PGOOD VCC Mode AMP Selection ERROR

N

E

K - + Point Point Point

L NVP Trip UVP Trip OVP Trip

C

T

T

R

V Soft Start MUX - + VDAC NTC BOOT DAC V VCC FB GND VID0 VID1 VID2 VID3 VID4 VID5 VID6 SOFT VSEN RGND COMP

DS8152E/F-04 April 2011 www.richtek.com 7 RT8152E/F

Absolute Maximum Ratings (Note 1) l VCC to GND------0.3V to 6.5V l RGND, PGND to GND------0.3V to 0.3V l VIDx to GND------0.3V to (VCC + 0.3V) l DPRSLPVR, VRON to GND------0.3V to (VCC + 0.3V) l PGOOD, CLKEN, VRTT to GND------0.3V to (VCC + 0.3V) l VSEN, FB, COMP, SOFT, OCSET, CM, CMSET, NTC to GND------0.3V to (VCC + 0.3V) l ISEN, ISEN_N to GND------0.3V to (VCC + 0.3V) l PVDD to PGND------0.3V to 6.5V l LGATE to PGND DC------0.3V to (PVDD + 0.3V) <20ns------2.5V to 7.5V l PHASE to PGND DC------0.3V to 28V <20ns------8V to 38V l BOOT to PHASE------0.3V to 6.5V l UGATE to PHASE DC------0.3V to (BOOT - PHASE) <20ns------5V to 7.5V l TON to GND------0.3V to 28V l Power Dissipation, PD @ T A = 25°C WQFN-32L 5x5------2.778W l Package Thermal Resistance (Note 2)

WQFN-32L 5x5, qJA ------36°C/W

WQFN-32L 5x5, qJC ------7°C/W l Junction Temperature------150°C l Storage Temperature Range------65°C to 150°C l Lead Temperature (Soldering, 10 sec.)------260°C l ESD Susceptibility (Note 3) HBM (Human Body Mode)------2kV MM (Machine Mode)------200V

Recommended Operating Conditions (Note 4) l Supply Voltage, VCC ------4.5V to 5.5V l Battery Voltage, VIN ------5V to 25V l Junction Temperature Range------40°C to 125°C l Ambient Temperature Range------40°C to 85°C

www.richtek.com DS8152E/F-04 April 2011 8 RT8152E/F

Electrical Characteristics

(VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Input R = 130kW, V = 3.3V, Supply Current I + I TON RON -- -- 10 mA VCC PVDD No Loading Current

Shutdown Current IVCC + IPVDD VRON = 0V -- -- 5 mA

Soft-Start/Slew Rate Control (based on 10nF CSS)

Soft-Start / Soft-Shutdown ISS1 SOFT = 1.5V -- 20 -- mA Normal VID Change Slew I SOFT = 1.5V 40 50 60 mA Current SS2 Deeper Sleep Exit/VID I For Render Mode Only, SOFT = 1.5V 80 100 120 mA Change Slew Current SS3 Reference and DAC V = 0.7500 - 1.5000 DAC -0.8 0 0.8 %VID DC Accuracy VFB (No Load, Active Mode) VDAC = 0.5000 - 0.7500 -7.5 0 7.5 mV RT8152E 1.089 1.1 1.111 Boot Voltage VBOOT V RT8152F 1.188 1.2 1.212 Error Amplifier

DC Gain RL = 47kW (Note 5) 70 80 -- dB

Gain-Bandwidth Product GBW CLOAD = 5pF (Note 5) -- 10 -- MHz

CLOAD = 10pF (Gain = -4, Slew Rate SRCOMP -- 5 -- V/ms Rf = 47kW, VOUT = 0.5V - 3V)

Output Voltage Range VCOMP RL = 47kW 0.5 -- 3.6 V

Maximum Source Current VCOMP = 2V 200 250 -- mA IOUTEA_COMP Maximum Sink Current VCOMP = 2V -- 20 -- mA Current Sense Amplifier

Input Offset Voltage VOSCS ISEN = ISEN_N = 1.5V -1 -- 1 mV

Impedance at Neg. Input RISEN_N ISEN_N = 1.5V 1 -- -- MW

Impedance at Pos. Input RISEN ISEN = 1.5V 1 -- -- MW DC Gain -- 10 -- V/V

VDAC = 1.1V, Input Range VISEN_IN -50 -- 80 mV VISEN_IN = ISEN - ISEN_N TON Setting

TON Pin Output Voltage VTON RTON = 80kW, VTON = VDAC = VBOOT -5 0 5 %

ON-Time Setting TON IRTON = 80mA, VTON = VDAC = VBOOT -- 350 -- ns

RTON Current Range IRTON VTON = VDAC = VBOOT 25 -- 280 mA

Minimum Off Time TOFF IRTON = 80mA, VDAC = VBOOT 250 -- 500 ns Protection Under Voltage Lock-out V Falling edge, 80mV Hysteresis 3.9 4.1 4.3 V Threshold UVLO To be continued DS8152E/F-04 April 2011 www.richtek.com 9 RT8152E/F

Parameter Symbol Test Conditions Min Typ Max Unit Protection Absolute Over Voltage V (Respect to 1.5V, ±50mV) 1.45 1.5 1.55 V Protection Threshold OVABS Relative Over Voltage V (Respect to V , ±50mV) 250 300 350 mV Protection Threshold OV DAC Measured at VSEN respect to Under Voltage Protection V unloaded output voltage (UOV) -450 -400 -350 mV Threshold UV (for 0.8 < UOV < 1.5) Negative Voltage Protection Measured at VSEN respect to V -100 -- -- mV Threshold NV GND

Current Limit Threshold VISEN - VISEN_N = VILIM, VILIM 46.5 50 53.5 mV Voltage VOCSET = 2V, 40 x VILIM = VOCSET

Thermal Shutdown Threshold TSD Typical hysteresis is 10°C -- 160 -- °C Logic Inputs RT8152E Respect to 1.05V, 70% 0.735 -- -- VIH RT8152F Respect to 3.3V, 70% 2.31 -- -- VRON Threshold V RT8152E Respect to 1.05V, 30% -- -- 0.315 VIL RT8152F Respect to 3.3V, 30% -- -- 0.99 Leakage Current of VRON -1 -- 1 mA

DAC (VID0 - VID6) and VIH Respect to 1.05V, 70% 0.77 -- -- V DPRSLPVR VIL Respect to 1.05V, 30% -- -- 0.33 Leakage Current of DAC (VID0 - VID6) and -1 -- 1 mA DPRSLPVR Power Good

CPU Core : VSEN - VBOOT -- -100 -- PGOOD Threshold VTH_PGOOD mV Render : VSEN - VDAC -- -100 --

PGOOD Low Voltage VPGOOD IPGOOD = 4mA -- -- 0.4 V CPU Core, CLKEN Low to 3 -- 20 PGOOD High PGOOD Delay TPGOOD ms Render Mode VRON High to 3 -- 20 PGOOD High Clock Enable For CPU Core Only, CLKEN Low Voltage VCLKEN -- -- 0.4 V ICLKEN = 4mA Thermal Throttling

Thermal Throttling Threshold VOT Measure at NTC respect to VCC -- 80 -- %VDD Thermal Throttling Threshold V At V = 5V -- 230 -- mV Hysteresis OT_HY CC

VRTT Output Voltage VVRTT IVRTT = 40mA -- -- 0.4 V Current Monitor Current Monitor Output V = 0.9V, V = 0.82V, DAC RCMSET 770 800 830 mV Voltage in Operating Range RCM = 7.5kW, RCMSET = 1.5kW

To be continued www.richtek.com DS8152E/F-04 April 2011 10 RT8152E/F

Parameter Symbol Test Conditions Min Typ Max Unit Current Monitor Maximum -- -- 1.15 V Output Voltage Gate Driver

VBOOT - VPHASE = 5V Upper Driver Source RUGATEsr -- 0.7 -- W VBOOT - VUGATE = 1V

Upper Driver Sink RUGATEsk VUGATE = 1V -- 0.6 -- W

Lower Driver Source RLGATEsr VPVDD = 5V, VPVDD - VLGATE = 1V -- 0.75 -- W

Lower Driver Sink RLGATEsk VLGATE = 1V -- 0.5 -- W

Upper Driver Source/Sink VBOOT - VPHASE = 5V IUGATE -- 3 -- A Current VUGATE = 2.5V Lower Driver Source I V = 2.5V -- 3 -- A Current LGATEsr LGATE

Lower Driver Sink Current ILGATEsk VLGATE = 2.5V -- 5 -- A Internal Boot Charging R PVDD to BOOT -- 30 -- W Switch On-Resistance BOOT

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. qJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of

JEDEC 51-7 thermal measurement standard. The case point of qJC is on the expose pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design.

DS8152E/F-04 April 2011 www.richtek.com 11 RT8152E/F

Typical Operating Characteristics

VIN = 12.6V, RTON = 150W, L = 0.36mH, COUT = 330mF, No Load, TA = 25°C, unless otherwise specified. CCM Efficiency vs. Load Current CCM VCC_SENSE vs. Load Current 100 1.16 90 1.14 80 VIN = 8V VIN = 12V 70 VIN = 19V 1.12 60 V = 8V 50 1.10 IN VIN = 12V 40 VIN = 19V 1.08 E ff i c e n y ( %) 30 V C _ SE N S E ( V) 20 1.06 10 VID = 1.15V, DPRSLPVR = Low VID = 1.15V, DPRSLPVR = Low 0 1.04 0 3 6 9 12 15 18 21 24 27 30 0 3 6 9 12 15 18 21 24 27 30 Load Current (A) Load Current (A)

CCM Efficiency vs. Load Current CCM VCC_SENSE vs. Load Current 100 0.95 VID = 0.9375V, DPRSLPVR = Low 90 0.94

80 VIN = 8V 0.93 VIN = 12V 0.92 70 VIN = 19V 0.91 60 0.90 50 0.89 VIN = 8V 40 VIN = 12V 0.88 VIN = 19V E f i c e n y ( %) 30

V C _ S E N ( V) 0.87 20 0.86 10 0.85 VID = 0.9375V, DPRSLPVR = Low 0 0.84 0 3 6 9 12 15 18 21 24 27 30 0 3 6 9 12 15 18 21 24 27 30 Load Current (A) Load Current (A)

RFM Efficiency vs. Load Current VCM vs. Load Current 100 1.1 95 1.0 90 0.9 0.8 85 0.7 80 VIN = 8V VIN = 8V VIN = 12V 0.6 75 (V) VIN = 12V VIN = 19V CM 0.5 VIN = 19V 70 V 0.4 E ff i c en y ( %) 65 0.3 60 0.2 55 0.1 VID = 0.85V, DPRSLPVR = High VID = 0.9375V, DPRSLPVR = Low 50 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 0 5 10 15 20 25 30 Load Current (A) Load Current (A)

www.richtek.com DS8152E/F-04 April 2011 12 RT8152E/F

CPU Mode Power On Render Mode Power On

VCC_SENSE (1V/Div) VCC_SENSE PGOOD (1V/Div) (5V/Div) PGOOD VRON (5V/Div) (5V/Div) VRON (5V/Div) CLKEN (5V/Div) CLKEN VID = 0.9375V, CLKEN Pull High to 3.3V (5V/Div) VID = 0.9375V, CLKEN Pull low to GND

Time (1ms/Div) Time (1ms/Div)

CPU Mode Power Down CCM VID Change Down

VCC_SENSE CLKEN Pull High to 3.3V (100mV/Div) VCC_SENSE (1V/Div) PGOOD UGATE (5V/Div) (20V/Div)

VRON LGATE (5V/Div) (5V/Div)

CLKEN VID0 (5V/Div) (5V/Div) VID = 0.9375V, CLKEN Pull High to 3.3V VID change from 0.9375V to 0.85V

Time (100μs/Div) Time (20μs/Div)

CCM VID Change Up CPU-RFM VID Change Down

VCC_SENSE VCC_SENSE CLKEN Pull High to 3.3V (100mV/Div) (100mV/Div)

UGATE UGATE (20V/Div) (20V/Div)

LGATE LGATE (5V/Div) (5V/Div)

VID0 VID0 (5V/Div) CLKEN Pull High to 3.3V (5V/Div) VID change from 0.85V to 0.9375V VID change from 0.9375V to 0.85V

Time (20μs/Div) Time (20μs/Div)

DS8152E/F-04 April 2011 www.richtek.com 13 RT8152E/F

CCM Load Transient Response CCM Load Transient Response

VID = 0.9375V, ILOAD = 5A to 28A VID = 0.9375V, ILOAD = 28A to 5A CLKEN Pull High to 3.3V (CPU) DPSLPVR = High VCC_SENSE DPSLPVR = Low VCC_SENSE (50mV/Div) (50mV/Div)

UGATE UGATE (20V/Div) (20V/Div)

LGATE LGATE (5V/Div) (5V/Div) CLKEN Pull High to 3.3V (CPU)

Time (10μs/Div) Time (10μs/Div)

C4 ENTRY / EXIT with VID Change Over Current Protection

VID = 0.9375V and 0.85V, CLKEN Pull High to 3.3V CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low DPSLPVR = High VCC_SENSE VCC_SENSE (100mV/Div) (1V/Div)

ILOAD (40A/Div) ILOAD (20A/Div) VID0 (5V/Div) PHASE (10V/Div)

DPRSLPVR PWRGD (5V/Div) (2V/Div) ILOAD-DPRSLPVR = 1A, ILOAD-CCM = 21A

Time (40μs/Div) Time (10μs/Div)

Over Voltage Protection Under Voltage Protection

VCC_SENSE VCC_SENSE (1V/Div) (1V/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE LGATE (10V/Div) (10V/Div)

PWRGD PWRGD (2V/Div) (2V/Div) CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low

Time (10μs/Div) Time (10μs/Div)

www.richtek.com DS8152E/F-04 April 2011 14 RT8152E/F

Application Information The RT8152E/F is a single-phase PWM controller with Differential Remote Sense Connection embedded gate driver. It is compliant with Intel IMVP6.5 The RT8152E/F includes differential, remote sense inputs Voltage Regulator Specification to fulfill its mobile CPU to eliminate the effects of voltage drops along the PC and Render voltage regulator power supply requirement. board traces, CPU internal power routes and socket

Inductor current are continuously sensed for loop control, contacts. CPU contains on-die sense pins VCC_SENSE and droop tuning, and over current protection. The 7-bit VID VSS_SENSE. Connect RGND to VSS_SENSE. Connect FB to

DAC and a low offset differential amplifier allow the controller VCC_SENSE with a resistor to build the negative input path to maintain high regulating accuracy to meet Intel of the error amplifier. Connect VSEN to VCC_SENSE for IMVP6.5 specification. CLKEN, PGOOD, OVP, and UVP detection. The 7 bit VID DAC and the precision voltage reference are referred to Design Tool RGND for accurate remote sensing. To help users to reduce the efforts and errors caused by manual calculations using the design concept below, a Current Sense Setting user friendly design tool is now available on request. The RT8152E/F is continuously sensing the inductor This design tool calculates all necessary design current. Therefore, the controller can be less noise parameters by entering user's requirements. Please sensitive. Low offset amplifiers are used for loop control contact Richtek's representatives for details. and over current detection. The internal current sense amplifier gain (AI) is fixed to be 10. The ISEN and ISEN_N Operation Modes denote the positive and negative input of the current sense Table 2 shows the RT8152E/F operation modes. When amplifier. VRON is enable (=1), and within 10ms the RT8152E/F will Users can either use a current sense resistor or the detect the CLKEN to determine which operation mode is inductor's DCR for current sensing. Using inductor's DCR applied. If the CLKEN is low, the RT8152E/F will operate allows higher efficiency as shown in Figure 3. To let : in Render core voltage regulator mode. If the CLKEN is L =´RCX (1) high, the IC will operate in CPU core voltage regulator DCR X mode. then the transient performance will be optimum. For DPRSLPVR determines the operation mode of the example, chose L = 0.36mH with 1mW DCR and CX = 100nF, controller operation in CCM or RFM. The controller enters yields for RX : RFM (Ring Free Mode) when DPRSLPVR = 1 and enters 0.36Hm R==W3.6k (2) CCM when DPRSLPVR = 0. X 1mW´100nF

Table 2. Control signal truth table for operation VOUT

modes of the RT8152E/F L DCR PHASE

CLKEN DPRSLPVR Operation Mode RX CX 0 0 Render CCM ISEN + VX - (GND) 1 Render RFM ISEN_N 1 0 CPU CCM (Pull High) 1 CPU RFM Figure 3. Lossless Inductor Current Sensing

DS8152E/F-04 April 2011 www.richtek.com 15 RT8152E/F

Considering the inductance tolerance, the resistor RX has The HS_FET on-time is determined by CCRCOT ON-Time to be tuned on board by examining the transient voltage. generator. When load current increases, VCS increases, If the output voltage transient has an initial dip below the the steady state COMP voltage also increases and makes minimum load line requirement with a slow recovery, RX the VOUT decrease, achieving AVP. A near-DC offset is chosen too small. Vice versa, with a resistance too cancellation is added to the output of EA to cancel the large, the output voltage transient has only a small initial inherent output offset of finite-gain current mode controller. dip and the recovery is too fast causing a ring back. In RFM, HS_FET is turned on with constant TON when

Using current sense resistor in series with the inductor VCS is lower than V COMP2. Once the HS_FET is turned off, can have better accuracy, but the efficiency is a trade off. LS_FET is turned on automatically. By Ringing-Free

Considering the equivalent inductance (LESL) of the current Technique, the LS_FET allows only partial of negative sense resistor, a RC filter is recommended. The RC filter current when the inductor free-wheeling current reaches calculation method is similar to the above mentioned negative. The switching frequency will be proportionately inductor DCR sensing method. reduced, thus the conduction and switching losses will be greatly reduced. Loop Control The RT8152E/F adopts Richtek's proprietary G-NAVPTM Output Voltage Droop Setting (with Temperature topology. G-NAVPTM is based on the finite-gain current Compensation) mode with CCRCOT (Constant Current Ripple Constant It's very easy to achieve the Active Voltage Positioning

On Time) topology. The output voltage, VOUT, will decrease (AVP) by properly setting the error amplifier gain due to with increasing output load current. The control loop the native droop characteristics. The target is to have : consists of PWM modulator with power stage, current VOUT = VDAC - ILOAD x RDROOP (3) sense amplifier and error amplifier as shown in Figure 4. , then solving the switching condition VCOMP2 = VCS in

VIN Figure 4 yields the desired error amplifier gain as : RT8152E/F R2 ARI´SENSE UGATE HS_FET VOUT A == CCRCOT V (4) L R1RDROOP PWM Logic LGATE RX CX C where AI is the internal current sense amplifier gain. RSENSE LS_FET CMP is the current sense resistor. If no external sense resistor + - ISEN COMP2 VCS + present, it is the DCR of the inductor. RDROOP is the Ai ISEN_N - C2 C1 resistive slope value of the converter output and is the desired static output impedance. COMP R2 R1 VCC_SENSE FB V Offset - OUT + EA - SOFT A > A Cancellation + V2 V1 C RGND SOFT VDAC VSS_SENSE

Figure 4. Simplified Schematic for Droop and Remote AV2 Sense in CCM AV1

0 Load Current

Figure 5. Error Amplifier Gain (AV) Influence on V OUT

www.richtek.com DS8152E/F-04 April 2011 16 RT8152E/F

Since the DCR of inductor is highly temperature dependent, R2 = AV, 25 x (R1b + R1a // RNTC, 25) (9) it affects the output accuracy at hot conditions. Where A V, 25 is the error amplifier gain at room temperature Temperature compensation is recommended for the and can be obtained from (4). R1b can be obtained by lossless inductor DCR current sense method. Figure 6 substituting (9) to (5), shows a simple but effective way of compensating the R1b = temperature variations of the sense resistor using an NTC R SENSE, HOT thermistor placed in the feedback path. ´-(R1a//RNTC, HOT)(R1a//R)NTC, COLD RSENSE, COLD RT8152E/F C2 C1 æöRSENSE, HOT ç÷1- (10) èøRSENSE, COLD COMP R2 R1b R1a VCC_SENSE FB Loop Compensation - NTC

EA + - SOFT + Optimized compensation of the RT8152E/F allows for best CSOFT VDAC 10nF possible load step response of the regulator's output. A RGND VSS_SENSE compensator with one pole and one zero is adequate for Figure 6. Loop Setting with Temperature Compensation a proper compensation. Figure 4 shows the compensation circuit. Prior design procedure shows how to decide the Usually, R1a is set to equal R (25°C). R1b is selected NTC resistive feedback components of error amplifier gain, the to linearize the NTC's temperature characteristic. For a C1 and C2 must be calculated for the compensation. The given NTC, design is to get R1b and R2 and then C1 and target is to achieve the constant resistive output impedance C2. According to (4), to compensate the temperature over the widest possible frequency range. variations of the sense resistor, the error amplifier gain (Av) should have the same temperature coefficient with The pole frequency of the compensator must be set to compensate the output capacitor ESR zero : RSENSE. Hence : 1 AR fP = (11) V, HOT=SENSE, HOT (5) 2´p´´CRC ARV, COLDSENSE, COLD Where C is the capacitance of output capacitor, and RC is From (4), we can have Av at any temperature (T) as the ESR of output capacitor. C2 can be calculated as R2 AV, T = (6) follows : R1a//RNTC, T + R1b CR´ C2 = C (12) The standard formula for the resistance of NTC thermistor R2 as a function of temperature is given by : The zero of compensator has to be placed at half of the

b-éù11 switching frequency to filter the switching related noise. { ëûêú( T+273) ( 298 ) } RNTC, T= RNTC, 25 e (7) Such that : 1 C1 = (13) Where RNTC, 25 is the thermistor's nominal resistance at (R1b+R1a//RfNTC, 25) ´p´ SW room temperature, b (beta) is the thermistor's material constant in Kelvins, and T is the thermistor's actual TON Setting temperature in Celsius. High frequency operation optimizes the application for the To calculate DCR value at different temperature can use smaller component size, trading off efficiency due to higher equation as below : switching losses. This may be acceptable in ultra portable

DCRT = DCR25 x [1 + 0.00393 x (T - 25)] (8) devices where the load currents are lower and the Where the 0.00393 is the temperature coefficient of the controller is powered from a lower voltage supply. Low copper. For a given NTC thermistor, solving (6) at room frequency operation offers the best overall efficiency at temperature (25°C) yields : the expense of component size and board space.Figure 5

DS8152E/F-04 April 2011 www.richtek.com 17 RT8152E/F shows the On-Time setting circuit. Connect a resistor Soft-Start and Mode Transition Slew Rates

(RTON) between VIN and TON to set the on-time of UGATE : The RT8152E/F uses 3 slew rates for various modes of -12 14.5´10´´R2TON operation. The three slew rates are internally determined TON = (14) (VIN - VDAC) by commanding one of three bi-directional current sources

(ISS) on to the SOFT pin. The 7 bit VID DAC and the Where T ON is UGATE turn on period, VIN is Input voltage precision voltage reference are referred to RGND for of converter, VDAC is DAC voltage. accurate remote sensing. Hence, connect a capacitor On-time translate only roughly to switching frequencies. (CSOFT) from SOFT pin to RGND for controlling the slew The on-times guaranteed in the Electrical Characteristics rate as shown in Figure 6. The capacitance of capacitor is are influenced by switching delays in external HS-FET. restricted to be larger than 10nF. The voltage (VSOFT) on Also, the dead-time effect increases the effective on-time, the SOFT pin is the reference voltage of the error amplifier reducing the switching frequency. It occurs only in CCM and is, therefore, the commanded system voltage. (DPRSLPVR = 0), and during dynamic output voltage The first current is typically 20mA used to charge or transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, discharge the CSOFT during soft-start, and soft-shutdown. The second current is typically 50mA used during other the PHASE goes high earlier than normal, extending the on-time by a period equal to the HS-FET rising dead time. voltage transitions, including VID change and transitions between operation modes. The third current is typically For better efficiency of the given load range, the maximum 100mA used during Render RFM with VID change up switching frequency is suggested to be : transitions. 1 FS(MAX) =´ (15) TTON-HS-Delay The IMVP-6.5 specification specifies the critical timing associated with regulating the output voltage. The symbol, VDAC(MAX)+ILOAD(MAX)´ëûéùRON_LS-FET+-DCRRLDROOP SLEWRATE, as given in the IMVP-6.5 specification will VIN(MAX)+ILOAD(MAX)´-ëûéùRRON_LS-FETON_HS-FET determine the choice of the SOFT capacitor, CSOFT, by the Where following equation : ISS } FsMAX is the maximum switching frequency C = (16) SOFT SLEWRATE } THS- Delay is the turn on delay of HS-FET Power up Sequence } VDAC(MAX) is the maximum VDAC of application With the controller's VCC voltage rises above the POR } VIN is the maximum application Input voltage MAX threshold (typ. 4.3V), the power up sequence begins when

} ILOAD(MAX) is the maximum load of application VRON goes high. If CLKEN = 1 (Pull High), the RT8152E/F will enter CPU mode power up sequence. If } RON_LS-FET is the Low side FET RDS(ON) the CLKEN = 0 (Connect to GND), the controller will enter } R is the High side FET R ON_HS-FET DS(ON) Render mode power up sequence. } DCR is the inductor DCR L After the RT8152E/F enters CPU mode, VSEN starts

} RDROOP is the load line setting ramping up to VBOOT within 1ms. The slew rate during

power up is 20mA/CSOFT. The RT8152E/F pulls CLKEN

low after VSEN gets across VBOOT - 0.1V for 73ms. Right TON RTON R1 CCRCOT VIN after CLKEN goes low, VSEN starts ramping to first VDAC On-Time C1 Generator VDAC value. After CLKEN goes low for approximately 4.7ms, PGOOD is asserted HIGH. DPRSLPVR are valid right after

On-Time PGOOD is asserted. UVP is masked as long as VSEN is

less than VBOOT - 0.1V. Figure 7. On-Time setting with RC Filter

www.richtek.com DS8152E/F-04 April 2011 18 RT8152E/F

VCC 4.3V 4.1V

POR

VRON

VID XX Valid xx

VBOOT VBOOT - 0.1V

VSEN 0.2V

PWM Hi-Z CCM DPRSLPVR Defined CCM Pull Down

DPRSLPVR XX Valid XX

CLKEN

PGOOD

73µs typ. 4.7ms typ.

Figure 8. CPU Mode Timing Diagram for Power Up and Power Down

After the RT8152E/F enters Render mode, VSEN starts ramping up to VDAC within 1ms. The slew rate during power up is 20mA/CSOFT. PGOOD is asserted HIGH after VSEN exceeds VDAC - 100mV for 4.77ms (typ.). DPRSLPVR are valid right after PGOOD is asserted. UVP is masked as long as VSEN is less than VDAC - 100mV.

VCC 4.3V 4.1V

POR

VRON

VID XX Valid xx

VDAC VDAC-100mV

VSEN 0.2V

PWM Hi-Z CCM DPRSLPVR Defined CCM Pull Down

DPRSLPVR XX Valid XX

PGOOD

4.77ms typ.

Figure 9. Render Mode Timing Diagram for Power Up and Power Down

DS8152E/F-04 April 2011 www.richtek.com 19 RT8152E/F

Power Down If the current limit function is triggered for 15 switching When VRON goes low, the RT8152E/F enters low power cycles, OCP will be tripped. Once OCP is tripped, both shutdown mode. PGOOD is pulled low immediately and high side and low side MOSFET will be turn off, and the the VSOFT ramps down with slew rate of 20mA/CSOFT. VSEN internal discharge resistor at the VSEN pin will be enabled also ramps down following VSOFT. After VVSEN is lower than to discharge output capacitors. OCP is a latched 200mV, the RT8152E/F turns off high side FETs and low protection, it can only be reset by cycling VRON or VCC. side FETs. An internal discharge resistor at VSEN will be If inductor DCR is used as current sense component, then enabled and the analog part will be turned off. temperature compensation is recommended for proper protection under all conditions. Figure 11 shows a typical Deeper Sleep Mode Transitions OCP setting with temperature compensation. After DPRSLPVR goes high, the RT8152E/F enters deeper VCC sleep mode operation. If the VIDs are set to a lower voltage setting, the output drops at a rate determined by the load ROC1a NTC and the output capacitance. The internal target VSOFT still ramps as before, and UVP, OCP and OVP are masked for ROC1b 73ms. OCSET

ROC2 Over Current Protection Setting The RT8152E/F compares a programmable current limit Figure 11. OCP Setting with Temperature Compensation set point to the voltage from the current sense amplifier output for Over Current Protection (OCP). The voltage applied to OCSET pin defines the desired current limit Generally, the ROC1a must be selected to be equal to thermistor's nominal resistance at room temperature. threshold ILIM : Ideally, VOCSET has same temperature coefficient with VOCSET = 40 x ILIM x RSENSE (17) RSENSE (Inductor DCR) : Connect a resistor voltage divider from VCC to GND, the VROCSET, HOTSENSE, HOT joint of the resistor divider is connected to OCSET pin as = (19) VROCSET, COLDSENSE, COLD shown in Figure 10. For a given ROC2, then R = æöVCC OC2 ROC1=R1OC2 ´-ç÷ (18) V a´REQU, HOT-REQU, COLD+(1-a´)REQU, 25 èøOCSET (20) VCC V ´(1)-a CC VOCSET, 25

ROC1 ROC1b = OCSET (a-1)´R+a´-RR OC2EQU, HOTEQU, COLD (21) ROC2 (1)-a Where Figure 10. OCP Setting Without Temperature a= Compensation R DCR´[1+0.00393´-(T25)] SENSE, HOT =25HOT RT8152E/F provides current limit function and over current RSENSE, COLDDCR25´[1+0.00393´-(TCOLD 25)] protection. The current limit function is triggered when (22) inductor current exceeds the current limit threshold ILIM REQU, T = R1a // RNTC, T (23) defined by VOCSET. When current limit function is tripped, high side MOSFET will be forced off until the over current condition is cleared. www.richtek.com DS8152E/F-04 April 2011 20 RT8152E/F

For example, the following design parameters are given : Over Temperature Protection (OTP)

DCR = 1mW, VCC = 5V, IL,ripple = 9A Over Temperature Protection prevents the VR from damaging. OTP is considered to be the final protection ROC1a = RNTC, 25 = 10kW, bNTC = 3450 stage against overheating of the VR. The thermal throttling For -20°C to 100°C operation range, to set OCP trip current VRTT shall be set to be asserted prior to OTP to manage I = 28A TRIP the VR power. When this measure was insufficient to keep I=28A+=9A 32.5A the die temperature of the controller below the OTP LIM 2 threshold, OTP will be asserted and latches. The die VOCSET, 25 =40´33A´1mW=1.297V temperature of the controller is monitored internally by a RNTC, -20°C = 78.4kW, RNTC,100°C = 0.98kW temperature sensor. As a result of OTP triggering, a soft

RSENSE, -20°C = 0.82mW, RSENSE,100°C = 1.29mW shutdown will be launched and VVSEN will be monitored.

When VVSEN is less than 200mV, the driver remains in Þ ROC2 = 4.7kW, ROC1b = 8.46kW high impedance state and the discharging resistor at VSEN Over Voltage Protection (OVP) pin will be enabled. A reset can be executed by cycling VCC or VRON. The OVP circuit is triggered under two conditions:

} Condition 1 : When VVSEN exceeds 1.52V. Thermal Throttling Control

} Condition 2 : When VVSEN exceeds VDAC by 300mV Intel IMVP-6.5 technology supports thermal throttling of (typ.). the processor to prevent catastrophic thermal damage. The RT8152E/F includes a thermal monitoring circuit to If either condition is valid, the RT8152E/F latches the detect an exceeded user defined temperature on a VR LGATE = 1 and UGATE = 0 as crowbar to the output point. The thermal monitoring circuit senses the voltage voltage of VR. Turn on all LS_FETs can lead to very large change across NTC pin. Figure 12 shows the principle of reverse inductor current and potentially result in negative setting the temperature threshold. Connect an external output voltage of VR. To prevent the CPU from damaging resistor divider between Vcc and GND. This divider uses by negative voltage. The RT8152E/F turns off all LS_FETs a Negative Temperature Coefficient (NTC) thermistor and when VVSEN falls below -100mV. a resistor. The joint of the resistor divider is connected to Under Voltage Protection (UVP) the NTC pin in order to generate a voltage that is inversely proportional to temperature. The RT8152E/F pulls VRTT If VVSEN is lower than VDAC by 400mV (typ.) a UVP fault will be tripped. Once UVP is tripped, both high side and low if the voltage on the NTC pin is greater than 0.8 x V CC. low side MOSFET will be turned off, and the internal The internal VRTT comparator has a hysteresis of 200mV discharge resistor at VSEN pin will be enabled. UVP is a (typ.) to prevent high frequency VRTT oscillation when latched protection, it can only be reset by cycling VRON the temperature is near the setting point. The minimum or VCC. assertion/de-assertion time for VRTT toggling is 1.6ms (typ.). Negative Voltage Protection (NVP) VCC

During the state that VVSEN is lower than -100mV, the VRTT NTC controller will force LGATE = 0 and UGATE = 0 for CMP NTC + preventing negative voltage. Once VVSEN recovers to be - RTT higher than 0V, NVP will be suspended and LGATE = 1 + 0.8 x V will be enabled again. CC

Figure 12. Thermal Throttling Setting Principle

DS8152E/F-04 April 2011 www.richtek.com 21 RT8152E/F

Users can use the same NTC thermistor for both thermal- The VCM(MAX) must be kept equal to 1V, I(MAX) is needed to throttling and current limit setting as shown in Figure 13. follow the setting current of the IMVP6.5 definition with

Just divide the ROC1b into RTTa and RTTb, and write the various CPU. The RDROOP is the load line setting of

VNTC equation at thermal throttling temperature TT°C : applications. The VCM(MAX) is clamped not higher than 1.15V. RTTa + RTTb = ROC1b (24) There is a example for current monitor, the following design RROC2+ TTb ´VCC=´0.8VCC parameters are given : ROC2++ROC1bROC1a//RNTC, TT

(25) I(MAX) = 30A, RDROOP = 3mW, Solving (27) and (28) for R and R as : TTa TTb VCM(MAX) = 1V, RCMSET = 10kW

RTTb = 4 x (ROC1a // RNTC, TT) - ROC2 (26) Þ RCM = 55.6kW

RTTa = ROC1b - RTTb (27)

VSEN VCC Current VCC_SENSE Monitor RCMSET Generator CMSET ROC1a NTC CM VCM

VRTT RCM C1 RTTa RGND CMP NTC + - RTTb + OCSET Figure 14. Current Monitor Setting Principle 0.8 x VCC ROC2 Inductor Selection The switching frequency and ripple current determine the Figure 13. Using Single NTC Thermistor for Thermal inductor value as follows : Throttling and Current Limit Setting VVIN- OUT LT(MIN)=´ON (30) IRipple-MAX Current Monitor

Figure 14 shows the current monitor setting principle. where T ON is the UGATE turn on period. Current monitor needs to meet IMVP6.5 specification, the Higher inductance yields in less ripple current and hence RT8152E/F is based on the relation between R and DROOP in higher efficiency. The flaw is the slower transient load current to provide an easily setting and high accuracy response of the power stage to load transients. This might current monitor indicator. increase the need for more output capacitors driving the

The current monitor indication voltage VCM equation is cost up. Find a low loss inductor having the lowest possible shown as : DC resistance that fits in the allotted dimensions. The

2´ILOAD´´RRDROOPCM core must be large enough not to be saturated at the VCM = (28) RCMSET peak inductor current.

Where I LOAD is the output load current, RDROOP is the load Output Capacitor Selection line setting of applications, RCM and RCMSET is the current Output capacitors are used to obtain high bandwidth for monitor current setting resistor. the output voltage beyond the bandwidth of the converter

To find RCM and RCMSET base on : itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output RCM VCM(MAX) = (29) capacitors can be found including, bulk capacitors closely RCMSET2´´IR(MAX)DROOP located to the inductors and ceramic output capacitors in www.richtek.com DS8152E/F-04 April 2011 22 RT8152E/F

3.0 close proximity to the load. Latter ones are for mid- Four Layers PCB 2.8 frequency decoupling with especially small ESR and ESL 2.6 values while the bulk capacitors have to provide enough 2.4 2.2 stored energy to overcome the low frequency bandwidth 2.0 gap between the regulator and the CPU. 1.8 1.6 1.4 Thermal Considerations 1.2 For continuous operation, do not exceed absolute 1.0 0.8 maximum operation junction temperature. The maximum 0.6 0.4 power dissipation depends on the thermal resistance of 0.2 M a x i m u P o w e r D s p t n ( W) IC package, PCB layout, the rate of surroundings airflow 0.0 and temperature difference between junction to ambient. 0 25 50 75 100 125 The maximum power dissipation can be calculated by Ambient Temperature (°C) following formula : Figure 15. Derating Curve for RT8152E/F Package

PD(MAX) = (TJ(MAX) - T A) / qJA Layout Considerations Where TJ(MAX) is the maximum operation junction Careful PC board layout is critical to achieve low switching temperature, T A is the ambient temperature and the qJA is losses and clean, stable operation. The switching power the junction to ambient thermal resistance. stage requires particular attention. If possible, mount all For recommended operating conditions specification of of the power components on the top side of the board RT8152E/F, The maximum junction temperature is 125°C. with their ground terminals flush against one another. The junction to ambient thermal resistance qJA is layout Follow these guidelines for optimum PC board layout : dependent. For WQFN-32L 5x5 package, the thermal } Keep the high current paths short, especially at the resistance qJA is 36°C/W on the standard JEDEC 51-7 ground terminals. four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following } Keep the power traces and load connections short. This formula : is essential for high efficiency.

PD(MAX) = (12°C - 25°C) / (36°C/W) = 2.778W for } The slew rate control capacitor should be connected WQFN-32L 5x5 package from SOFT to RGND, and it should be placed physically close to IC. The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal Connect slew rate control capacitor at SOFT pin to resistance qJA. For RT8152E/F package, the Figure 15 of RGND. derating curve allows the designer to see the effect of } When trade offs in trace lengths must be made, it rising ambient temperature on the maximum power preferable to allow the inductor charging path to be made allowed. longer than the discharging path.

} Place the current sense component close to the controller. ISEN and ISEN_N connections for current limit and voltage positioning must be made using Kelvin sense connections to guarantee the current sense accuracy. The PCB trace from the sense nodes should be parallel back to controller.

} Route high speed switching nodes away from sensitive analog areas (SOFT, COMP, FB, VSEN, ISEN, ISEN_N, CM, etc...)

DS8152E/F-04 April 2011 www.richtek.com 23 RT8152E/F Outline Dimension

D D2 SEE DETAIL A

L 1

E E2

1 1 e b 2 2

DETAIL A A A3 Pin #1 ID and Tie Bar Mark Options A1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 4.950 5.050 0.195 0.199 D2 3.400 3.750 0.134 0.148 E 4.950 5.050 0.195 0.199 E2 3.400 3.750 0.134 0.148 e 0.500 0.020 L 0.350 0.450 0.014 0.018

W-Type 32L QFN 5x5 Package

Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com DS8152E/F-04 April 2011 24