A High-Efficiency CMOS Rectifier for RF Using Bulk Biasing Control Circuit

Journal of Integrated Circuits and Systems, vol. 13 , n. 2, 2018 1

1 2 3 T. O. Moraes Junior , R. C. S. Freire , and C. P. Souza

1Department of Electrical Engineering, Mauricio de Nassau University Center, Campina Grande, Brazil 2 Department of Electrical Engineering, Federal University of Campina Grande, Campina Grande, Brazil 3 Department of Electrical Engineering, Federal University of Paraíba, João Pessoa, Brazil, e-mail: [email protected]

the source and drain terminals of the CMOS transistors are Abstract— In MOSFET-transistor based rectifier circuits, clearly not continuous and, consequently, a positive poten- leakage currents occur through both source-bulk and drain- tial difference appear across the drain-bulk junction and bulk connections of their transistors causing some power dissi- across source-bulk junction causing leakage current through pation decreasing their efficiency. Such a scenario is more the respective bulk due to the appearance of parasitic di- worrying in ultra-low power circuits as those used in energy harvesting. As a solution, in this work it is proposed a control odes. circuit of transistor bulk biasing that switches the bulk bias in In order to reduce or eliminate such leakage currents, it is an efficient way assuring adequate inversion of the source-bulk shown some half-wave rectifiers in [11] and [12] that uses a and drain-bulk junctions. The rectifier based on the proposed scheme of switching the bulk terminals of the diode- bulk biasing control circuit shows to be a high-efficiency one connected transistors in order to reduce the threshold volt- capable of reducing the leakage currents. To obtain experi- age and the leakage current. In [11], as the bulk terminals mental results, the circuit was fabricated in a 130 nm CMOS process and tested on a micromanipulator. The results were are connected directly to terminals of the alternating power compared with other works where it is observed that the effi- supply, the bulk biasing voltage is not constant allowing ciency of our proposal reaches up to 72.5% or 5% higher that conduction through the drain-bulk or source-bulk junctions the best previous one. decreasing the achieved PCE. In [12] the bulk biasing is carried out by an external power supply provided by a mi- Index Terms— CMOS rectifier; bulk biasing; power con- croprobe that is unviable where such a power supply is not version efficiency. possible in practice. In [13], four additional transistors are used to bias the bulk of the bridged p-type transistors of a I. INTRODUCTION conventional full-wave rectifier to eliminate leakage cur- Ultra-low power CMOS rectifiers are applied to RFID rents (for the n-type transistors, there is no bulk biasing). [1], energy harvesting systems, biomedical instrumentation However, those additional transistors degrade the efficiency [2][3], or any electronic device that energy consumption is of the rectifier because they generate even more leakage critical. In general, researching of CMOS rectifier topolo- currents. In [14] the bulk biasing technique is applied in a gies aims to reduce voltage drop of the constituent transis- charge-pump based DC-DC converter that requires an ex- tors and to improve the power conversion efficiency (PCE) ternal clock generator for bulk biasing making it unfeasible [4-7] for energy harvesting. Some topologies of rectifier are based on: (I) Vt cancella- As an alternative to overcome these drawbacks, in this tion techniques [1][7]; (II) circuits with active-diode using work it is introduced a high efficiency low-power full-wave operational amplifiers [6][10]; (III) bridgeless AC-DC con- CMOS bridge rectifier using a proposed bulk biasing converters [6]; (IV) conventional AC-DC rectifier using transis- trol circuit (BBCC) that avoids the appearance of parasitic tors instead of diodes [9][10]. diodes and consequently leakage currents. The proposed In rectifier topologies based on Vt cancellation tech- BBCC is composed of only four additional transistors ar- nique, it is aimed to decrease the voltage drop through the ranged in a simple and innovative way and the BBCC-based rectifier to obtain larger output voltage levels across the rectifier shows to achieve a high PCE. The BBCC does not load [1][7]. However, these techniques reduce the PCE of use neither operational amplifier nor Vt cancellation tech- the rectifier, since the involved leakage currents are in- niques and, unlike the schemes of [11-14] its additional creased due to the transistors operate near the linear region transistors provide a continuous bulk voltage for self- when they are in cut-off state. Rectifiers with active-diode biasing the n-type and p-type transistors of the bridge, based on operational amplifiers [4][8] increase the energy avoiding appearance of parasitic diodes in the drain-bulk consumption since the operational amplifiers needs to be and source- bulk junctions. Plus, the proposed circuit does powered with some external power supply, which is not fea- not depend on any external power supply for bulk biasing, sible for energy harvesting, for example. Bridgeless AC-DC operating exclusively with the input alternate voltage. converters [6] use inductors that show to increase energy An integrated BBCC-based rectifier circuit was fabricat- consumption decreasing PCE. ed with a 130 nm CMOS process with its components fully In the conventional CMOS rectifier, for instance the di- integrated. Experimental results were obtained using a test ode bridge full-wave one [9], the voltage levels applied to bench containing a RF generator, a micromanipulator with microprobes and an oscilloscope. Additionally, post-layout

Digital Object Identifier 10.29292/jics.v13i2.3510.29292/jics.vXXiX.X 2 MORAES JUNIOR et al.: A High-Efficiency CMOS Rectifier for RF Using Bulk Biasing Control Circuit

simulations were performed in Virtuoso/Cadence software p-type conduction and its results were compared with the experimental ones. 0.8 Finally, an experimental comparative study with other cir- 0.6

0.4 p-type bulk (V ) cuits was carried out to demonstrate the efficiency of our out T T drain (V ) proposition. 0.2 N0 P0 A 0 n-type bulk

II. CONVENTIONAL RECTIFIER 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5 25 n-type conduction

The proposed BBCC-based rectifier circuit is based on a Voltage (V) Vin conventional full-wave CMOS rectifier, shown in Fig. 1, 0.5 which consists of two p-type transistors, TP0 and TP1, and 0 two n-type transistors, TN0 e TN1. In this circuit, when -0.5 and , TP0 and TN1 are conducting (ON) while

TP1 and TN0 are cut-off (OFF), interconnecting the load 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5 25 time (ns) to through TN1 and TP0. Similarly, when and , TN1 and TP0 are OFF while TP1 and TN0 are ON, and Fig. 2. Conduction of the drain-bulk junctions of the conventional Full- Wave CMOS rectifier. is interconnected to through TP1 and TN0. As in all situations the higher potential is interconnected to the load, on the capacitor . the voltage across in relation to ground is always positive Then, , because and . Therefore, [1]. can be expressed as (1) the sum of the current in the triode It is important to observe that the bulk biasing of the region and the current in the drain-bulk junction according transistors in ON state should be in such a way that the pn to [15][16]: junctions between source-bulk and drain-bulk of the transistors must be reversed. This biasing prevents leakage current, Wp 1 2 and transistor body-effect take places. i Cv  V v   v   I evDB nV T 1 , (1) d p oxL GS t DS2 DS S   In order that the threshold voltage has not large varia- p  tions, the bulk (B) is connected to the source (S) terminal, where represents the aspect ratio of the p-type tran- ( =0), as shown in Fig. 1. On the other hand, when sistor; the transconductance parameter; the thresh- , the drain-bulk voltage and parasite diode and leakage current appear. Therefore, in a rectifier circuit it old voltage; the saturation current of the drain-bulk junc- is important to ensure that the both source-bulk and drain- tion diode; n the ideality factor; the thermal voltage. bulk junctions are always reverse preventing leakage cur- In Fig. 1, when and , TP0 and TN1 are ON rent and unneeded power dissipation. For example, when while TP1 and TN0 are cut-off, thus the circuit current can the drain voltage ( of TP0 in Fig. 1, is equal to and its be computed based on (1) considering and bulk voltage is equal to is greater than and . Then, replacing and in (1) and let leakage current appears as can be seen in the simulation re- VDB nVT I K  I S e 1 be the leakage current, it is obtained: sults shown in Fig. 2 (red circle at p-type conduction). Simi- Wp larly, for TN0, is less than and leakage current appears ICC  p ox ... as can be seen in Fig. 2 (black circle at n-type conduction). Lp (2) Then, leakage currents exist in drain-bulk junctions for all 1 2 transistors of the rectifier shown in Fig. 1. ...VVVCAAAKVV t out V out VI   2 To compute the drain current of , for example, when is equal to , ; where and in (2), according to [15][16], can be expressed as: is the peak value of the input voltage ; is the voltage drop across the transistor; is the ripple voltage depending 1 Vout(V p  V d ) 1  , (3) 4fCL (R L r DS ) CA

because , where , load A and TN1 transistor resistance. Thus replacing in it is obtained (3). is given by, according to [15][16]: TN0 TP0 vvDS DS rDS  , (4) Vout VIN iD Wn 1 2 nC ox vGS V t v DS   v DS  novos temas novas maneirasnovas Ln 2 RL TN1 TP1 de colaborarformasCL where represents the aspect ratio of the n-type tran- C sistor. Considering and , and replacing and in (4), can be rewritten as follows: CA Fig. 1. Conventional Full-Wave CMOS rectifier. Journal of Integrated Circuits and Systems, vol. 13 , n. 2, 2018 3

2LVnC niques of bulk biasing, which is a well-known one, but nev- rDS  . (5)  CVVVVW 2 V   2   2L er applied in CMOS full-wave rectifier to the best of our n oxnt A C C C n knowledge. The BBCC, as shown in Fig. 3, operates as follows. In Thus replacing (5) in (3), the positive half of the cycle of (point A is positive with

respect to point C), when and , TN1 and TP0 1 BL 2 n Vout(V p  V d ) 1   , (6) are conducting and TN0 and TP1 are cut-off (OFF), intercon- 48fRL C L L n V C fC L necting to through TN1 and TP0. Under these condi-

tions, TP2 and TP3, are conducting ( ) connecting where: BCVVVV  WV2   2 . Therefore, to the bulk of T and T (see the red line at Fig. 4(a)) and n oxnt  A C C C  P0 P1 connecting the voltage source’s negative voltage, , to the the circuit current in (2) can be given by, replacing (6) in bulk terminals of T and T (see the purple line at Fig. (2): N0 N1 4(a)). TN2 and TN3 (see the gray line at Fig. 4(a)) are cut-off ( ). As the BB ’s transistors were designed with Wp ICVC p oxVV C  A  t  ultra-low threshold voltage 100 mV, their conduction state Lp and voltage drop occur at low voltage level and, the most 1 BL 2 important, the BBCC switching ensure that both source- (V V ) 1   n V p d A  bulk and drain-bulk junctions are always reverse preventing 48fRL C L L n V C fC L leakage current and unneeded power dissipation. 2  1  1 BL 2 n   In a similar way, in the negative half of the cycle of (Vp V)1d  VI A  K 2 48fR C L VfC  (point A is negative with respect to point C), when  L L n CL  and , TP0, TN1, are cut-off while TP1, TN0, are con- or ducting, and is interconnected to through TP1 and

TN0. Under these conditions, TN2 and TN3, are conducting III0 (7) CCK connecting to the bulk of TP0 and TP1 (see the red line at

Fig. 4(b)) and connecting to the bulk of TN0 and TN1 (see In the circuit shown in Fig. 1, the PCE can be written us- the purple line at Fig. 4(b)). TP2 and TP3, (see the gray line at ing: Fig. 4(b)) are cut-off ( ). In a general way, the BBCC maintain the drain-bulk P V 2 R junctions of T , T , T and T reversed biased through- PCE  L  out L 100 (8) N0 N1 P0 P1 0 out the positive and negative cycle of , taking close Pin Vin (IC  IK ) to zero reducing the junction leakage currents of the transistors and the channel effects related to bulk biasing, because where is the output power consumed by and is the input power delivered by the source. Other leakage currents the drain and bulk potential are about the same when TN0, are not considered because they are negligible. TN1, TP0 and TP1. To achieve this, the BBCC switches the bulk of the n-type transistors to the lowest potential (either Take in consideration (8), the greater, the lesser PCE. or and switches the bulk of the p-type transistors to In the next section a proposed solution to decrease is introduced. the highest potential (either or accordingly to the voltage polarity of (positive or negative). Additionally, as the transistor currents decrease, the on-resistance of them III. PROPOSED RECTIFIER does not increase contributing to better the efficiency. To reduce the current through the convectional CMOS full- A way to prove that the reduction of leakage currents de- wave rectifier transistor’s drain-bulk junctions and increase creases the power dissipation in TN0, TN1, TP0 and TP1 and the PCE, a bulk biasing control circuit (BBCC) is intro- increases the rectifier PCE is shown in Fig. 5, which shows duced and shown in Fig. 3. The BBCC is based on tech- the simulation results of the dissipated power by TP0, for example, in the conventional rectifier (line ) and in CA

CA Positive Negative A CA BBCC A A TN0 TP0 TN0 TP0 TN0 TP0

out V Vout VIN VIN VIN Vout N2 P2 T T TN2 TP2 TN3 TP3 N3 TP3 novas TN2 TP2 TN3 TP3 T RL RL CL RL foCrLmas CL

TN1 TP1 TN1 TP1 TN1 TP1 C C

CA CA C Negative Positive (b) CA (a)

Fig. 3. BBCC-based Rectifier. Fig. 4. cycles: (a) Positive cycle (b) Negative cycle. 4 MORAES JUNIOR et al.: A High-Efficiency CMOS Rectifier for RF Using Bulk Biasing Control Circuit

0.8 6 T conventional P0 0.6 T proposed 5 P0 0.4 p-type bulk (V ) BBCC out 4 0.2 T T drain (V ) N0 P0 A 3 0 n-type bulk

20 20.5 21 21.5 22 22.5 23 23.5 24 24.5 25 2

Voltage (V)

Dissipated Power (uW) Dissipated Power 1 Vin 0.5 0

0 -1 -60 -50 -40 -30 -20 -10 0 Input power (dBm) -0.5 Fig. 5. Output DC voltage and PCE as a function of . 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5 25 time (ns) the BBCC-based rectifier (line ). For a range of input Fig. 7. Bulk biasing voltage through several cycles to n-type and p- power, the dissipated power of BBCC-based rectifier’s P0 type transistors. is always lower than that dissipated by TP0 in the conventional rectifier. The same result happens for TN0, TP1 and I  I 0 (9) TN1. Fig. 5 also shows the dissipated power of the entire C C BBCC block (line ) that is very small, almost negligi- In this way, PCE for the proposed BBCC-based rectifier ble, because either TN2 and TP2 or TN3 and TP3 are never VR2 shorted on the same time. is given by PCE out L 100 that prove to be higher than 0 It is important to highlight that during the periods, called VIin C here dead zone as shown in Fig. 6, that the transistor switch- conventional rectifier given by (8). ing occurs ( ), that is, the periods from TN2 stops conducting to TP2 begins conducting and vice-versa (or sim- IV. RESULTS AND DISCUSSION ilarly from TN3 stops conducting to TP3 begins conducting and vice-versa), TN2 and TP2 (or TN3 and TP3) do not conduct Simulation results of the proposed BBCC-based rectifier (no short-circuited) simultaneously avoiding short-circuiting were obtained by modeling and simulation analysis using and consequently power dissipation peaks. Virtuoso/CADENCE with 130 nm CMOS process. An inte- Fig. 7 shows the bulk biasing voltage through several grated circuit was fabricated and experimental results were cycles that, as expected, the n-type transistors’ bulk voltage also obtained. The integrated circuit parameters were: is negative and the p-type transistors’ bulk voltage is posi- L = 180 nm for all transistors; W = 10 µm for TN0 and TN1, tive demonstrating that their bulk junctions are reversed. An W = 18 µm for TP0 and TP1, W = 600 nm for TN2, TN3, TP3 explanation for this is that, considering for example and and TP2; CA = 10 pF and CL = 1 pF. The test frequency was when and , , where is the 915 MHz since it is an unlicensed frequency for ISM com- voltage drop across the respective conducting transistors in monly used in other works. the BBCC. It is possible to see in Fig. 7 that the blue curve Fig. 8 shows a comparative chart with the achieved PCE crosses up the red one (at top) and down the purple one (at of the conventional rectifier and the BBCC-based rectifier bottom), but there is no conduction in these situations as the for different input power for = 2 kΩ, in which is possible concerned potential differences do not overcoming the pn to observe the greater PCE of BBCC-based rectifier. Also, as shown in Fig. 8, the rectified DC output voltage is slight- barrier potential. As then and thus , because . Since , the term ly greater as well. In order to achieve the value of that achieve the high- of (7) is approximately zero. For and , I K est PCE (efficiency), Fig. 9 shows the values of PCE for is similar. different values of and the best = 2 kΩ. Consequently, (7) can be rewritten as:

PCE proposed 80 4 PCE convencional V proposed 70 out V convencional 60 out 3

40 2

30 Efficiency (%)

20 1 voltage Output (V) DC

0 0 -25 -20 -15 -10 -5 0 5 10 Input power (dBm) Fig. 6. Dead zone of the BBCC block transistors. Fig. 8. Comparative results with the achieved PCE of the conventional rectifier and the BBCC-based rectifier for different input power for = 2 kΩ. Journal of Integrated Circuits and Systems, vol. 13 , n. 2, 2018 5

80 0.8 100 4 70 Experimental PCE 90 Experimental - voltage 60 0.6 Simulation PCE 80 Simulation - voltage PCE 50 70 Output voltage 40 0.4 60

50 2 Efficiency (%) 30

Output DC voltage Output (V) DC 40 20 0.2 Efficiency (%)

30 voltage Output (V) DC 10 20 0 0 0 1 2 3 4 5 6 10 Resistance (k) 0 0 Fig. 9. Output DC voltage and PCE as a function of . -25 -20 -15 -10 -5 0 5 10 Inout Power (dBm)

In order to achieve the value of that achieve the high- Fig. 11. Simulation and experimental results of output DC voltages and est PCE (efficiency), Fig. 8 shows the values of PCE for PCE as a function of input power. different values of and the best = 2 kΩ. bulk-source junctions of the rectifier bridge transistors and Experimental results were obtained using a test bench increase its PCE. The performance summary and compari- containing a microprobe manipulator, an RF signal genera- son with previous work are shown in Table 1. It is important tor and an oscilloscope. The entire test bench is suspended to observe that the rectifier topologies of [9] and [18] work in an aluminum cage fully grounded. from -12 dBm and -11 dBm of input power, respectively, Fig. 10 shows a photomicrograph of the fabricated recti- that are lesser than the proposed BBCC-based rectifier, but fier. their load must be greater than 1 kΩ and 68 kΩ, respec- Fig. 11 shows the comparison between the simulation tively. In [9], a 100-mV output voltage has been obtained at and experimental results of the output DC voltage and PCE a cost of a poor PCE of 5%. For its turn, the proposed cir- as a function of input power. The best result is 72.5% for cuit in [11] works from input power greater than -6dBm and -7 dBm. load value lesser than that achieved in [9] and [18], but its As shown in Fig. 11, the simulation and experimental re- obtained PCE is just 11%, that is, 61.5% lesser the proposed sults of the proposed rectifier are very close, mainly after BBCC-based rectifier. -10 dBm of input power, demonstrating that the circuit has a In [1] an output voltage of 1.5 V was obtained, but voltage good efficiency for energy harvesting applications. There is boost circuit is needed. [17] and [18] did not specify (*) the a small difference between the simulation and experimental output voltage. We conclude that, even needing input power results for values below -10 dBm due to imperfections of greater than -7 dBm, the proposed BBCC-based rectifier the manufacturing process increasing the threshold voltage achieves the best PCE, 72.5%, even using a few more tran- and delaying the conduction of the transistors. For values sistors, but considering a 2 kΩ-load. below -15 dBm, the input power is insufficient for biasing the transistors and the circuit is operational. TABLE I Some novelties have been proposed in this work, as for PERFORMANCE SUMMARY AND COMPARISON WITH PREVIOUS WORK. example: (1) no change on topology in the rectifier bridge, Input Technology Frequency Load PCE V only new interconnections are made from the bulk of the Ref. Power out (nm) (Hz) (kΩ) (%) (mV) rectifier bridge transistors to BBCC; (2) the BBCC-based (dBm) rectifier does not use any external power supply for its op- [1] 300 -6 950 M 3.7 11.0 1500 eration, depending exclusively on the voltage input power [9] 180 -12 953 M 10 67.5 600 supply ; (3) the BBCC provides a constant voltage for all [17] 350 -6 953 M 14.2 36.6 * [18] 90 -11 13.56 M 68 45.0 * bulk of the rectifier bridge transistors regardless of the po- This 130 -7 915 M 2 72.5 500 larity of ; and, as its main goal, (4) the BBCC decreases work drastically the leakage currents through bulk-drain and

V. CONCLUSION

Proposed A bulk biasing control circuit, called BBCC, for high- Rectifier CA efficiency CMOS bridge rectifier was proposed and shown to be very effective to decrease drastically the leakage currents through bulk-drain and bulk-source junctions of the transistors that form the bridge rectifier and, consequently, CL increase the efficiency of the rectifier. The proposed BBCC switches efficiently the source-bulk and drain-bulk junctions of the bridge rectifier transistors to maintain them in reverse biased. According to the experimental results achieved, the overall power efficiency obtained is 72.5% for Fig. 10. Photomicrograph of the fabricated rectifier. 915 MHz at 2 kΩ load. The proposed BBCC-based rectifier 6 MORAES JUNIOR et al.: A High-Efficiency CMOS Rectifier for RF Using Bulk Biasing Control Circuit

shows to be more efficient than other rectifiers found in re- [17] H. Nakamoto, D. Yamazaki, T. Yamamoto, H. Kurata, S. Yamada, K. cent scientific literature. Mukaida, . Ninomiya, . Ohkawa, S. Masui, and K. Gotoh “A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35 um Technology,” IEEE Journal of Solid-State Circuits, ACKNOWLEDGEMENTS vol. 42, no. 1, january 2007. [18] T. T. Nguyen, T. Feng, P. Häfliger, and S. Chakrabartty. “Hybrid The authors would like to acknowledge the financial sup- CMOS Rectifier Based on Synergistic RF-Piezoelectric Energy port from CAPES – Brazil, CNPq – Brazil, Scavenging,” IEEE Transactions on Circuits and Systems, vol. 61, no. 12, december 2014. NAMITEC/CNPq. the Postgraduate Program of Electrical Engineering (COPELE) of the Federal University of Cam- pina Grande – Brazil and the Postgraduate Program of Elec- trical Engineering of the Federal University of Paraíba – Brazil.

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