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August 24, 2018 | Equity Research Wells Fargo Technology Weekly IT Hardware & Communications Strength / Acceleration in Artificial Intelligence Continues: Data / commentary continues to highlight robust demand / market Networking expansion trends in Artificial Intelligence (AI). This week we would highlight: (1) Supermicro reported that its Accelerated Computing segment revenue grew 90% y/y. This reflects servers primarily utilizing NVIDIA GPUs and hot-swappable NVMe-based SSDs. Over the past twelve months (ending 2Q18), Supermicro’s Accelerated Computing segment revenue has grown by more than 125% y/y. (2) DigiTimes last week reported that TSMC is expected to see strong demand for 7nm and 5nm chips focused on Artificial Intelligence – expecting demand to surpass the demand for other sub-10nm chips. (3) We would highlight an article published by Semiconductor Engineering last week that discusses the changing dynamics in semiconductor architectural designs – a market moving from process technology driven innovation (node transitions) to front-end Apple iPhone Launch Expectations (September 12th; Retail Sales on September 21st?): The details on Apple’s upcoming next- generation iPhone product cycle are seemingly starting to solidify. Reports have been consistent in terms of two OLED iPhone X versions (6.5-inch and 5.8-inch) and a lower cost LCD-based iPhone (replacing iPhone SE). From a derivative perspective, we will be particularly interested in expectations that Apple’s next-gen. iPhones will expand the high-end storage capacity to 512GB (along with 64GB and 256GB capacities). We would note that the last two times Apple has increased the high-end capacities we have seen a significant increase in avg. GB/iPhone – (1) +71% to 33GB with 128GB (3Q14), and (2) +57% to 64GB with 256GB (3Q16). Apple’s iPhone has accounted for ~15% of total second half calendar year NAND Flash industry capacity demand over past two product cycles (2016 and 2017). Reports have also noted that the next-gen. iPhones could increase DRAM capacity to 4GB vs. a current total iPhone average DRAM capacity at 2.5GB. Other Topics: (1) Seagate’s HAMR Drives a 2020 Story? DigiTimes published an article highlighting an interview of Seagate SVP, BS Teh, in which it is noted that the company is currently sampling their 14TB Exos enterprise HDDs using HAMR; volume production HAMR-based HDDs would begin in 2020 at 20TB. We expect investors to become increasingly focused on Seagate’s positioning of HAMR-based HDDs versus W. Digital plans to commence production of their MAMR-based high-cap HDDs in 2019. (2) 3D NAND Thoughts: Semi Engineering published an interesting article highlighting the belief that QLC 3D NAND could prove to be a meaningful inflection point in NAND Flash vs. HDDs; noting that Toshiba’s 1.3Tb/die 96-Layer 3D NAND would be produced using a 40% smaller die size than 512Gb/die 64-Layer 3D Aaron Rakers, CFA NAND – leaving us to consider a meaningful increase in per wafer Senior Analyst|314-875-2508 capacity; Toshiba noting that “QLC will have a game-changing impact [email protected] across many different industries.” (3) Semi Engineering last week also Joe Quatrochi, CFA published an article highlighting the changing landscape of innovation Associate Analyst |314-875-2055 in semiconductors – moving from process node transitions to front-end [email protected] design and back-end packaging; low-latency memory-based data Jake Wilhelm, CPA movement becoming increasingly critical. Associate Analyst |314-875-2502 [email protected] Please see page 19 for rating definitions, important disclosures and required analyst certifications. All estimates/forecasts are as of 08/24/18 unless otherwise stated. 08/24/18 17:13:50 ET Wells Fargo Securities, LLC does and seeks to do business with companies covered in its research reports. As a result, investors should be aware that the firm may have a conflict of interest that could affect the objectivity of the report and investors should consider this report as only a single factor in making their investment decision. IT Hardware & Communications Networking Equity Research Highlighted Industry News / Thoughts: Semiconductor Engineering Highlights the Progression to 96-Layer and Beyond 3D NAND – “QLC will have a game-changing impact across many industries” Article Link: https://semiengineering.com/3d-nand-flash-wars-begin/ Last week Semiconductor Engineering published an article highlighting the NAND Flash industry’s move to 3D NAND. While much of the article is background on the industry’s ramp / progression in 3D NAND (now 70%+ of total NAND bits shipped), we thought we would highlight a few of the incremental takeaways: The article notes that vendors are expected to introduce 128-Layer 3D NAND by mid-2019, while continuing to develop technologies to 256-layer and 512-layer technologies – noting that the industry reflects a race to the highest number of stacks. Yangtze Memory Technology Corp (YMTC), backed by significant funding from the Chinese funding, is noted to move directly from 64-layer to 128-layer technology with a focus on catching up to Samsung and others in the 2020-2021 timeframe. The article notes that YMTC’s 64-layer 3D NAND has density that is close to its competitors 96-layer products, thus driving the company’s decision to skip the next step to 96-layer and move to 128-layer. The article notes that the NAND Flash industry will move to utilizing cryogenic etching, which was first introduced as a key manufacturing process in the 1980s. It also notes that new bonding and other technologies are being developed to facilitate continued layer count increases. Semiconductor Engineering notes that Toshiba’s (and thus W. Digital’s) 96-Layer (QLC) at 1.33Tb/die (~166GB/die) is a 40% smaller die size than their 64-layer product (note: our prior discussions had pointed to a 35% smaller die size for the 96-layer 512Gb die). Scott Nelson, SVP of Toshiba’s Memory Business Unit, is quoted as stating that “QLC will have a game-changing impact across many different industries.” QLC = 2x or 4x Increase in Capacity per Wafer? Based on the aforementioned details on Toshiba’s 1.33Tb/die QLC 96-layer 3D NAND (+16Gb/mm2 vs. 64L 512Gb 3D NAND at ~4Gb/mm2), we would calculate as much as a 4x increase in the implied amount of capacity per wafer produced vs. the company’s 512Gb 64-layer TLC 3D NAND. Other industry contacts have noted the following as it relates to QLC 3D NAND: 96L TLC = 40%-45% more bits per wafer than 64L TLC; QLC 3D NAND would add 28% more bits than TLC – implying a ~1.8x increase in 96L QLC 3D NAND versus +64L 3D NAND. While investors will want to consider the reliability / endurance characteristics of QLC 3D NAND vs. TLC, as well as the ramp of QLC bit contributions (IDC estimates QLC NAND to grow from ~4% of capacity shipped in 2019 to 14% by 2022), if such an increase in capacity per wafer is achievable than we would consider: (1) The ramifications on supply vs. bit demand dynamics, and (2) the ability of NAND (or SSDs) to take a meaningful next step forward in replacing HDDs (i.e., incremental focus being on expanding into nearline / high-cap HDDs over the next 3-5+ years; note that Flash capacity shipped in enterprise SSDs still stands at sub-10% of total enterprise HDD + Flash capacity shipped). Beyond 128-layer? The article notes that Samsung could move to 180- or 190-layers 3D NAND after 128-layer instead of moving to 256-layer – this coming from research by TechInsights. Lam Research has noted that it sees a path for the NAND industry to move to 256-layers using a single deck (stack) approach – noting that Samsung is focused on this architecture with its current evolution (undetermined as to how high). Micron has already been utilizing a string stack architecture at 64- layers (2 x 32-layer 3D NAND). The article notes that double-stack solutions are becoming the norm at 96-layers. The article points out that string-stacking involves the manufacturing of two device separately, and thus doubling the number of steps to make a single device, which results in increased costs and cycle times (note: our discussions in the past have highlighted 10%-20% cost added for a string-stack implementation versus a single stack die). Manufacturing Process: The article points out the manufacturing steps involved in 3D NAND, at a high-level pointing out the shift of importance moving to deposition and etch versus lithography in planar NAND shrinks. The firms step involves Chemical Vapor Deposition (CVD) that involves depositing and stacking alternating thin films on the substrate. In its July 2018 introduction of the 5th generation V-NAND, Samsung noted that it was able to achieve the technology due to enhancements in Atomic Layer Deposition. Each vendor will utilize different materials to stack layers on the substrate; precise uniformity is a critical manufacturing challenge to overcome – i.e., more layers equates to increasing layers of materials deposition and thus increasing uniformity challenges. 2 | Wells Fargo Securities, LLC Wells Fargo Technology Weekly Equity Research The equipment vendors with the leading share in total CVD include: Applied Materials (30% share in 2017), Lam Research (27%), Tokyo Electron (18%), and Hitachi Kokusai Electric (10%). Leaders in Atomic Layer Deposition include: Tokyo Electron (31%), ASM International (30%), and Lam Research (15%). The CVD equipment market, according to Gartner, was estimated at $8.2 billion in 2017, an increase of 61% y/y. In this, the Atomic Layer Deposition tools market was estimated at $1.47 billion, an increase of 45% y/y in 2017.