Tms320c6a8168, Tms320c6a8167 C6000 Dsp+Arm
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TMS320C6A8168 TMS320C6A8167 www.ti.com SPRS680C –OCTOBER 2010–REVISED MARCH 2012 TMS320C6A816x C6000 DSP+ARM Processors Check for Samples: TMS320C6A8168, TMS320C6A8167 1 Device Summary 1.1 Features 1234567891011 • High-Performance C6000™ DSP+ARM® Multiply Supported up to: Processors – 2 SP x SP → SP Per Clock – ARM® Cortex™-A8 RISC Processor – 2 SP x SP → DP Every Two Clocks • Up to 1.5 GHz – 2 SP x DP → DP Every Three Clocks – C674x VLIW DSP – 2 DP x DP → DP Every Four Clocks • Up to 1.25 GHz • Fixed-Point Multiply Supports Two 32 x • Up to 12000/9000 C674x MIPS/MFLOPS 32 Multiplies, Four 16 x 16-bit Multiplies • Fully Software-Compatible with C67x+™ including Complex Multiplies, or Eight 8 x and C64x+™ 8-Bit Multiplies per Clock Cycle • ARM® Cortex™-A8 Core • C674x Two-Level Memory Architecture – ARMv7 Architecture – 32K-Byte L1P and L1D RAM/Cache • In-Order, Dual-Issue, Superscalar – 256K-Byte L2 Unified Mapped RAM/Caches Processor Core • DSP/EDMA Memory Management Unit • NEON™ Multimedia Architecture (DEMMU) – Supports Integer and Floating Point (VFPv3- – Maps C674x DSP and EMDA TCB Memory IEEE754 compliant) Accesses to System Addresses • Jazelle® RCT Execution Environment • 512K-Bytes On-Chip Memory Controller (OCMC) RAM • ARM® Cortex™-A8 Memory Architecture • SGX530 3D Graphics Engine (available only on – 32K-Byte Instruction and Data Caches the C6A8168 device) – 256K-Byte L2 Cache – Delivers up to 30 MTriangles/s – 64K-Byte RAM, 48K-Byte Boot ROM – Universal Scalable Shader Engine • TMS320C674x Floating-Point VLIW DSP – Direct3D® Mobile, OpenGL® ES 1.1 and 2.0, – 64 General-Purpose Registers (32-Bit) OpenVG™ 1.1, OpenMax™ API Support – Six ALU (32-/40-Bit) Functional Units – Advanced Geometry DMA Driven Operation • Supports 32-Bit Integer, SP (IEEE Single – Programmable HQ Image Anti-Aliasing Precision/32-Bit) and DP (IEEE Double • Endianness Precision/64-Bit) Floating Point – ARM/DSP Instructions/Data – Little Endian • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks • HD Video Processing Subsystem (HDVPSS) • Supports up to Two Floating-Point (SP or – Two 165 MHz HD Video Capture Channels DP) Approximate Reciprocal or Square • One 16/24-bit and One 16-bit Channel Root Operations Per Cycle • Each Channel Splittable Into Dual 8-bit – Two Multiply Functional Units Capture Channels • Mixed-Precision IEEE Floating-Point – Two 165 MHz HD Video Display Channels 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2C6000, C64x+, SmartReflex, TMS320C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments. 3Cortex, NEON are trademarks of ARM Ltd or its subsidiaries. 4ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries. 5USSE, POWERVR are trademarks of Imagination Technologies Limited. 6OpenVG, OpenMax are trademarks of Khronos Group Inc. 7Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries. 2 8I C BUS is a registered trademark of NXP B.V. Corporation Netherlands. 9PCI Express, PCIe are registered trademarks of PCI-SIG. 10OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other countries. 11All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2010–2012, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C6A8168 TMS320C6A8167 SPRS680C –OCTOBER 2010–REVISED MARCH 2012 www.ti.com • One 16/24/30-Bit and One 16-bit Channel GPMC to Provide Up to 16-Bit/512-Bytes – Simultaneous SD and HD Analog Output Hardware ECC for NAND – Digital HDMI 1.3 transmitter with PHY with – Flexible Asynchronous Protocol Control for HDCP up to 165-MHz pixel clock Interface to FPGA, CPLD, ASICs, etc. – Advanced Video Processing Features Such • Enhanced Direct-Memory-Access (EDMA) as Scan/Format/Rate Conversion Controller – Three Graphics Layers and Compositors – Four Transfer Controllers • Dual 32-bit DDR2/3 SDRAM Interfaces – 64/8 Independent DMA/QDMA Channels – Supports up to DDR2-800 and DDR3-1600 • Seven 32-bit General-Purpose Timers – Up to Eight x8 Devices Total • One System Watchdog Timer – 2 GB Total Address Space • Three Configurable UART/IrDA/CIR Modules – Dynamic Memory Manager (DMM) – UART0 With Modem Control Signals • Programmable Multi-Zone Memory – Supports up to 3.6864 Mbps UART Mapping and Interleaving – SIR, MIR, FIR (4.0 MBAUD), and CIR • Enables Efficient 2D Block Accesses • One 40-MHz Serial Peripheral Interface (SPI) • Supports Tiled Objects in 0°, 90°, 180°, or With Four Chip-Selects 270 Orientation and Mirroring • SD/SDIO serial interface (1-/4-Bit) • Optimizes Interlaced Accesses • Dual Inter-Integrated Circuit ( I2C BUS®) Ports • One PCI Express® (PCIe®) 2.0 Port With • Three Multichannel Audio Serial Ports Integrated PHY – One Six-Serializer Transmit/Receive Port – Single Port With 1 or 2 Lanes at 5.0 GT/s – Two Dual-Serializer Transmit/Receive Ports – Configurable as Root Complex or Endpoint – DIT-Capable For S/PDIF (All Ports) • Serial ATA (SATA) 3.0 Gbps Controller With • Multichannel Buffered Serial Port (McBSP) Integrated PHYs – Transmit/Receive Clocks up to 48 MHz – Direct Interface for Two Hard Disk Drives – Two Clock Zones and Two Serial Data Pins – Hardware-Assisted Native Command – Supports TDM, I2S, and Similar Formats Queuing (NCQ) from up to 32 Entries • Real-Time Clock (RTC) – Supports Port Multiplier and Command- – One-Time or Periodic Interrupt Generation Based Switching • Up to 64 General-Purpose I/O (GPIO) Pins • Two 10/100/1000 Mbps Ethernet MACs (EMAC) • On-Chip ARM® ROM Bootloader (RBL) – IEEE 802.3 Compliant (3.3V I/O Only) • Power, Reset, and Clock Management – MII and GMII Media Independent I/Fs – SmartReflex™ Technology (Level 2) – Management Data I/O (MDIO) Module – Seven Independent Core Power Domains • Dual USB 2.0 Ports With Integrated PHYs – Clock Enable/Disable Control For – USB 2.0 High-/Full-Speed Client Subsystems and Peripherals – USB 2.0 High-/Full-/Low-Speed Host • IEEE-1149.1 (JTAG) and IEEE-1149.7 (cJTAG) – Supports End Points 0-15 Compatible • General Purpose Memory Controller (GPMC) • 1031-Pin Pb-Free BGA Package (CYG Suffix), – 8-/16-bit Multiplexed Address/Data Bus 0.65-mm Ball Pitch – Up to 6 Chip Selects With up to 256M-Byte • Via Channel™ Technology Enables use of 0.8- Address Space per Chip Select Pin mm Design Rules – Glueless Interface to NOR Flash, NAND • 40-nm CMOS Technology Flash (With BCH and Hamming Error Code • 3.3-V Single-Ended LVCMOS I/Os (except for Detection), SRAM and Pseudo-SRAM DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN – Error Locator Module (ELM) Outside of at 1.8 V) 2 Device Summary Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6A8168 TMS320C6A8167 TMS320C6A8168 TMS320C6A8167 www.ti.com SPRS680C –OCTOBER 2010–REVISED MARCH 2012 1.2 Applications • Machine/ Industrial Vision System • High-End Test and Measurement • Tracking and Control • Medical/Biological Imaging 1.3 Description The C6A816x C6000™ DSP+ARM® Processors are a highly-integrated, programmable platform that leverages TI's C6000 technology to meet the processing needs of the following applications: Medical/Industrial Vision Systems, High-End Test and Measurement, Tracking and Control, and Medical/Biological Imaging. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines programmable digital signal processing with an ARM® processor and a highly-integrated peripheral set. The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000™ DSP platform. The C674x floating-point DSP processor uses 32KB of L1 program memory and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining is non-cacheable no- wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining is non- cacheable no-wait-state data memory. The DSP has 128KB of L2 RAM, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip memory accesses are routed through an MMU. Programmability is provided by an ARM® Cortex™-A8 RISC CPU with NEON™ extension and TI C674x VLIW floating-point DSP core. The ARM® allows developers to keep control functions separate from A/V algorithms programmed on the DSP, thus reducing the complexity of the system software. The ARM® Cortex™-A8 32-bit RISC processor with NEON™ floating-point extension includes: 32K bytes (KB) of instruction cache; 32KB of data cache; 256KB of L2 cache; and 64KB of RAM. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs;