Private Digital Communications Using Fully-Integrated Discrete-Time Synchronized Hyper Chaotic Maps

Home , Gauss iterated map, Lorenz system, Tent map

PRIVATE DIGITAL COMMUNICATIONS USING FULLY-INTEGRATED DISCRETE-TIME SYNCHRONIZED HYPER CHAOTIC MAPS

BOSHAN GU

Submitted in partial fulﬁllment of the requirements

For the degree of Master of Science

Thesis Adviser: Dr. Soumyajit Mandal

Department of Electrical, Computer, and Systems Engineering

CASE WESTERN RESERVE UNIVERSITY

May, 2020 Private Digital Communications Using Fully-Integrated Discrete-time

Synchronized Hyper Chaotic Maps

Case Western Reserve University Case School of Graduate Studies

We hereby approve the thesis1 of

BOSHAN GU

for the degree of

Master of Science

Dr. Soumyajit Mandal 4/10/2020 Committee Chair, Adviser Date

Dr. Christos Papachristou 4/10/2020 Committee Member Date

Dr. Francis Merat 4/10/2020 Committee Member Date

1We certify that written approval has been obtained for any proprietary material contained therein. Table of Contents

List of Tables v

List of Figures vi

Acknowledgements ix

Abstract x

Chapter 1. Introduction1

Nonlinear Dynamical Systems and Chaos1

Digital Generation of Chaotic Masking7

Motivation for This Project 11

Chapter 2. Mathematical Analysis 13

System Characteristic 13

Synchronization 16

Chapter 3. Circuit Design 19

Fully Differential Operational Ampliﬁer 19

Expand and Folding function 27

Sample and Hold Circuits 31

Digital Signal Processing Block and Clock Generator 33

Bidirectional Hyperchaotic Encryption System 33

Chapter 4. Simulation Results 37

iii Chapter 5. Suggested Future Research 41

Current-Mode Chaotic Generators for Low-Power Applications 41

Appendix. Complete References 43

iv List of Tables

1.1 Different chaotic map and its system function.6

1.2 Similar factors between chaotic encryption and traditional

cryptography.8

3.1 Op-amp performance simulated using different process parameter 23

3.2 Different gate voltage of transistor in corner case simulation 23

4.1 System performance comparison between previous work and this

project. 39

v List of Figures

1.1 Two different perspectives of a 2-D nonlinear system1. (a) Time series

view. (b) Planar phase space view2

1.2 (a) Lorenz system plot with initial conditions x = -1, y = 0, z = 0. (b)

Lorenz system plot with different initial conditions.3

1.3 Bifurcation diagram of a logistic map5

1.4 Scheme of chaotic encryption system based on memristor-based

chaotic circuits2.9

1.5 (a) Experimental setup and FPGA test board2. (b) Experimental data

stream decrypted by the system2.9

1.6 Overview of the IoT data transferring and proposed improved data

communication system9

1.7 Photograph of a single hyperchaotic system implemented on a PCB

board3. 10

1.8 Block diagram of purposed discrete-time hyperchaotic encryption

system 11

2.1 Different folding function under several value of β 14

2.2 Estimated LE spectrum of proposed hyperchaotic system 16

3.1 Feedback path of Opamp4 20

3.2 Generic model with compensation for two stage ampliﬁer4 20

3.3 Schematic of op-amp structure using indirect feedback method4. 21

3.4 Generic model of opamp with indirect feedback method4. 21

vi 3.5 Block diagram of purposed two stage telescopic op-amp with indirect

feedback path. 22

3.6 Block diagram of purposed switched-capacitor common mode

feedback circuits. 22

3.7 Step response for (a) rising edge and (b) falling edge. 24

3.8 Periodic noise response. 24

3.9 Post-layout simulated AC response. 25

3.10 Block diagram of biasing circuits 26

3.11 Layout of purposed fully differential op-amp with two stage SC CMFB

circuits. 26

3.12 (a) Schematic of nonlinear function generator circuits. (b) Simulated

DC transfer function for folding point equals 1 and -1, β = 0.5. 27

3.13 Schematic of a strong-arm comparator with pre-apmliﬁer stage4 28

3.14 Clock operation of comparator in the folding function 29

3.15 Proposed fully differential folding function circuits schematic. 30

3.16 Dynamic discrete comparator based logic condition module. 30

3.17 Simulation result of folding function when β= 0.5, folded point 0.5 = − and 0.5. 30

3.18 Schematic of the sample and hold circuit. 32

3.19 Simulation results for two series connected SH circuits 32

3.20 General block diagram for non-overlapping generating circuits5 33

vii 3.21 Block diagram of purposed discrete-time hyperchaotic encryption

system. 35

3.22 2 mm 1 mm sized layout of purposed discrete-time hyperchaotic × encryption system. 36

4.1 Time series of the hyperchaotic system and zoomed-in ﬁgure. 37

4.2 (a) Phase space of the simulated data X , Y and Z . (b) Power spectrum

density of the vector output. 38

4.3 Time domain synchronization error of x, y and z channels. 38

4.4 Synchronization of X, Y state variables 39

4.5 Time series of demodulated signal at receiver. 40

4.6 Time series of demodulated signal at receiver. 40

5.1 A chaotic communication system in current mode6. 42

viii Acknowledgements

0.1 Acknowledgements

I would like to thank my advisor, Dr. Soumyajit Mandal, for his knowledge, guidance, and advice throughout my studies here at CWRU.

I would also like to thank Dr. Francis Merat and Dr. Christos Papachristou for being a part of my committee and reviewing my thesis.

Finally I would like to thank all the ICSP Lab members especially Jifu Liang, Xinyao

Tang, giving a lot of practical advice on my chip design and helping me a lot when taping out.

ix Abstract

Private Digital Communications Using Fully-Integrated Discrete-time Synchronized Hyper Chaotic Maps

Abstract

BOSHAN GU

0.2 Abstract

With the proliferation of Internet-of-Things (IoT) at public facilities, work places, the home, and beyond, securing data communications is becoming increasingly challeng- ing. This thesis describes the analysis and practical integrated circuit (IC) design of synchronized hyperchaotic maps for energy-efﬁcient private data communication between (or within) IoT nodes. The data is streaming-encrypted in the physical layer using chaotic masking and decrypted with synchronized chaotic mapping, resulting in a compact and low-power system that operates independently of the digital processor and avoids the need for analog-to-digital (ADC) conversion. The proposed private communication scheme is expected to be particularly useful for high-ﬁdelity real-time private data transmission through short-range wired links (e.g., memory and peripheral buses).

Simulation results for the proposed hyperchaotic communication system were initially obtained by implementing two identical hyperchaotic maps in MATLAB. Next, the maps were implemented on-chip using fully-differential switched-capacitor (SC)

x discrete-time circuits and simulated using Cadence design tools. The chosen SC circuit topology was used to realize low-power analog computation for the key building blocks in the hyperchaotic maps, while multiple tuning bits and a serial peripheral interface (SPI) control interface were added for changing the map parameters (thus al- lowing post-fabrication trimming and changing of encryption keys). The simulated hyperchaotic system consumes approximately 15 mW from a 2 V power supply at a clock

frequency of 2 MHz clock, and can operate at frequencies up to 10 MHz if needed. Ana-

log signals (sinusoids at 50 mVpp , 10 kHz) were directly masked using the hyperchaotic

system and successfully demasked with a synchronized map. The proposed system was

designed and laid out in the TSMC 180 nm CMOS process, where it consumes an active

die area of 2 mm x 1 mm, and is currently being fabricated.

xi 1

1 Introduction

1.1 Nonlinear Dynamical Systems and Chaos

Since the earliest beginnings, researchers and electrical engineers have solved a large

number of communication signal processing and encryption problems using a linear

paradigm that obeys the superposition principle. In essence, this viewpoint provides

a ﬁrst-order approximation of a naturally nonlinear system. However, noise and

distortion can not be safely ignored in most scenario. Moreover, those commonly used

signal functions like frequency generation and synthesis require inherently nonlinear

effects to be harnessed1. Hence, study and practical use of nonlinear dynamical system

is indispensable. Some basic concepts and technical essentials will be introduced in this

chapter.

1.1.1 Concepts and Classic Examples of Chaotic Systems

A Nonlinear system views its state temporal behavior in a phase space whereas a

linear system uses time series. In the phase space perspective, the n system states are

plotted against each other in n-dimensional space with time implicit on variable. The

phase space usually contains all possible position and momentum variables. Unlike Introduction 2

Figure 1.1(a), Figure 1.1(b) gives a more natural and obvious geometrical orbit which makes quantitatively analysis easier7.

(a) (b) Y

Time X

Figure 1.1. Two different perspectives of a 2-D nonlinear system1. (a) Time series view. (b) Planar phase space view

A Nonlinear dynamical system can be described using a set of differential equations.

For example, the differential equations for the one dimension state of a system can be written as

dx f (x) (continuous-time system) (1.1) dt =

xn 1 f (xn) (discrete-time system) (1.2) + =

for continuous time system and discrete time system, respectively.

One of the most well-known and real-world-based chaotic model is called the

Lorenz system. This simpliﬁed model was ﬁrst proposed by Edward Lorenz in 1963.

This mathematical model was used to depict natural phenomenon and forecasting

atmospheric convection8. The Lorenz equations also arise in simpliﬁed models for many objects such as lasers, brush-less DC motors, electric circuits and chemical reactions. The system can be described using ordinary differential equations now Introduction 3

known as the Lorenz equations,

  dx (y x)  dt σ  = −  dy (1.3) dt ρx y xz  = − −    dz x y βz dt = −

These equations describe a two-dimensional ﬂuid layer uniformly warmed from below and cooled from above. In Equation 1.3, the constants σ and ρ represent the system parameters proportional to the Prandtl Number and Rayleigh Number(both are dimen- sionless number in ﬂuid mechanics). The constant β refers to the physical dimensions of the layer itself. Figure 1.2 (a) shows the three-dimensional phase space plot of a

50 50

40 40

30 30 Z Z 20 20

10 10

0 0 30 30 20 -20 20 -20 10 10 0 0 0 0 -10 20 -10 20 (a) X -20 Y (b) X -20 Y

Figure 1.2. (a) Lorenz system plot with initial conditions x = -1, y = 0, z = 0. (b) Lorenz system plot with different initial conditions.

Lorenz system with initial condition equals x 1, y 0,z 0 where the physical = − = = parameters σ, ρ, and β take on the values 10, 28, and 8/3, respectively. From a technical standpoint, the Lorenz system is nonlinear, non-periodic, deterministic and highly sensitive to initial condition. Figure 1.2 (b) shows the three-dimensional evolution of two trajectories, the blue trace describes the system with initial condition ( 1,0,0) , and − the yellow trace describes the system with initial condition ( 0.5,0,0) . Two trajectories − Introduction 4

in the Lorenz attractor starting at two closely initial points differ only by 0.5 in the

X-coordinate. Initially, the two trajectories seem coincident but after some time the divergence is obvious. We can observe from the ﬁgures that only a slight change in the initial value leads to very different orbital in only a few iterations. Sometimes this behavior is referred to as the "butterﬂy effect". This kind of effect leads to a rapid loss of information and expansion of any errors, therefore making long-term weather prediction elusive.

Other autonomous one-dimensional prototypical example comes from the discrete dynamical system class known as the logistics map which is used to model population dynamics. Speciﬁcally, the word "mapping" indicates a recurrence relation in a nonlinear system9. Normally maps can be expressed by mathematical equations. The logistic map follows equation as:

xn 1 r xn(1 xn) (1.4) + = −

The interval of the system parameter r in equitation 1.4 is in [0,4] and it is calculated from the birth rate and the death rate of the species. When the system parameter r are in some certain interval, slight variations in the initial population yield dramatically different results over time which will be considered as chaotic.

Figure 1.3 shows the bifurcation diagram of a logistic map. Specifically, the cobweb image in the left part of figure indicates that when r has values of around 3.7375, the orbit keeps routing towards multiple fixed points instead of converging towards one stable fixed point. More detailed behavior is observed with different r parameter: (1) when r is between 0 to 1 the population will eventually die and it is independent of the initial population. (2) When r is between 1 and 3, the population quickly Introduction 5

Figure 1.3. Bifurcation diagram of a logistic map

r 1 approaches the value of −r and is also independent of the initial condition, the different convergence rate changes for different values of r . (3) With r increasing from 3 to

3.54409, the population will oscillate between two to eight values, then 16, 32, etc. under almost all initial conditions. The bifurcation intervals decrease rapidly and the ratio of two successive bifurcation intervals obey the Feigenbaum constant δ 4.66920. In ≈ mathematics, this behavior is an example of a period-doubling cascade. (4) r 3.56995 ≈ is the onset of chaos condition and a ﬁnite period can not be observed for almost all initial conditions. A small change of the initial condition yields dramatically different results over time. This is a prime characteristic of chaos. General chaotic behavior exists for the cases when r is larger than 3.56995 but some isolated ranges of r show non- chaotic behavior. For instance, beginning at r 3.82843, the orbit oscillates among three ≈ values, then for slightly higher value of r oscillates among six values etc. This chaotic behavior illustrates the stretching and folding over a sequence of the map iteration10.

Hence, the quality of unpredictability and apparent randomness caused the logistic map to be popular for pseudo-random number generator in early computers. Introduction 6

1.1.2 Different Types of Chaotic Maps

From the previous discussion, we know that the chaotic map is an evolution function that exhibits chaotic behavior. Chaotic and quasi-chaotic maps have been used as the basis for data and image encryption for a long time. Table 1.1 lists some chaotic maps.

µ·x¸¶ ·2 1¸·x¸ Arnold’s cat map Γ mod1 y = 1 1 y 2 Gauss iterated map xn 1 exp( αxn) β + = − + ( 2 xn 1 1 αxn yn Hénon map + = − + yn 1 bxn + =  dx y z  dt = − − Rössler system dy x ay  dt = +  dz z(x c) b dt = − + ( 1 µxn for xn 2 Tent map xn 1 < + = µ(1 x ) for 1 x − n 2 ≤ n 2 Van der Pol system d x µ(1 x2) dx x 0 dt 2 − − dt + = Table 1.1. Different chaotic map and its system function.

We can determine whether a chaotic map is continuous-time domain or discrete- time domain by its system function. Additionally, all chaotic systems are characterized by having at least one positive Lyapunov exponent (LE). The value of LE quantiﬁes the rate at which nearby trajectories in state space diverge with time along a particular dimensions, thus resulting in sensitivity to initial conditions. An M-dimensional system has a different LE along each dimension, resulting in a M-element Lyapunov vector.

Hyperchaotic systems form a subset of continuous and discrete-time chaotic systems; they are deﬁned as multidimensional systems (M 1) with two or more positive > Introduction 7

LEs. The existence of multiple positive LEs often results in several unique properties, including nearly noise-like autocorrelation functions.

The chaotic mappings listed above illustrate the potential impact of chaos on information processing. The popularity of chaos in so many topics such as communication, encryption, fractals and wavelet is a beneﬁt and a detriment to a established subject worthy of serious consideration. Further study and analysis can be found in

Anandkumar. R et al. and Jianghong.B et al.11 12

Base on the above discussion, this digital communication encryption chip is based on tent map because the function is suitable and reliable for implementing in circuit design.

1.2 Digital Generation of Chaotic Masking

As the exchange of data over the modern Internet and multimedia world is growing, information security and reliability becomes a major concern. The Internet of Things

(IoT) is rapidly growing in applications, research field and development of suitable wireless technologies. The use of IoT in different situation such as smart home, military facilities and medical care will require a more effective, confidential and lightweight communication mechanism13. Traditional cryptographic schemes are only suit for the delivering relatively small sizes file at low bit rates. Chaotic encryption becomes a preferable technique due to its highly unpredictable and random-like signal behavior.

As shown in table. 1.2, several similarity factors make chaotic encryption an attractive method for secure information transmission14. Introduction 8

Chaotic encryption Traditional cryptography Sensitivity to initial condition and parameter key Diffusion step Random behavior and orbit Pseudo-random signal Iteration through initial condition Confusion-diffusion round Key parameter of chaotic map key Table 1.2. Similar factors between chaotic encryption and traditional cryptography.

The basic process of chaotic masking is done by applying chaotic maps to provide randomness and unpredictable behavior in a few iterations. Then a reversible function of decryption is used to recover transmitted signal. The system parameters must be perfectly matched between the transmitter and receiver. Very small differences are allowed in practical circuits.

The Lorenz system and Chua’s circuits can be used for generating pseudo-random sequence and data encryption application15. The memristor Chaotic Circuit is also popular in FPGA implemented applications16. Abdulaziz H. Elsafty et al.2 develope a memristor-based chaotic circuit for text, image encryption and decryption. Their purposed system model a memristor-based chaotic circuit has been simulated and tested in the FPGA in Figure 1.4 and Figure 1.5. The S-box in the schematic provides the function of variable register and selection according to different process of chaotic for each cycle. The encryption system throughput equals 0.71 Gbit/sec based on their test results.

Knowing form ﬁgure ??, information can be easily attack on wireless node or using physcical probing during IoT communication. A light-weight and real-time private hyper chaotic system is proposed to improve the security issue. This thesis is based on the previous work done by Xinyao Tang et al.3 Figure 1.7 shows a photograph of a Introduction 9

Figure 1.4. Scheme of chaotic encryption system based on memristor- based chaotic circuits2.

1. Problem and ConventionalFigure 1.5. (a) Experimental S setupolution and FPGA test board2. (b) Experimen- tal data stream decrypted by the system2. . Information can be attacked at Wireless node; Physical Probing.

. Most conventional cipher such as data encryption algorithm (DEA) which is developed based on data encrption standard. Low speed Large data volume

Make theses cipher method not suitable for image/videoFigure 1.6. Overview of the IoT data transferring and proposed improved encryption in real datatime communication system

10 Title Suppressed Due to Excessive Length 13

0.5 ) λ

-0.5

Lyapunov exponent ( λ -1 1 λ 2 λ 3 -1.5 0 5 10 15 Normalized phase duration, T n

Fig. 11 Simulated LE spectrum of the non-ideal system dynamics as a function of the normalized hold time Tn = T/τ for β = 0.5.

The proposed circuit implementation of the hyperchaotic system was simulated in LTspice usingIntroduction manufacturer-provided device models for various values10 of fclk, i.e., Tn. The results were in good agreement with the theoretical system dynamics, but are not discussed furthersingle hyperchaotic to save system space. implemented on a 4-layer printed circuit board (PCB) that measures 15.3 cm × 12.5 cm in size. Two maps were implemented at the board level

and tested at clock frequencies up to 1.5 MHz. They demonstrated bit error rate (BER)

6 of 2×10− at a bit rate of 10 kbps and a clock frequency of 0.5 MHz, These features 7 Experimental Results≈ allow real-time transmission of compressed speech without further error correction.

Fig. 12 shows a photographIn this thesis, we of reproduce a single the hyperchaotic hyperchaotic system implementation system implemented on a custom on a 4-layer printed circuit board (PCB) that measures 15.3 12.5 cm in size. Two of these PCBs integrated circuit (IC) which will improve system speed× while reducing size and power were populated usingconsumption. nominally identical parameters in order to study synchronization and data communication applications.

Figure 1.7. Photograph of a single hyperchaotic system implemented on a PCB board3. Fig. 12 Photograph of a single hyperchaotic system implemented on a PCB. Important blocks are labeled.

Table 1 summarizes the measured electrical parameters of the two hyperchaotic systems that were implemented. Here VCC and VEE are the on-board positive and Introduction 11

This thesis is organized as follows: analysis of the hyperchaotic circuit and system character are discussed in Section2. Section 3 discus the circuits used for this hyperchaotic encryption/decryption scheme. Results are presents in Section4 and suggested future research is discussed in Section5.

1.3 Motivation for This Project

Figure 1.8. Block diagram of purposed discrete-time hyperchaotic encryption system

The ﬁrst motivation of this project is to make the private security key programmable.

As shown in figure 1.8, The chip uses serial peripheral interface (SPI) block to tune the digital-to-analog converter(DAC) which defines the system prameters to realize different sets of security key. This method is much more configurable than the previous

PCB version since changing system parameter in PCB version means re-soldering the Introduction 12

components in physical level. The second motivation is that we want to achieve smaller size and lower power consumption design which is suits for wireless application.

Besides, making compassion with the previous work is also a motivation of our project. 13

2 Mathematical Analysis

2.1 System Characteristic

In this design we implement a three-dimensional hyperchaotic map3 which (1) contains a linear transformation that locally expands the volume of phase space along several dimensions, and (2) a nonlinear map that “folds” trajectories back into a conﬁned region of phase space whenever they leave. The system can be deﬁned as

xn 1 f (Axn,β) (2.1) + =

In equation 2.1, A is the linear transformation matrix, f (x,β) is the folding function, and β is a asymmetry parameter for folding function in the interval [0,1]. f (x,β) equals

  g(x)/(1 β) ,when g(x) (1 β) and β 1  − | |≤ − >  f (x,β) (2.2) = (1 g(x))/β ,when g(x) (1 β) and β 0  − > − >   ( 1 g(x))/β ,when g(x) (1 β) and β 0 − − < − − >

In 2.2, g(x) equals (mod(x 1,2) 1) which limits the output range to [ 1,1]. The + − − partition deﬁned input intervals makes the map in either positive or negative linear Mathematical Analysis 14

slope which are 1 \ (1 β) and 1 \ β, respectively. When β 0.5, the map become − − = symmetric and equals the classic tent map. Figure 2.1 shows folding functions for 4 Xinyao Tang, Soumyajit Mandal different β values.

1 β = 0.01 0

-1 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 1 β = 0.25 0

-1 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 1 ) β = 0.5 β 0 x, ( f -1 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 1 β = 0.75 0

-1 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 1 β = 0.99 0

-1 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 x

Figure 2.1. Different folding function under several value of β Fig. 2 The proposed folding function f (x,β) for several values of the asymmetry parameter β.

Base on the study by Louis M. Pecora and Thomas L. Carroll17 the linear transforma- Lyapunov exponents (LEs) can be estimated by first finding the Jacobian J of the maption defined matrix inA is (1). defined The latter as is given by

= ,  J Da f 0Ab (4)  ·      where D f is the Jacobian of the foldingA  function0 c 1 f (x,β). Next, we denote Jn as(2.3) the =   Jacobian at time step n. The matrix Yn that describes evolution of the system till this 1 1 0 time step is given by Yn = Jn 1Jn 2 ...J0. The multiplicative ergodic theorem [18] − − then guaranteesWhen a that1, b the1 , followingc 1, the symmetricsystem is proved positive to be deﬁnite hyperchaotic matrix mathematically. (known as the Oseledec matrix)< − exists≈ | |< Here we use the default value a = -4/3, b = 1, and c1 = 1/3. Commonly people use 2n = lim (Yn)T Yn . (5) expansion rates based on so-calledn Lyapunov∞ exponents· (LEs) to quantitatively estimate → Thethe logarithms behavior of of the the system. eigenvalues Positive of exponentsare the LEs. provide a very strong indication of It is evident that is the average of JJT along the system trajectory. It can be analytically evaluated in certain cases. Firstly, since the folding function f (x,β) in (1) is independently applied to each state variable, D f is a diagonal matrix. Moreover, when β = 0 or 1, f (x) has a constant slope (1 or -1, respectively) for all x, so D f reduces to I where I is the identity matrix. Thus, in these special cases J = A, ± n ± i.e., is constant for all n. Thus, the averaging operation in (5) is not needed and each Lyapunov exponent is simply equal to λi = ln(Λi)/2, where Λi is the i-th eigenvalue of JJT = AAT. For the default set of parameters (a = 4/3, b = 1, and c = 1/3), − the resulting LE spectrum is given by (0.683, 0.302, -0.985). The presence of two positive LEs indicates hyperchaos. Moreover, in this case the sum of the LEs is zero, so the map is locally volume-preserving (VP) [19]. In the general case, i.e., for arbitrary values of β, the slopes of the upward and downward segments of the piecewise-linear folding function f (x,β) are different. Mathematical Analysis 15

chaotic behavior. Moreover, hyperchaotic systems exhibit chaotic attractors with more than one positive Lyapunov exponent18. The Lyapunov exponents describe the behavior of vectors in the tangent space of the phase space and are deﬁned from the Jacobian

∂fi matrix J in whose Ji j with the system evolution equation as x˙n f (x˙n). This = ∂x j =

Jacobian deﬁnes the evolution of the tangent vectors, given by the matrix Jn at time step n. The matrix Yn that describes evolution of the system till time step is given by Yn

= Jn 1 Jn 2...J0. − −

T 1 Λ lim ((Yn) Yn) 2n (2.4) n = →∞

The logarithms of the eigenvalues of limit Λ are LEs. LEs can be analytically evaluated in certain cases since we know that Λ is the average of JJ T along tangent space and we know in our case evolution function is equation 2.1. Because the folding function

f (x,β) in equation 2.1 is independently applied to each state variable, J f old is a diagonal matrix. Moreover, when β = 0 or 1, f (x) has a constant slope (1 or -1, respectively) for all

x, so J f old reduces to ±I where I is the identity matrix. Thus, the averaging operation in equation 2.4 is not needed and each Lyapunov exponent is simply equal to λi = ln(Λi )/2,

T T where Λi is the i-th eigenvalue of JJ = AA . For the default set of parameters, the

estimated LE spectrum is given by (0.683, 0.302, -0.985). The presence of two positive

LEs indicates hyperchaos.

Various algorithms are available for calculating LEs. The Eckmann-Ruelle method19

can numerically estimates the LE spectrum by using the neighborhood of points to

estimate the local Jacobian, and then determines the LEs from the eigenvalues of

Jacobians estimated around the attractor. Another method called the Sano-Sawada Title Suppressed Due to Excessive Length 5

Specifically, D f is either 1/(1 β) or 1/β, so J = D f A can take one of two val- − − · ues and we have to evaluate the matrix average in (5) along the trajectory to estimate LEs. Various algorithms are available for this purpose; we used the Eckmann-Ruelle method [7] to numerically estimate the LE spectrum. This method uses a small neighborhood of points to estimate the local Jacobian, and then determines LEs from the eigenvalues of Jacobians estimated around the attractor. Since the folding of the attractor brings diverging orbits back together, the algorithm tends to slightly under- estimate the positive exponents. For comparison, we also estimated the LE spectrum using the Sano-Sawada algorithm, which uses a similar approach [22]. The results are shown in Fig. 3(a) as a function of the asymmetry parameter β. For β = 0 and 1, the estimated LEs are (0.925, 0.478, -0.879) and (0.894, 0.482, -0.743) for the Eckmann- Ruelle and Sano-Sawada algorithms, respectively. These values are in good agreement with each other but somewhat larger than the theoretical ones (particularly for the first LE). Thus, the sum of the estimated LEs is positive, which corresponds to a locally volume-expanding (VE) map. Interestingly, in both cases the first two LEs are almost constant versus β, which shows that the hyperchaotic behavior is robust

Mathematical Analysisto the symmetry of the folding map. By contrast,16 the third LE is maximum for the symmetric folding map (β = 0.5) and decreases strongly as f (x,β) becomes more asymmetric. algorithm is applied for comparison20. Estimation plot is shown in the Figure 2.2 (a).

1 0.95 )

0.8 1 λ

) 0.9

λ 0.6 0.4 0.85 0.2

0 0.8 -0.2 -0.4 0.75

Lyapunov exponents ( -0.6 0.7 -0.8 Dominant Lyapunov exponent ( -1 0.65 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 Asymmetry parameter (β) (b) Asymmetry parameter (β)

Figure 2.2. Estimated LE spectrum of proposed hyperchaotic system Fig. 3 (a) Simulated Lyapunov exponent spectrum of the proposed hyperchaotic system as a function of the asymmetry parameter β using the Eckmann-Ruelle and Sano-Sawada algorithms (solid and dashed lines, respectively). (b) Simulated dominant Lyapunov exponent of the same system using the Wolf et al. algorithm. 2.2 Synchronization

Classical synchronizationGiven of the periodic well-known oscillators has numerical been known issues by discovering with the estimating the entire LE spectrum, we also estimated the dominant LE as a function of using the direct algorithm coupled form of the phenomenon in clocks on a wall. The driven or injection behavior β proposed by Wolf et al. [28], which is widely used and known to be robust for a of synchronizationvariety was discovered of dynamical later when systems. observing that The a smallresults periodic are forcing shown in Fig. 3(b). They conﬁrm the signal could causerobustness natural resonance of the of dominant a system to lock LE into with the source respect signal. to Asβ forand are also in general agreement our topic, chaoticwith synchronization those from was the ﬁrst announced LE spectrum by L.M Pecora estimationet al.21. algorithms. Then Moreover, the estimated investigation andvalue application at β based= 0 on and chaos 1 modulationis 0.655, and which demodulation matches began. the theoretical value of 0.683. Given that the various LE estimation methods are in good agreement, for the remainder of In this thesis, we use the synchronous substitution method to synchronize two nominally ideal hyperchaotic system denoted by transmitter and receiver. In this Mathematical Analysis 17

method invertible transformation T to the variable in transmitter such that w = T (xt ),

and transmit only w1 which is the ﬁrst component of w to the receiver.

1 At the receiver side, we apply inverse transformation T − to the w, so that we can

get xr by xr xt as long as the two system are nearly identical. Then we create the T ≈ r in the receiver side to get u = T (x ). Thus, by using the transmitted signal w1 for the

ﬁrst component and ui for rest of components, new vector is created wr = (w1,u2,...un)

w, instead where n is the total number of state variables. Now the receiver has the ≈ 1 r estimated state variable xt = T − (w ) updated by the received variable w1. Finally, all

component at the receiver will be synchronized to the transmitter.

The transformation T must be chosen properly to ensure synchronization. In our

case, we use xt to create additive feedback and the receiver response can be updated

r r 1 as xn 1 f (Axn CT − (wr xr ),β), where C is the coupling matrix, as simplicity we + = + −

consider C equals to the unity matrix. The coupling term Ccouple is the outer product of

1 the ﬁrst column of CT − and (w x ). So the modiﬁed Jacobian of the receiver is r − r

J J (A C ) (2.5) r = · − couple

We select wn = Γxn - zn in our system with three state variables x, y and z. We also

r use zn as our driving variable. Then the update equations at receiver are governed by

  r r t  xn 1 f (axn bzn,β)  + = +  yr f (c yr zt ,β) (2.6)  n 1 = n + n  +   r r r  zn 1 f (xn yn,β) + = + Mathematical Analysis 18

According to the equation 2.1, possible eigenvalues of the receiver Jacobian matrix are deﬁned by the (a bΓ,c,0)/(1 β), and (a bΓ,c,0)/β since the possible value for ± − − ± − folding function we used is 1/(1 β) and (1 β). The magnitudes of all eigenvalues ± − ± − must be < 1 to keep the receiver system stable. Asymmetric parameter β and the system parameters c are limited by each other. Moreover (a bΓ) limits the useful range of Γ. | − | For our default setting with a 4/3,b 1, and β = 1/2, it becomes 4/3 Γ < 1/2, the = − = | − − | useful range is 11/6 Γ 5/6. − < < − Robustness of synchronization is also studied in Xinyao Tang et al’s previous work.3 which suggests that state variables are sensitive to noise in various degrees, with x and

y having the lowest and highest sensitivity, respectively. Because the transmitter and receiver system may not reach the folding point simultaneously, small synchronization errors may occur in the absence of noise due to the sudden loss of synchronization. This effect is weakest when β = 1/2, so we chose that β value for our circuit implementation. 19

3 Circuit Design

To interface with various IoT applications, the proposed hyperchaotic system is designed and fabricated in TSMC 180 nm CMOS process. In detail, ﬁgure 1.8 shows the block diagram of our proposed hyperchaotic system, which includes (1) a tunable linear transformation for volume expansion on state parameter; (2) two nonlinear blocks: modulus and bounds for discrete tent mapping; (3) a conventional sample-and-hold block for the state iterations on parameters (e.g., x, y and z); and (4) other minor blocks include i) the driving variable generator for chaotic masking; ii) linear operation for chaotic demasking; iii) Serial Peripheral Interface (SPI) and biasing generator. Tx/Rx mode is hard coded on printed circuit board (PCB).

3.1 Fully Differential Operational Ampliﬁer

The operational ampliﬁer (op-amp) is a fundamental building block in analog integrated circuit design which has been implemented in many electric circuits. An op- amp produces an output potential that is typically hundreds or thousands of times larger than the potential difference between its input terminals. Engineers use them to perform mathematical operations in many linear, non-linear, and frequency-dependent Chapter 24 Operational Amplifiers I 777

Vout AQLU) ACL(/) = (24.5) l + p-Aodf) If we take AOL(/) —> °°, then the closed loop gain of this non-inverting topology is **<'>-F = 1+fe (24.6) We have several important points that we need to discuss. To begin, notice that in Eq. (24.5) if

V-AOLW) = -\ (24.7) or more precisely Circuit Design 20 \P-AOL(/)\ = 1 and Zß ■A0Uf) = ± 180° (24.8) the closed loop gain blows up (the feedback amplifier becomes unstable). The worst case situation (the largest value of ß) occurs when all of the output is fed back to the op-amp circuits22. Since the real world contains non-ideal effects, many enhanced op-amp are input (assuminChaptegr 2n1o Amplifier transformers , amplifier, etc. in the feedback path). The 67voltag9 e follower, Fig. 24.7, is an example of this situation. To determine the stability of an designedop-amp, we to '11 improve look at the the operatingopen loop gain frequency, when the linearity, feedback stabilityfactor is one, and that the is, close loop gain. Why the name pole splitting? If we increase the effective size of CgM by placing a capacitor, C , from the amplifier's input to its output (so that C is in parallel with C , There are severalc techniques\A0L(f)\ we need= 1 an tod considerZA0L{f) = in 180 our°c design. First(24.9 we dl) use indirect that is, the effective value is Cc + CgM), then, as Eq. (21.56) shows, the low-frequency Notice thalocatiot the nlarge of thre thpole,/e close, , decreasesd loop . gainAt th,e thsame esmalle time, increasinr the valug thee effectivof ß (the size eles of sC outpugdl t feedbacksignal we tofeecause improved backs the locatio) an thed nth oe stabilityf morthe high-frequence likel behaviory they op-ampole/ and, pa scircuit speed. seen in, Eqwit From. h(21.62) feedback Figure, to increase, wil 3.1l . b ,Thue we stables know. that the name pole splitting. This is important. While feedback helps to desensitizVoute an amplifier'AOL(f ) s gain to variations in the closed-loop gain of the op-amp ACL(f ) = . The feedback ampliﬁer an op-amp'Poles A Splitting, the drawbac Summaryk is stability. In a high-performancVin 1 βAOLe (op-amf ) p that will never OL = + operate in a unity-follower configuration, we can get an enhancement in speed by will becomeBecaus unstablee of the ubiquit wheny βofA pole( splittinf ) g i1,n CMO withS Aamplifiebecomesr design, let'1 s assummariz A reachese our inﬁnity. reducing thdiscussioe amounn tusin ofg compensatio a generic OLmodeln (th, =Fige −.amoun 21.25. tI no fterm thCLes reductioof the parametern guideβ s dsee bOLyn Eqin thi. (24.8s ) with the actuafigurel valuthe locatioe of nß oused)f the zer. Whilo is noew thi s discussion has focused on the non-inverting Hence in order to get acceptable phase margin we want the open loop gain of the op- topology (voltage or series-shunt amplifiers, ß =gml Vflv ) a similar discussion can be given fz = out (21.63) for the inverting amplifier (shunt-shunt where 2nß =■ Ciflvc t) topology, see Sec. 30.2. amp to be much less than one when the phase shiftou is 180 . The first pole is located at ◦

1 (21.64) 2JI[(CC + C2) • Ri + (Ci + C„(l +gmiR2)) -R\] we can Vout For large gain, gm2R2 > simplify this to 1 (21.65) /i* 2ng 2RiR\C m c ß = VflVout The second pole is located at

gmlCc /2«: (21.66) 2jt-(CcCi+CiC2 + CeC2) The transfer function is then written as

V( V w-£ AAf)= -^r£=grnxR\gn,2R2- Aodf) > (21.67) O - / K. J_ ' 1+7 Vf Wß 1 > ' where Av = gm\RigmiRi (the gain is now positive because of the defined direction of the current source in Fig. 21.25). < - ß — i— Again note that if Cc is increased, /, moves downwards and f2 moves upwards (pole splitting). Also note that if the capacitor, C , is made large (quite common), then/ c 4 Figure 24.is muc6 Ah nlowe examplr thane Figure thoef locatiofeedbac 3.1.n kof ith Feedbackne a nothe op-ampr pole patho, rse thee zerSec ofo Opamp. (th30.e 2pol foer associate additionad withl discussion/ is .

Cc ©

gml -© :*,. 4=Ci (T)£»2VI£Ä2 ^=c2 vout

1 ^ !—

4 Figure 3.2.Figur Generice 21.25 Generi modelc mode withl used compensationto estimate bandwidthfor in a twoCMOS stage amplifier ampliﬁer.

The basic idea of compensation is commonly used in ampliﬁer design. For example, applying pole splitting in circuits, the lower frequency pole f1 will move downwards in 784 CMOS Circuit Design, Layout, and Simulation

VDD VDD VDD VDD Circuit Design 21 M4 -C M4A Vl © c ICc frequency and the higher frequency pole f2 will go3 in the opposite direction by adding a Cc © MCG v0B, = v2 compensation capacitor to the feedback path. For the^ generic two stage op-amp model Vuc 5 3 1 in Figure 3.2 of two stage ampliﬁer, f1 for large second stage gain when ≈ 2πgm2R2R1Cc * bias A n n p gm2Cc f2 . But there is a more practical and effective method called indirect 2π(CcC1 C1C2 CcC2) ≈ + + ^ 1, 784feedback. Figure 3.3 and its small signalCMO modelS Circui shownt Design in Figure, Layout 3.4 ,suggest and Simulatio smartern way Figure 24.17 Feeding back a current indirectly to avoid the RHP zero. Vout Vout 4 − A2 to compensate the op-amp . The current feedback through Cc is icc and icc To determine the frequency response of this amplifier, consider the =mode1/l jsee wCnc in Fig. 24.18 (modified from Fig. 21.25). Summing the currents at node 1 gives VDD VDD VDD VDD

M4 Vl Vout -gmlVs + = 0 (24.13) ÄIIIT-C V M4Uj

To determine the frequency response of this amplifier, consider the model seen in Fig. 24.18 (modified from Fig. 21.25). Summing the currents at node 1 gives

Vl Vout C2 vout -gmlVs + = 0 (24.13) ÄIIITV Uj

Plugginand betterg Eq. (24.14 power) supplyinto this noise equatio rejection.n gives . Cc

-^TT-v0Ut + vs Vout = -gm\R\gmlR2 ' (24.16) (l+j

C2 vout

Figure 24.18 Model used to estimate bandwidth when indirect feedback current is used. Circuit Design 22

VDD Vb1 Vb1

Vb2 Vb2 Vb2

Vb3

Vout+ Vout- ibias Vin- Vin+

Vbias

Vcmfb2 Vcmfb1 Vcmfb2

Figure 3.5. Block diagram of purposed two stage telescopic op-amp with indirect feedback path.

The NMOS-pair fully-differential op-amp structure we use in our design is shown in

Figure 3.5. We apply here fully differential design rather than single-ended to improve

the CMRR (common-mode rejection ratio). Since we determine to operate our system

VDD in discrete fully differential design, we need common mode feedback circuits for the

op-amp. Figure 3.6 shows the structure we apply in the op-amp circuit. Vb2 Vop Von φ1 φ2 φ2 φ1 Vcm Vcm Vout+ C1 C2 C2 C1 Vin- φ1 φ2 φ2 φ1 Vbias Vbias

Vcmfb

Figure 3.6. Block diagram of purposed switched-capacitor common mode feedback circuits.

Unlike the common mode output DC voltage can stabilize using negative feedback

in single-ended design. Discrete - time fully differential op-amp must use switched - Circuit Design 23

GBP(Hz) Phase margin(deg) tt 130M 64◦ ss 104M 66◦ ff 160M 60◦ Table 3.1. Op-amp performance simulated using different process parameter

Vb1(V) Vb2(V) Vb3(V) Vb4(V) tt 1.41 1.1 806m 574m ss 1.37 1.06 842m 616m ff 1.46 1.14 771m 540m Table 3.2. Different gate voltage of transistor in corner case simulation

capacitor (SC) common mode feedback(CMFB) circuits to force the output DC voltage maintain in its operating point23. With a high-speed clock in the system, the above feedback function can be achieved following these steps: (1) When φ1 is close, Vcm and Vbi as charge to C1, (2) next when φ2 is close, voltage stored on C1 transfers to the

Vop /Von (Op-amp output stage) node and Vcm f b (current mirror biasing node), (3) After a few clock cycles output stage and the biasing node will fall within the same value as the same as Vcm or Vbi as.

In the Cadence simulation tool, data in table 3.1 and 3.2 are captured using periodic static state (PSS) and periodic AC(PAC) simulation under the basic operation for normal process parameter and corner case. These frequency response suggests the reliability and stability after taking the unpredictable unbalance and non-ideal effects introduced during foundry into account.

Simulation results for basic op-amp circuit operation is shown below. From Fig- ure 3.7, we can get that the time constant τ is around 0.05 µs with a 1% error, which indicates the maximum clock frequency is around 1/2τ 10 MHz. In Figure 3.8, periodic = noise response shows that ﬂicker noise is dominant over the bandwidth of interest. Circuit Design 24

(a) (b)

Figure 3.7. Step response for (a) rising edge and (b) falling edge.

Figure 3.8. Periodic noise response.

Post simulation results shows in Figure 3.9 indicate 88 MHz gain band product and

60◦ phase margin for AC response.

In analog circuits, speciﬁc DC voltage and current is required for transistors to reach proper operating point. Based on our knowledge, MOSFET has different operation mode depending on the terminal voltage. In practical it is more complex than the algebraic model we learned from the book. To ensure the transistor is operating in our desired region, current mirror circuits is essential24. The fundamental concept of current mirror is to implement the principle that if a gate-source voltage of two uniforms

MOS transistors is same then their channel current ﬂowing would be equal. In the Circuit Design 25

Figure 3.9. Post-layout simulated AC response.

current mirror, we generate a current reference so to copy that current in various current sources in the top-level system.

Speciﬁcally, we can analysis the biasing circuits from the current source in most left side of the Figure 3.10. In out design, desired sinking current source value is 1/4 of the current in single branch for op-amp. Since the P-mos which at the top of the current source share the same component parameter (transistor size) and Vg s and Vdsat to the second branch P-mos, the current sinking in the second branch is the same as the ﬁrst branch, identically. The NMOS component parameter in the second branch has been adjusted until the Vg s of the cascade NMOS in the third branch equals to desired VDD

Vb2 Vop Vom φ1 φ2 φ2 φ1 Vcm Vcm Vout+ C1 C2 C2 C1 Vin- φ1 φ2 φ2 φ1 Vbias Vbias Circuit Design 26 Vcmfb

VDD

Vbp Vb1

Vb3 Vbp

Vb3 Vb2 Vb2

Vb3 Vb3 Vb4

Vb4 Vb4

GND

Figure 3.10. Block diagram of biasing circuits

value (V ), according to I = W/L (V V )2. Because the top P-mos in third cm f b D ∝ g s − th branch sinking the same amount of current as the first branch and those two NMOS are the same, once the cascade NMOS in the third branch reach the saturation region, the biasing NMOS in the bottom is also in the saturation region. The same principle in the fourth and fifth branch to make precise current flow in the fifth branch.

Figure 3.11. Layout of purposed fully differential op-amp with two stage SC CMFB circuits. 10 Xinyao Tang, Soumyajit Mandal

K-1 Response r w* n Circuit Design Variable - 27 f K Γ clk Linear Transformation Sample Γ xn+1 A xn & hold a 0 b Finally, the layout ofΓx then+1 proposed fully differential op-ampSample is shown in Figure 3.11. yn+1 = 0 c 1 * yn & hold 1 1 0 Sample With two CMFB circuits in each side,z commonn+1 centroidzn structure was apply when laying + Tx/Rx & hold out the differential pair to minimize the mismatchModulus of etching.Bounds Driving Out wn+1 +1 Out Variable +1

In -2 -1 1 2 In -2 -1 1 2 -1 -1 mod{In + 1, 2} - 1

Fig. 7 Block diagram of the proposed discrete-time hyperchaotic system for a clock frequency of fclk. The 3.2main Expand blocks include and the linear Folding transformation, function tent map function (modulus and bounds), and sample and hold circuits.

The linear transformation and folding function circuits are shown in Figure 3.12, vOUT are the input and output voltages, respectively. When vIN > VP (i.e., for larger fundamental function of the circuit is built by the comparison circuits| | including strong- input voltages), the voltage v1 (which is generated by the op-amp U3) is subtracted from v , thus implementing the folding operation. The correct region of operation ARM comparator,OUT inverter and NOR gate. But since our system is no longer continuous- is determined by the comparators U4, U5, and U6 (which compare vIN with VN, timeground, based, and someVP) modiﬁcation and two single-pole as well as double-throw improvement (SPDT) are explained analog in switches. this part.

VN VP

2R − U4 R Simulated − 2 Ideal + R U3 + − U5 1 VN 2R v1 + 0 − U6

+ VP -1 R Output voltage (V) R 2R R − R -2 vIN U1 − vOUT + U2 (a) + -5 -3 -1 1 3 5 (b) Input voltage (V)

Figure 3.12. (a) Schematic of nonlinear function generator circuits. (b) Fig. 8 (a) Schematic of the nonlinear function generator circuit. (b) Simulated DC transfer function of the circuitSimulated using LTspice DC transfer for V = functionV = 1 for V. The folding ideal pointfolding equals function 1 for andβ = -1,0.β5= is 0.5. also shown for P − N comparison.

For the case when folding point V = V = 1, V = 2V when V < V . And Apart from op-amps (LT1364,n Linear)− p and analogOUT switchesIN (TS12A4517,| IN | p Texas whenInstruments),VIN > Vp , V theOUT circuit= 2(VIN is implemented2). Thus makes using the high-speed system function comparators as tent map (LT1394, as shown Lin- ear) and two-input NOR gates− (74LVC2G02, NXP) with propagation delays of 7 ns ∼ in Figureand 1.8 3.12 ns, (b) respectively. indicates. The unit resistance value is R = 1 kΩ, but slightly lower values (985 Ω) are used to compensate for the 15 Ω on-resistance of the analog ∼ switches when necessary. Chapter 27 Nonlinear Analog Circuits 919

VDD VDD VDD VDD T T

Out

In+_ MB1 MB2 ||—m~

Figure 27.15 A clocked comparator based on Figs. 16.32 and 16.35.

Our modification is seen in Fig. 27.16. Instead of biasing the PMOS and NMOS diff-amps with a bias circuit, here, to be different, we simply use long-length MOSFETs. The bias currents aren't too critical in this application (like they are in an op-amp design). We can still use a bias circuit if controlling the bias current is, for some reason, important. We've removed the triode-operating MOSFETs MB1 and MB2 from the basic cross-coupled latch section. Now we are steering currents from one side of the latch to the other. The differences in the currents causes the latch to switch dependent on the input signalsCircuit. Not Designe that if either of the diff-amps isn't present in the comparator or if one is off 28 because the comparator's input common-mode voltage is too high or too low, the comparator still works as desired. Only one diff-amp is needed to create the imbalance. Also noteAs, for again the, improvementthat the SR latc weh is done used into makingmake the folding outputsfunction, of the circui ﬁrstt chang we takee on a th looke at rising edge of the clock signal. If the outputs of the comparator can go high, for a particulastrong-Armr application comparator, whe25n 26thwithe cloc pre-ampliﬁerk signal is circuitlow the wen usethe inNAN logicD conditiongates can module.be removed. We build a discrete-time comparator used the schematic in Figure 3.134.

j-c| r Long L rC( H H l0^/^ L J >

Figure 3.13. Schematic of a strong-arm comparator with pre-apmliﬁer stage4 Figure 27.16 Wide-swing clocked comparator. Outputs change on the rising edge of the clock signal. Take one comparison results shown in Figure 3.14 which was simulated in Cadence

simulation tool as an example. We have two clock phase (1) PH1 for operation cycle and

(2) PH2 for reset cycle since the entire system is discrete-time application. Green signal

and the pink signal are one comparator’s input signal V and V respectively. Orange + − signal is the system Operating phase PHI1. Signal in the middle sub window is the

positive output of the comparator while the purple clock signal is the comparator clock

signal. It can be easily found that frequency of clock for comparator is doubled of the

system clock. This is a commonly used method to acquire more accurate comparison

results and eliminating the glitch. Hence correct output of comparator only occurs in

the second half cycle of PH1. Moreover, it reaches the resolution around 50mV after

doing linear sweep simulation which is sufﬁcient for general digital signal transmitting

or the lower resolution analog signal.

The linear transform matrix is implemented in our system by fully differential

summing or subtracting circuits based on the op-amp mentioned above. As for the

folding function circuits and logic condition module, Figure 3.12 and Figure 3.16 Circuit Design 29

Figure 3.14. Clock operation of comparator in the folding function

indicate similar function as the previous work by Xinyao Tang et al. which we talked before. Logic circuits generate the WP,WN,SN,SP switch signal to switch to different

condition under various input voltage. Switched-capacitor structure is used here to

realize discrete-time application as well as improve the noise performance4. Moreover

this design is more ﬂexible when reproduce the application in integrated circuits level

rather than printed circuits board level. Here we make β default value which equals to

0.5, but we can still make the folding point changeable by reserving the pin in chip so

that the range of the folding function can be easily changed via reference voltage off

chip.

And the simulation results prove that this folding function is almost ideal except for

the input value Vnx almost reaches the VDD or ground (VIN = 1.9 V, IN = 0.3 V for VCM + − = 1.1V) which means the op-amp is no longer behave linearly. VDD Vop Vom φ1 φ2 φ2 φ1 Vcm Vb2 Vcm

C1 C2 C2 C1 φ1 φ2 φ2 φ1 Vbias Vbias Vout+ Vin- Vcmfb

VDD

Vbp Vb1

Vb3 Vbp

Vb3 Vb2 Vb2

Vb3 Vb3 Circuit Design Vb4 30

Vb4 Vb4

GND

Vcm Vcm Vcm Vcm φ2φ2 φ2φ2

φ1 φ1 φ1 φ1 φ2 φ2 φ2 Vcm Vcm Vcm Vcm Vcm Vcm

VP VN φ2 φ2 φ2φ2 Vcm φ2φ2

φ1 φ1 φ1 φ1 φ1 φ1 Vin+ + - + - + - Vout+ + Vin- - + - + - Vout- φ1 φ1 φ1 φ1 φ1 φ1

φ2 φ2 φ2 φ2 Vcm φ2φ2

Vcm Vcm Vcm Vcm Vcm Vcm φ1 φ1 φ2 φ2 φ2 φ1 φ1

VP VN φ2φ2 φ2φ2

Vcm Vcm Vcm Vcm

Figure 3.15. Proposed fully differential folding function circuits schematic.

Op-amp Sample-and-Hold Sample-and-Hold Folding function adder/subtractor circuits circuits

Figure 3.16. Dynamic discrete comparator based logic condition module.

Figure 3.17. Simulation result of folding function when β= 0.5, folded point 0.5 and 0.5. = − Circuit Design 31

3.3 Sample and Hold Circuits

Sample and hold circuits are widely used in linear system and they are important building blocks in data-converter systems. The circuits sample the voltage of a continuously varying analog signal and holds its value at a constant level for a speciﬁed minimum period of time. Switched-capacitor techniques take advantage of the excellent properties of on-chip capacitors and MOSFET switches therefore permit the realization of numerous analog sampled-data circuits. Figure 3.18 suggests the schematic we used in our design. When φ1 is closed, differential input signal is fed into the buffer sized ampliﬁer, in φ2 phase, capacitors are disconnected from the input signal while the voltage of feedback capacitor at the output node is stored during the last sample phase.

Although capacitors are invariably discharged by their own leakage currents and load current, the voltage drop within a speciﬁed hold time remains in an acceptable error margin.

In our system, sample and holds are mainly used as clocked delay elements for iterating the state variables. Each delay is implemented using two sample-and-hold circuits that are connected in series and clocked on opposite phases. Sampled sine data is used as an example in Figure 3.19 to illustrate the function of series connected operation. The blue-color clock signal is φ1 and the pink-color clock signal is φ2 in the bottom sub window. The second sample and hold circuits store the previous state of value of the ﬁrst sample and hold circuits, which make the output of second SH circuits delay half cycle of the clock frequency. VDD

Vb2 Vop Vom φ1 φ2 φ2 φ1 Vcm Vcm Vout+ C1 C2 C2 C1 Vin- φ1 φ2 φ2 φ1 Vbias Vbias

Vcmfb Circuit Design 32

Vcm

φ1

Vcm φ2 φ2

Vcm φ2 φ1

φ1 Vout- Vin+ + - Vin- - + φ1 Vout+ φ2 φ1 Vcm φ2 φ2

Vcm

φ1

Vcm

Figure 3.18. Schematic of the sample and hold circuit.

Figure 3.19. Simulation results for two series connected SH circuits Circuit Design 33

3.4 Digital Signal Processing Block and Clock Generator

The biggest motivation to reproduce the application in chip level is that we will get a

more complex encryption key by adding tuning bit of the system parameter a, b, c and

Γ. With proper choice of the capacitor value in the DAC, four parameter can be easily

changed by the SPI block. The approximated range of the four parameters are : -2.4 a ≤ -1, 1 b 1.8, 0.0625 c 1 and 1 Γ 1.8. Proceeding of the 2011 IEEE Students' Technology Symposium ≤ ≤ ≤ ≤ ≤ ≤ ≤ 14-16 January, 2011, lIT Kharagpur The chip uses an SPI block which consist of 16 shift register to slave the four 4-bit Plot for frequency of oscillation for given number of stages

35�� r=�==�==�� - -�-�- - - -analytical results DAC for a,b c and Γ since we do not need to change1 our bit values frequently. The\ data -- Simulation results fOSC= -- (17) \ 2 n"cp 30 \ N pin and the chip selectwhere pin 'rp helps is the writingaverage propagation external signals delay and into n theis the chip accordingI to the � c 25 number of delay stages in series. Fig. 5 clearly shows that o correct address27. the frequency of oscillation calculated using delays obtained � � 20 from Section IV closely follow the simulated results. '0 g 1 Two D type ﬂip ﬂops and non-overlappingTABLE I generating circuits are used� to5 generate DELAY COMPARISON OF CASCADED SIMPLE INVERTER WITH PROPOSED I BLOCK FROM RING OSCILLATOR 1 different frequency clocks for our system. We use the delay of inverted inverters0 to make

Cascaded Simple Inverter Proposed Delay Block � 5 L-� 4 6��8��1��1��1-4 �16��18�� the delay chain and theTransistor delay Count time can be4 easy adjusted using4 multiple unity inverted 0 2 20� 22 No. of Stages T 145 ps 7.2 ns 5 inverter . Fig. 5. Plot for frequency of oscillation for given number of stages

f---,------oph i 1 clock in and simple inverter. Fig. 6 shows that as non-overlap period increases the area benefitsdrawn from this technique increases. It may be noticed that since the proposed delay block does not have a rail to rail swing, additional two CMOS inverters may f----'-----Oph i2 be used as buffers at the end of delay chain to make the signal swing rail to rail. This justifies the additional four transistors in the transistor count of NOC generators. Figure 3.20. General blockFig.diagram 4. Block diagram for non-overlapping of NOC generator generating circuits5 TABLE III FREQUENCY COMPARISON OF RING OSCILLATOR TABLE II COMPARISION OF ANALYTICAL AND SIMULATED RESULTS Simple Inverter Proposed delay block

Stages Transistor Count Analytical Simulated Frequency 27.7 MHz 27.7 MHz fose fose No. of Stages 503 5 3.5 Bidirectional Hyperchaotic5 24 Encryption32.4 MHz 27.7 MHz System Transistor Count 1006 24 7 32 23.19 MHz 20.8 MHz Ide 8.95 rnA 112 JlA 9 40 18.D3 MHz 16.5 MHz Pde 16.01 mW 201.6 JlW In summary, the entire chipII block48 diagram 14.75 in MHz Figure 13.72 3.21 MHzcontains: (1) FourIal'g biasing 63.05 JlA 75.17JlA 13 56 12.48 MHz 11.5 MHz Pavg 113.5 JlW 135.3 JlW 15 64 10.82 MHz 10 MHz circuits. ibi asQ for two SH17 circuits as72 buffer and9.54 MHz two op-amp8.6 MHz adder/subtractor,ibi asX 19 80 8.54 MHz 7.7 MHz TABLE IV 21 88 7.73 MHz 7.2 MHz RING OSCILLATOR SIMULATION USING PROPOSED DELAY BLOCK

No. of Stages 5 7 9 The traditional NOC generator block diagram is as shown Frequency of Oscillation 27.7 MHz 20.82 MHz 16.49 MHz in Fig. 4. We know that, if 'rp is the delay of 1 block, then Transistor Count 24 32 40 n'rp is the delay of n such blocks in series. Since the non Ide 112 JlA 172.2 JlA 182.5 JlA overlap period of a NOC generator is the delay offered by the Pde 201.6 JlW 265.1 JlW 328.5 JlW delay chain, the number of stages of delay blocks required to Iavg 75.17 JlA 83.8 JlA 92.17 JlA achieve a given non-overlap period is directly given by Pavg 135.3 JlW 150.8 JlW 165.9 JlW Desired non overlap period No. 0f stages = ------'--'-- (18) 'rp The layout of a NOC generator, as shown in Fig. 7 was Knowing the delay offered by the proposed delay block, designed [19] using UMC 180nm process in Cadence envi the number of stages required to achieve a given non-overlap ronment. 84 stages of the proposed block was used in the period can be easily calculated and verified. delay chain covering a total area of around 250.um x 160.um. Table IV compares the transistor count required to achieve a Simulation results are shown in Table VI. This NOC generator given non-overlap period when using the proposed delay block was used to integrate a dc signal generated on chip.

TS11VLSIOP045 229 Circuit Design 34

,Y and Z are biasing three state variable linear transform and folding function circuits.

(2) Two output buffer used for sampled x and z state variables. (3) Two op-amp

Adder/subtractors. One is for creating driving variable wn at transmitter side and solving state variable Z at receiver side (using the output of those two sample and hold circuits). Another is for decoding the transmitted signal using one of the received variable and its estimation signal. (4) Linear transformation and folding function circuits block for three state variables. (5) Frequency divider for clock: create CLK (for comparator) PHI1 (sample) and PHI2 (reset/hold) using two D ﬂip-ﬂop and a non- overlapping clock generator. (6) Create inverted signal to control transmission gate using inverters. (7) SPI block to control four 4-bit DAC.

Besides the normal signal and biasing node for Op-amp, IBN and IBP is for

comparator biasing. EN is control signal to enable the initial condition signal. ENS

is the clock ( much slower than the system clock )to sampling in the transmitted signal.

VP/VN is the comparator reference signal.

For the transmitter we use x and z buffer output (which is the same as the state variable iteration loop output) to create driving variable wn and send it to the receiver.

As for the receiver, one op-amp adder/subtractor is used for extracting z using wn and

x, and decoding transmitted signal using the other. Two systems can synchronizing

in a few cycles and the circuit works properly in corner case simulations. Hence the

demodulation block denoted by * in the chip block diagram will not be used in the

receiver system.

The chip uses 22 op-amps in total and has 51 pins including VDD and ground as

shown in Figure 3.22. The chip is 2 1 cm2 area, including the pads and die seal ring. × The power consumption is 15 mW under a 2 V power supply. Circuit Design 35

VDD VDD VDD VDD

Bias Bias circuits circuits VbiasQ VbiasX ibiasQ ibiasX ibias2 ibias1 ibias3 ibias4 ibias5 ibias6 ibias_a ibias_c ibias_b ibias_d ibias_a * 3 biasing circuits for driving variable X,Y and Z X 3 XSHin+ + - XSHout- SH circuits SPI out XSHin- - + XSHout+ B3 B2 A3 A2 B1 B0 A1 A0 ibiasX ibiasY IBP ibiasZ IBN

Xout1+ ibias_b Xin+ Xout1- Linear Transformation Zout1+ Xin- Zout1- Yin+ and folding function with two stage SH circuits Xout+ ZSHin+ + - ZSHout- Yin- Xout- Zin+ Yout+ SH circuits Zin- ZSHin- + ZSHout+ X 3 Yout- - Zout+ Zout- C3 C2 C1 C0 SPI out EN SPI out ibias_c T0 T1 T2 T3 EN_bar VinitY- VinitY+ VinitX- VinitZ- VinitX+ VinitZ+ Inv EN_bar XWin+ EN XWin- Opamp ZWin+ Wout+ ENS Inv ENS_bar ZWin- Adder/Subtractor Wout- Vsigin+ with 4-bit DAC Vsigin- PHI1 Inv PHI1_bar

*Driving variable generator ENS ENS_bar CLK2 Inv CLK2_bar ibias_d PHI1 Inv PHI1_bar

ZR+ ZR- Opamp Vsigout+ CLK ZR2+ adder/subtractor Vsigout- D Q D Q ZR2- D flip-flop D flip-flop CLK2_bar CLK Q_bar CLK2 CLK Q_bar *Demodulation block

PHI1 Non-Overlapping PHI2

VDD Vb1 Figure 3.21. Block diagram of purposed discrete-time hyperchaotic encryptionVb2 system.Vb2 Vb2 Vb3

Vout+ Vout- Vin- Vin+

Vbias

Vbias Vcmfb Vcmfb Circuit Design 36

Figure 3.22. 2 mm 1 mm sized layout of purposed discrete-time × hyperchaotic encryption system. 37

4 Simulation Results

Typical output can be found in Figure 4.1 for the basic operation with a 2 MHz clock frequency. Time series data refers to continuing iteration with its own state variable.

Relatively noiseless signal and its good boundary meets the analysis in previous chapter and indicates the reliability of the entire system. Features such as randomness, and white spectra are observed shown in Figure 4.2. Note that the power spectrum will reach the lowest level at the system clock frequency.

Figure 4.1. Time series of the hyperchaotic system and zoomed-in ﬁgure.

In order to characterize synchronization performance, the two systems are conﬁg- ured as transmitter and receiver. Figure 4.3 shows the error between the transmitter and receiver among three state variables z, y and z. Two systems can synchronize Simulation Results 38

(a) (b)

Figure 4.2. (a) Phase space of the simulated data X , Y and Z . (b) Power spectrum density of the vector output. with each other in a few clock cycles. No obvious deviation is observed in the x and

y variables (z variable is the driving variable so zr and zt should be identical when there is no interference among trace) shown in Figure 4.4 indicates good performance of this hyperchaotic mapping.

2.5

1.5

0.5 Voltage(V) 0

-0.5

-1

-1.5 0 0.5 1 1.5 2 2.5 3 Time(s) 10-5

Figure 4.3. Time domain synchronization error of x, y and z channels.

Figure 4.5 simulates the data demodulation process where the message data is a

50 mV, 10 kHz sine wave. As we described in Section 3.5, demodulated data is recovered Simulation Results 39

(a) (b)

Figure 4.4. Synchronization of X, Y state variables

Previous Version New Version Size 15 cm x 15 cm 2 mm x 1 mm Encryption Key Fixed Programmable Frequency 5 MHz 10 MHz Power Consumption 2.1 W 15 mW Table 4.1. System performance comparison between previous work and this project. by the demodulation block by subtracting estimated variable and received variable. A

100 kHz switch signal is used at transmitter to down-sample the message and then add this down-sampled message to the driving variable w. The RMS noise is around

3 6.5×10− under 50 mV peak to peak voltage in Figure 4.6. All the features mentioned above match our previous mathematical analysis and verify good performance of the integrated circuit design.

Table 4.1 shows the comparison of the previous work and this work. Our work achieves better performance and ﬂexible design by implementing the purposed hyper chaotic system in integrate circuit. Chaotic Demodulation Data demodulation a 50mv 10 KHZ sine wave using 2MHz Clock . As sampling signal enabled. The signal will be demodulated using state vector Simulation Results. Slower sampling rate than the system clock, need couple40 of cycles to return synchronize state

Sampled signal Demodulated signal Enable Chaotic Demodulation Data demodulation a 50mv 10 KHZ sine wave using 2MHz Clock . As sampling signal enabled. The signal will be demodulated using state vector . Slower sampling rate than the system clock, need couple of cycles to return synchronize state (b)

(a) (a) Demodulated sine signal at receiver Figure 4.5. Time series of demodulated signal at receiver. 6 (b) Sampled data vs. input data Sampled signal Demodulated signal Enable

(b)Figure 4.6. Time series of demodulated signal at receiver.

(a) (a) Demodulated sine signal at receiver 6 (b) Sampled data vs. input data 41

5 Suggested Future Research

5.1 Current-Mode Chaotic Generators for Low-Power Applica-

tions

Current-mode circuits usually can operate with low power supply voltages because of the small voltage swings associated with the low-impedance nodes. The use of current rather than voltage as the active parameter gives the advantage of higher usable gain, accuracy and bandwidth due to reduced voltage excursion at sensitive nodes.

Besides, current-mode approach is not just restricted to current processing, but also offers certain important advantages when interfaced to voltage-mode circuits28. That

makes current mode circuits attractive to implement low power design especially for

IoT applications.

In Joseph E. Varrientos et al.’s work6, they present an efﬁcient current-mode

approach to synchronous chaos for signal encryption using simple current integrators,

current mirrors, and a simple current Schmitt trigger. Because summation is a necessary

operation for signal encryption, current signals are a natural solution since these

signals can be summed at a single node. Also, the use of current-mode integrators I -AI LIENARD DRIVING, ...... SYSTEM

I 1 I-

ci I @ U Fig. 2: Block Diagram- of Chaotic Synchronous Non-Linear Lienard System. IV. CURRENT-MODEIMPLEMENTATION

...... The proposed current-mode implementation is given in HYSTERESIS CURRENT BUFFER Fig. 3(a) and Fig. 3(b). The driving system is shown in Fig. Fig. 3(a): Circuit Diagram of Driving System. 3(a), while the response systems is shown in Fig. 3@). The two circuits are connected by the node v,. The uppennost The response system in Fig. 3(b) is identical to the subcircuit for the driving system shown is an unstable driving system, except in two important ways, as mentioned Lienard oscillator. Transistor MI and capacitor C 1 comprise in section 11. First, note the omission of capacitor C1 in the a simple current integrator, biased by the current source 11. response system. Thus, M1 of the response system is used to Transistor M2 and capacitor C2 comprise the second current mirror the current in the first integrator of the driving integrator. Transistor M7 and the current mirror M6M5 system, and only one integrator appears in the response provide positive feedback around the first integrator as system. Also note the omission of the feedback current from Suggestedshown in Fig. Future2. Transistor Research pair M3M4 mirror and invert the current buffer. This feedback current for the response 42 the current from the second integrator. The current buffer system becomes an output current for the synchronized comprised of transistors M17 and M18 is used to remove response system. one high impedance node from the Lienard oscillator, which would normally have two such nodes if the circuit was

I -AI designed literally from Fig. 2. Since the input impedancesLIENARD of RESPONSE SYSTEM LIENARD DRIVING, ...... SYSTEM , ...... the integrators are extremely high, the circuit's performance would become asymptotically unstable for practical output conductances. The use of the current buffer removes this v'v dynamic tension from the oscillator loop, without changing x':p the fundamental dynamics of the system. Y

I 1 I- The current in the second integrator is mirrored by , ...... , ...... ,...... transistor M18 and provides the input current to the ', :: :: ', hysteresis shown in the lower left portion of the driving system[3]. The width of the hysteresis is controlled by current source 12. Transistors MI4 and M15 provide output ci I @ U current for the hysteresis circuit. Transistors M15 and MI6 help to further reduce the value of the output current by Fig. 2: Block Diagram of Chaotic Synchronous Non-Linear Lienard System. - forcing transistors M14 and M15 into their linear regions IV. CURRENT-MODEIMPLEMENTATION during each transition of the hysteresis. The output current is then summed with the output currents from the oscillator ...... at the input of the current buffer. The output current from , The proposed current-mode implementation is given in HYSTERESIS CURRENT BUFFER Fig. 3(a) and Fig. 3(b). The driving system is shown in Fig.the buffer is then fed back to the input of the first current HYSTERESIS I OUT CURRENT BUFFER Fig. 3(a): Circuit Diagram of Driving System. 3(a), while the response systems is shown in Fig. 3@). Theintegrator. Fig. 3(b): Circuit Diagram of Response System. 6 two circuits are connected by the node v,. The uppennost The responseFigure system 5.1. in Fig. A chaotic3(b) is identical communication to the system in current mode . subcircuit for the driving system shown is an unstable driving system, except in two important ways, as mentioned Lienard oscillator. Transistor MI and capacitor C 1 comprise in section 11. First, note the omission of capacitor C1 in the a simple current integrator, biased by the current source 11.takes response advantage system. Thus, of M1 the of inherentthe response system low voltageis used to swings and good linearity of current-mode Transistor M2 and capacitor C2 comprise the second current mirror the current in the first integrator of the driving134 integrator. Transistor M7 and the current mirror M6M5 system, and only one integrator appears in the response provide positive feedback around the first integrator circuits.as system. As Also shown note the omission in Figure of the 5.1 feedback, fewer current component from were used in the application. shown in Fig. 2. Transistor pair M3M4 mirror and invert the current buffer. This feedback current for the response the current from the second integrator. The current buffer system becomes an output current for the synchronized comprised of transistors M17 and M18 is used to remove response system. one high impedance node from the Lienard oscillator, which would normally have two such nodes if the circuit was RESPONSE SYSTEM LIENARD designed literally from Fig. 2. Since the input impedances of , ...... the integrators are extremely high, the circuit's performance would become asymptotically unstable for practical output conductances. The use of the current buffer removes this v'v dynamic tension from the oscillator loop, without changing x':p the fundamental dynamics of the system. Y

The current in the second integrator is mirrored by , ...... , ...... ,...... transistor M18 and provides the input current to the ', :: :: ', hysteresis shown in the lower left portion of the driving system[3]. The width of the hysteresis is controlled by current source 12. Transistors MI4 and M15 provide output current for the hysteresis circuit. Transistors M15 and MI6 help to further reduce the value of the output current by forcing transistors M14 and M15 into their linear regions during each transition of the hysteresis. The output current is then summed with the output currents from the oscillator at the input of the current buffer. The output current from , the buffer is then fed back to the input of the first current HYSTERESIS I OUT CURRENT BUFFER integrator. Fig. 3(b): Circuit Diagram of Response System.

134 Bibliography 43

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