CSE 675.02: Introduction to Computer Architecture State Elements

Register File Design • Unclocked vs. Clocked • Clocks used in synchronous logic and – when should an element that contains state Memory Design be updated?

Falling edge cycle time

Presentation E

Slides by Gojko Babić Clock period Rising edge

07/11/2005

An unclocked state element Latches and Flip-flops

• The set-reset latch • Output is equal to the stored value inside the element (don't need to ask for permission to look at the – output depends on present inputs and also on value) past inputs • Change of state (value) is based on the clock R • Latches: whenever the inputs change, and the clock is Q asserted • Flip-flop: state changes only on a clock edge (edge-triggered methodology)

Q S A clocking methodology defines when signals can be read and written — wouldn't want to read a signal at the same time it was being written D-latch D flip-flop

• Two inputs: • Output changes only on the clock edge – the data value to be stored (D) D D Q D Q D D Q – the clock signal (C) indicating when to read & store D latch latch Q Q • Two outputs: C C – the value of the internal state (Q) and it's complement C

D C Q D C

C _ Q Q Q D

Register File

Our Implementation • The register file includes 32 32-bit registers, as it is needed for 32 general purpose registers of MIPS architecture

• An edge triggered methodology 5 Read register num ber 1 Read 32 • Typical execution: data 1 5 Read register – read contents of some state elements, num ber 2 Register file – send values through some combinational logic 5 Write – write results to one or more state elements register Read 32 Write data 2 State State 32 element Combinational logic element data Write 1 2 Figure B.8.7

• This register file makes possible to simultaneously read from Clock cycle two registers and write into one register as it is appropriate for MIPS processor. g. babic Presentation E 8 Register File Functioning Register File Design: Read Part

• The given register file functions as follows: – any value provided on 5-line Read register number 1 Read register number 1 port makes that content of corresponding register is Register 0 5 Read register Register 1 M number 1 Read 32 provided on 32-line Read data 1 port data 1 u Read data 1 5 Read register x – any value provided on 5-line Read register number 2 Register n – 1 number 2 Register n Register file port makes that content of corresponding register is n=31 Write Read register register provided on 32-line Read data 2 port number 2 Read 32 Write data 2 – on the falling edge of write line, values that appear on data Write M 32-bit Write data port are written into the register with u Read data 2 the number on 5-line Write register port. x Note that requirements for set-up time (and hold time) Figure B.8.8 also apply here. This is a design at a level of register and complex multiplexer.

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Register File Design: Write Part Introduction to Memory Design

• Main memory is built in one of two technologies: Write

C –SRAM- Static Random Access Memory 0 Register 0 1 D Read register – DRAM - Dynamic Random Access Memory number 1 Read 5 n-to-1 C Register number data 1 decoder Register 1 Read register • A memory is normally built using a number of memory D n – 1 number 2 chips. n Register file 5 Write n=31 register • Memory chips have specific configurations given as a C Read Register n – 1 32 Write data 2 product of two number, e.g. D data Write C – 128K*1 - 128K addressable locations with 1 bit in each 32 Register n location, i.e. width of read/write operations is 1 bit Register data D Figure B.8.9 – 16K*8 - 16K addressable locations with 8 bits in each location, i.e. width of read/write operations is 8 bits This is a design at a level of register and decoder. • Notice that two chips above accommodate identical We are now going to design the MIPS register file at a level of number of bits (128K bits). flip-flop, basic multiplexer and decoder. • Both memories are volatile.

g. babic Presentation E 11 g. babic Presentation E 12 SRAM and DRAM: 1 Bit Memory Cell DRAM Technology Characteristics Since 1975, the main memory is composed of semiconductor • In SRAM technology, a three-state D-latch is the DRAM’s (Dynamic Random Access Memory). basic building block, i.e. basic memory cell. DRAM chip capacity had been growing at rate of about 4 times Internally, a D-latch can have a state corresponding every three years, while lately growth slowed down to 2 times to 0 or 1. every two years. • In DRAM technology, the basic memory cell is built Currently, maximum DRAM chip capacity is 512M bits with an access time in the range 40-60 nsec and a cycle time of about around one capacitor coupled with one transistor. 80 nsec. The value in the cell is stored as a charge. A Access time & cycle time are two measures of memory latency: charge can not be stored indefinitely and DRAM • access time – the time between a read is requested and when chips must be periodically refreshed. Since charges the desired content arrives, can be kept for several msec, 1-2% of time is used • cycle time – the minimum time between two memory requests. for refreshing. For DRAM technology cycle time is longer than access time. For SRAM technology access time and cycle time are identical.

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Growth of Capacity per DRAM chip Prices of Six Generations of DRAMs

Figure 1.13

g. babic Presentation E 15 g. babic Presentation E 16 SRAM Technology Characteristics Memory Chip Functioning

15 • SRAM – Static Random Access Memory technology is Example: 32K×8 chip Address normally used for caches. • read and write Chipselect operations are 8 bits 8 • In comparable technologies, SRAM cycle time is about 8 to 16 RAM Read enable Dout[7–0] times faster than DRAM, e.g. currently 0.5-5 nsec. wide 32K × 8 • there are 32K • Since SRAM address lines are not multiplexed, there is no Write enable addressable locations 8 difference between access time and cycle time. D in[7– 0] • But, SRAM chip capacity (as well as density) is roughly 4 to 8 • Functioning of memory chip: times less than that of DRAM –CS (Chip select) has to be set for either reading or writing • Also SRAM is more expensive, e.g. 1GB in 2004 $4,000 – –R (Read enable)=0 & W (Write enable)=0 Æ chip is not being accessed – R=0 and W=1 Æ write values at Din lines into the chip address at $10,000 for SRAM and $100 – $200 for DRAM. Address lines • In addition, SRAM chips have higher power consumption and – R=1 and W=0 Æ read into Dout lines values from the chip address at power dissipation than DRAM chips. Address lines – R=1 and W=1 Æ not allowed • Thus SRAM designs are concerned with speed, while in DRAM Two designs of memory chip: – Basic structure design designs the emphasis is on cost per bit and capacity. – Typical organization design g. babic Presentation E 17 g. babic Presentation E 18

Basic Structure Design of 4×2 SRAM Chip Design of Memory Chip Basic Structure

2 Address • The design of the basic structure of SRAM chip uses some Chip select Chip Select SRAM 2 Output enable Dout[1– 0] 4 × 2 ideas from the register file design e.g. the write parts in two Din[1] Din[0] Write enable 2 designs are identical. The main differences are in read part Read Enable Din[1– 0] D D D D design. In the memory chip with the usage of three-state D- Writeenable C latch Q C latch Q Enable Enable latches a multiplexer is eliminated. E.g. for 32K*8 SRAM 0 chip, a multiplexer with 32K inputs each input having 8 lines 2-to-4 D D D D decoder would be needed. C latch Q C latch Q Enable Enable 1 • But for design of the basic structure of SRAM chip, we still need a very large decoder. E.g. for 32K*8 SRAM chip, a D D D D Address C latch Q C latch Q decoder with 15 input lines (that is not so bad) and 32K Enable Enable 2 output lines (that is bad) is required. Typical organization of SRAM uses two level decoding that eliminates need for that D D D D C latch Q C latch Q very large decoder. Enable Enable 3 Figure B.9.3

Dout[1] Dout[0] g. babic Presentation E 19 g. babic Presentation E 20 4×2 Array of D- Latches Typical Organization Design

The next example will be using 512×64 array • Example: Design (read part only) a typical organization (i.e. two level Chip Select of D-latches. decoding design) of 32K×8 SRAM chip that uses 512*64 arrays of D- Din[1] Din[0] latches. Read Enable D D D D • Note: Arrays used have to have a bit capacity equal to a number of Writeenable C latch Q C latch Q addressable locations in the chip, e.g. in this example that condition Enable Enable 0 is satisfied since 512*64 = 32K. A number of arrays used should be E equal to the number of bits in each memory location. 2-to-4 C D D D D decoder C latch Q C latch Q 9-to-512 512 × 64 512 × 64 512 × 64 512 × 64 512 × 64 512 × 64 512 × 64 512 × 64 Enable Enable decoder 512 SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM 1 Address E [14– 6]

C D D D D Address C latch Q C latch Q

Enable Enable 64 2 Address E [5– 0]

C D D D D Mux Mux Mux Mux Mux Mux Mux Mux C latch Q C latch Q Enable Enable 3 Dout7 Dout6 Dout5 Dout4 Dout3 Dout2 Dout1 Dout0 E C DRAM memory chip would have similar design. g. babic Dout[1] Dout[0] 21 g. babic Presentation E 22

Main Memory Specification Main Memory Specification: Example 1 • A memory has identical inputs and outputs as memory chips, • Provide inputs and outputs of 128MByte memory with 8-bit except that CS does not exist. But the specification of a read/write operations and byte addressability. memory should include: Note that 8-bit read/write operations requires byte a. memory capacity (usually in bytes), addressability. b. memory addressability, i.e. smallest unit that has its

address, WE MemWrite d. width of read/write operations, i.e. a number of bits that can be read or written from/to memory. 27 8 Address Read • Operations on memory: reading from memory and writing into data 128MB Dout memory; 8 Write =128M units data – RE=0 and WE=0 Æ memory is not being accesses Din – RE=0 and WE=1 Æ writing into memory

MemRead – RE=1 and WE=0 Æ reading from memory RE – RE=1 and WE=1 Æ not allowed

g. babic Presentation E 23 g. babic Presentation E 24 Main Memory Specification: Example 2 Main Memory Specification: Example 3

• Provide inputs and outputs of 128MByte memory with 32-bit • Provide inputs and outputs of 128MByte memory with 32-bit read/write operations and byte addressability. read/write operations and 32-bit addressability.

WE MemWrite WE MemWrite

27 32 25 32 Address Read Address Read data data 128MB Dout 128MB Dout 32 Write =128M units 32 Write =32M units data data Din Din

MemRead MemRead RE RE

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Steps in Memory Design Memory Design: Example 1

1. determine inputs and outputs for a memory to be design and • Design 128MByte memory using 32M*8 chips, with 8-bit memory chips that are being used; read/write operations and byte addressability. 2. determine number of memory chips needed; 3. determine number of memory chips in each set; a number of CS Dout and/or Din lines in the set should be identical to number of WE MemWrite 25 Dout and/or Din lines in the memory; Address 27 8 4. determine number of sets; Address Read data 5. allocate sufficient number of memory address lines to select Dout 8 128MB R 32M×8 each of sets: those are the most significant address lines Write 8 =128M units Dout data W 6. allocate next set of memory address lines as inputs to all Din memory chip address lines; 8 Din MemRead 7. If the number of bits in read/write operations equals the number RE of bits in addressability, then all memory address lines are used up in steps 5 and 6. Number of chips needed: 4 8. When condition in 7 is not satisfied Æ go to slide 26 Number of chips per set: 1 9. Connect Din and Dout lines of memory and chips Number of sets: 4 g. babic Presentation E 27 g. babic Presentation E 28 Memory Design: Example 2 Memory Design: Example 3

• Design 512MByte memory using 64M*4 chips, with 8-bit • Design 128MByte memory using 128M*1 chips, with 8-bit read/write operations and byte addressability. read/write operations and byte addressability.

CS CS

WE MemWrite MemWrite 26 WE 27 Address Address

29 8 27 8 Address Read Address Read data data Dout 4 Dout 1 512MB R 64M×4 128MB R 128M×1 8 Write =512M units Dout 8 Write =128M units Dout data W data W Din Din 4 1 Din Din RE MemRead MemRead RE Number of chips needed: 16 Number of chips needed: 8 Number of chips per set: 2 Number of chips per set: 8 Number of sets: 8 Number of sets: 1 g. babic Presentation E 29 g. babic Presentation E 30

Memory Design: Example 4 Steps in Memory Design (continued)

• Design 128MByte memory using 8M*8 chips, with 32-bit • This is the second part of step 7 in “Steps in Memory Design” read/write operations and 32-bit addressability. slide:

CS – when the number of bits in read/write operations is greater WE MemWrite 23 than the number of bits in addressability, then some lowest Address order memory address lines are not used 25 32 Address Read data – if the width of read/write operations doubles that of 128MB Dout 8M×8 8 R addressability then the least significant memory line is 32 Write =32M units Dout data W Din unused, 8 Din – if the width of read/read operations is 4 times greater than RE MemRead the number of bits in addressability then the two least Number of chips needed: 16 significant memory lines are unused, etc. Number of chips per set: 4 • Note, it doesn’t make sense to have the width of read/write Number of sets: 4 operations smaller than addressability. g. babic Presentation E 31 g. babic Presentation E 32 Memory Design: Example 5

• Design 128MByte memory using 8M*8 chips, with 32-bit read/write operations and 8-bit (byte) addressability.

CS WE MemWrite 23 Address

27 32 Address Read data Dout 8 128MB R 8M×8 32 Write =128M units Dout data W Din 8 Din RE MemRead Number of chips needed: 16 Number of chips per set: 4 Number of sets: 4 g. babic Presentation E 33