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Register File Design and Memory Design State Elements An CSE 675.02: Introduction to Computer Architecture State Elements Register File Design • Unclocked vs. Clocked • Clocks used in synchronous logic and – when should an element that contains state Memory Design be updated? Falling edge cycle time Presentation E Slides by Gojko Babić Clock period Rising edge 07/11/2005 An unclocked state element Latches and Flip-flops • The set-reset latch • Output is equal to the stored value inside the element (don't need to ask for permission to look at the – output depends on present inputs and also on value) past inputs • Change of state (value) is based on the clock R • Latches: whenever the inputs change, and the clock is Q asserted • Flip-flop: state changes only on a clock edge (edge-triggered methodology) Q S A clocking methodology defines when signals can be read and written — wouldn't want to read a signal at the same time it was being written D-latch D flip-flop • Two inputs: • Output changes only on the clock edge – the data value to be stored (D) D D Q D Q D D Q – the clock signal (C) indicating when to read & store D latch latch Q Q • Two outputs: C C – the value of the internal state (Q) and it's complement C D C Q D C C _ Q Q Q D Register File Our Implementation • The register file includes 32 32-bit registers, as it is needed for 32 general purpose registers of MIPS architecture • An edge triggered methodology 5 Read register num ber 1 Read 32 • Typical execution: data 1 5 Read register – read contents of some state elements, num ber 2 Register file – send values through some combinational logic 5 Write – write results to one or more state elements register Read 32 Write data 2 State State 32 element Combinational logic element data Write 1 2 Figure B.8.7 • This register file makes possible to simultaneously read from Clock cycle two registers and write into one register as it is appropriate for MIPS processor. g. babic Presentation E 8 Register File Functioning Register File Design: Read Part • The given register file functions as follows: – any value provided on 5-line Read register number 1 Read register number 1 port makes that content of corresponding register is Register 0 5 Read register Register 1 M number 1 Read 32 provided on 32-line Read data 1 port data 1 u Read data 1 5 Read register x – any value provided on 5-line Read register number 2 Register n – 1 number 2 Register n Register file port makes that content of corresponding register is n=31 Write Read register register provided on 32-line Read data 2 port number 2 Read 32 Write data 2 – on the falling edge of write line, values that appear on data Write M 32-bit Write data port are written into the register with u Read data 2 the number on 5-line Write register port. x Note that requirements for set-up time (and hold time) Figure B.8.8 also apply here. This is a design at a level of register and complex multiplexer. g. babic Presentation E 9 g. babic Presentation E 10 Register File Design: Write Part Introduction to Memory Design • Main memory is built in one of two technologies: Write C –SRAM- Static Random Access Memory 0 Register 0 1 D Read register – DRAM - Dynamic Random Access Memory number 1 Read 5 n-to-1 C Register number data 1 decoder Register 1 Read register • A memory is normally built using a number of memory D n – 1 number 2 chips. n Register file 5 Write n=31 register • Memory chips have specific configurations given as a C Read Register n – 1 32 Write data 2 product of two number, e.g. D data Write C – 128K*1 - 128K addressable locations with 1 bit in each 32 Register n location, i.e. width of read/write operations is 1 bit Register data D Figure B.8.9 – 16K*8 - 16K addressable locations with 8 bits in each location, i.e. width of read/write operations is 8 bits This is a design at a level of register and decoder. • Notice that two chips above accommodate identical We are now going to design the MIPS register file at a level of number of bits (128K bits). flip-flop, basic multiplexer and decoder. • Both memories are volatile. g. babic Presentation E 11 g. babic Presentation E 12 SRAM and DRAM: 1 Bit Memory Cell DRAM Technology Characteristics Since 1975, the main memory is composed of semiconductor • In SRAM technology, a three-state D-latch is the DRAM’s (Dynamic Random Access Memory). basic building block, i.e. basic memory cell. DRAM chip capacity had been growing at rate of about 4 times Internally, a D-latch can have a state corresponding every three years, while lately growth slowed down to 2 times to 0 or 1. every two years. • In DRAM technology, the basic memory cell is built Currently, maximum DRAM chip capacity is 512M bits with an access time in the range 40-60 nsec and a cycle time of about around one capacitor coupled with one transistor. 80 nsec. The value in the cell is stored as a charge. A Access time & cycle time are two measures of memory latency: charge can not be stored indefinitely and DRAM • access time – the time between a read is requested and when chips must be periodically refreshed. Since charges the desired content arrives, can be kept for several msec, 1-2% of time is used • cycle time – the minimum time between two memory requests. for refreshing. For DRAM technology cycle time is longer than access time. For SRAM technology access time and cycle time are identical. g. babic Presentation E 13 g. babic Presentation E 14 Growth of Capacity per DRAM chip Prices of Six Generations of DRAMs Figure 1.13 g. babic Presentation E 15 g. babic Presentation E 16 SRAM Technology Characteristics Memory Chip Functioning 15 • SRAM – Static Random Access Memory technology is Example: 32K×8 chip Address normally used for caches. • read and write Chipselect operations are 8 bits 8 • In comparable technologies, SRAM cycle time is about 8 to 16 RAM Read enable Dout[7–0] times faster than DRAM, e.g. currently 0.5-5 nsec. wide 32K × 8 • there are 32K • Since SRAM address lines are not multiplexed, there is no Write enable addressable locations 8 difference between access time and cycle time. D in[7– 0] • But, SRAM chip capacity (as well as density) is roughly 4 to 8 • Functioning of memory chip: times less than that of DRAM –CS (Chip select) has to be set for either reading or writing • Also SRAM is more expensive, e.g. 1GB in 2004 $4,000 – –R (Read enable)=0 & W (Write enable)=0 Æ chip is not being accessed – R=0 and W=1 Æ write values at Din lines into the chip address at $10,000 for SRAM and $100 – $200 for DRAM. Address lines • In addition, SRAM chips have higher power consumption and – R=1 and W=0 Æ read into Dout lines values from the chip address at power dissipation than DRAM chips. Address lines – R=1 and W=1 Æ not allowed • Thus SRAM designs are concerned with speed, while in DRAM Two designs of memory chip: – Basic structure design designs the emphasis is on cost per bit and capacity. – Typical organization design g. babic Presentation E 17 g. babic Presentation E 18 Basic Structure Design of 4×2 SRAM Chip Design of Memory Chip Basic Structure 2 Address • The design of the basic structure of SRAM chip uses some Chip select Chip Select SRAM 2 Output enable Dout[1– 0] 4 × 2 ideas from the register file design e.g. the write parts in two Din[1] Din[0] Write enable 2 designs are identical. The main differences are in read part Read Enable Din[1– 0] D D D D design. In the memory chip with the usage of three-state D- Writeenable C latch Q C latch Q Enable Enable latches a multiplexer is eliminated. E.g. for 32K*8 SRAM 0 chip, a multiplexer with 32K inputs each input having 8 lines 2-to-4 D D D D decoder would be needed. C latch Q C latch Q Enable Enable 1 • But for design of the basic structure of SRAM chip, we still need a very large decoder. E.g. for 32K*8 SRAM chip, a D D D D Address C latch Q C latch Q decoder with 15 input lines (that is not so bad) and 32K Enable Enable 2 output lines (that is bad) is required. Typical organization of SRAM uses two level decoding that eliminates need for that D D D D C latch Q C latch Q very large decoder. Enable Enable 3 Figure B.9.3 Dout[1] Dout[0] g. babic Presentation E 19 g. babic Presentation E 20 4×2 Array of D- Latches Typical Organization Design The next example will be using 512×64 array • Example: Design (read part only) a typical organization (i.e. two level Chip Select of D-latches. decoding design) of 32K×8 SRAM chip that uses 512*64 arrays of D- Din[1] Din[0] latches. Read Enable D D D D • Note: Arrays used have to have a bit capacity equal to a number of Writeenable C latch Q C latch Q addressable locations in the chip, e.g.
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