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Family of Solutions for HSPA Enterprise Femtocell Applications

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Family of Solutions for HSPA Enterprise Femtocell Applications New single-chip, multicore DSP solution for HSPA enterprise femtocell applications Product Bulletin Key features The TMS320TCI6489 from Texas Instruments is a high-performance, cost-competitive, TMS320TCI6489 high-performance DSP single-chip digital signal processor (DSP) solution. Targeted at the demanding enterprise • Three 850-MHz, TMS320C64x+™ cores femtocell market, the TCI6489 is capable of supporting PHY and MAC layer processing provide flexible processing for supporting different standards for 2G, 3G and 4G femtocell base stations, and offers substantial development Built-in UMTS receiver accelerator coprocessor (RAC) benefits for manufacturers. Optimized for wireless baseband applications with turbo and Viterbi The TCI6489 DSP includes three cores and In the office femtocell base stations enhance decoder coprocessors is capable of supporting 32 users on a single the wireless experience by bringing higher 1 MB of internal L2 memory per core WCDMA carrier. Designed to run both PHY data rates, better coverage and lower cost sGMII Gigabit Ethernet and higher layer processing, it is also capable plans to the user. A typical femtocell network Four antenna interface lanes supporting of supporting 32 users on a single WCDMA architecture is shown on next page. The either OBSAI or CPRI carrier. With a broad selection of available femtocell architecture allows a mobile phone DDR2 667 MHz McBSP – Two McBSP links, each at analog RF components, the TCI6489 user in enterprise to be connected to a femto 100 Mbps enterprise platform is ideally suited for base station. This femto base station uses McBSP can be used for multichannel any femtocell original equipment the existing landline connection (typically clocked serial communications manufacturer (OEM). DSL, cable or fiber) to connect to the wireless I2C – One I2C link at 400 kbps operator’s network. These femtocell base I2C can be used for communication TCI6489 WCDMA enterprise stations must coexist within the macro links between integrated circuits or femtocell system parameters base station area and must cope with the for peripheral devices on an embedded system • 32 UEs challenges of interference, power control • Ease of programming enables • HSDPA up to 15 Mbps and hand off with the macro network. TI offers a complete software solution for customization combined with fast time • HSUPA up to 5.7 Mbps to market the TCI6489 to reduce manufacturers’ time • Cell size < 200 m Allows system developers to make • L3/L2/L1 functionality to market and overall development costs, modifications if deployments encounter allowing them to respond quickly to these unexpected issues With TI’s TCI6489 femtocell base station challenges and provide the necessary features Speeds time to market for involvement solutions, OEMs can use a single device for and updates operators require. Because in trials and to obtain critical feedback PHY and full upper-layer processing without TI’s solutions are DSP-based and software on solutions incurring excessive research and development programmable, OEMs can future-proof their Leverages the most comprehensive set expenditures, as a separate RISC processor femtocell base station products, thereby of DSP development tools, including TI’s for Layer 2 and 3 processing is no longer appealing to wireless service providers who Code Composer Studio™ IDE and the required. can easily support new features with field DSP/BIOS™ software kernel foundation software upgrades. Key features continued Enterprise • Optimized software for WCDMA Optimized HSPA Layer 1, 2 and 3 software reference design Femto Carrier-class code development provides concentrator ease of use and smooth integration IpSec Tunnel Residential DSL, cable or fiber network Option A Option B RNC MSC Iub Iub IuCS IuCS ATM or IP PSTN Node B IuPS SGSN GGSN Gn GI IP backbone A typical femtocell network architecture The TCI6489 allows OEMs to address any per core on each device. To support wireless Another important feature of the TCI6489 is wireless standard from GSM to LTE. These applications, each DSP contains a number of support of standard interfaces such as Gigabit solutions are also code-compatible with other specialized coprocessors: Ethernet, DDR2 and McBSP. TI DSPs for the wireless infrastructure market, The TCI6489 supports four AIF lanes, each • Viterbi decoder coprocessor 2 (VCP2) reusing any previous investments in maco or configurable as either OBSAI or CPRI, with • Turbo decoder coprocessor 2 (TCP2) pico base stations. a maximum rate of 3.072 Gbps (OBSAI) and • Receiver accelerator coprocessor (RAC) 2.4576 Gbps (CPRI). These features simplify High-performance board-level design and further reduce The RAC subsystem is a chip-rate DSP architecture system cost. accelerator, used in the receiver side of The TCI6489 DSP is capable of supporting the base station and based on a generic physical layer functionality, including correlator coprocessor (GCCP) that supports symbol rate, chip rate and full MAC UMTS-specific operations. The RAC assists processing. Although femtocells are small in in transferring received antenna data to the size, they still require powerful performance, receive core, performing functions targeted for as requirements for HSPA femtocells are the WCDMA macro base station applications. same in terms of raw bandwidth as single These focused set of accelerators deliver sectors of macro base stations. While there the ideal features and performance for any are simplifications in the RF and in Layer 2 type of femto base station. The subsystem processing, the basic physical layer data includes two GCCP accelerators, used for ™ rate support is almost equivalent to a Three C64x+ cores (850 MHz) finger despread (FD), path search (PS), single-sector macro. 3 MB L2 (1 MB per core) preamble detection (PD) and stream power TI’s TCI6489 high-performance DSP has estimation (SPE). In addition, the RAC has a Four AIF lanes three independent TMS320C64x+™ DSP back-end interface (BEI) for managing RAC cores, at the heart of each subsystem. For configuration and data output. flexibility, there is 1 MB of L2 SRAM/cache Key benefits I2C GPIO • Low-cost, power-efficient baseband designs TMS320C64x+™ for enterprise femtocell base stations Core PLL Timers Single TCI6489 DSP baseband solution RSA Supports both PHY and MAC on each Boot ROM DSP core L1 D Memory Targeted UMTS receiver accelerator Others coprocessor (RAC) as well as VCP2/TCP2 L1 P Memory accelerators VCP2 • Flexible, software-programmable baseband solution Layers 1, 2 and 3 functionality for WCDMA L2 Memory TCP2 RAC and eventually LTE Capable of running Linux as necessary Field software upgrades enable emerging EDMA 3.0 with switch fabric applications on existing hardware platforms Single hardware platform supports a varied feature set depending on operator’s unique Giga Ethernet McBSP DDR2 Antenna IF FSync requirements Faster time to market OEMs can reuse their C64x+™ DSP TCI6489 block diagram based baseband application software The TCI6489 has three 850-MHz TMS320C64x+™ DSP cores. Each core includes 1-MB L2 memory. developed for today’s macro base stations Software compatibility with legacy C64x+DSP software shortens development Layer 1 and 2 processing WCDMA software time and allows reuse of existing software The TCI6489 is designed to completely handle reference design User-friendly Code Composer Studio™ the needs of Layer 1 and 2 processing on TI has partnered with third-party software integrated development environment a single DSP for an enterprise femtocell, suppliers mimoON and Continuous Computing available to reduce development time with two cores for PHY processing. With to provide customers with software for and cost 3 MB of internal L2 memory , the TCI6489 Layer 1, 2 and 3 wireless protocol processing is ideally proportioned between performance (control plane and user plane). This software and memory for femtocells. The TCI6489 is is 3GPP Release 6 compliant (Release 7 down-converters, high-speed data converters, also capable of running Linux for Layer 3 and 8 [LTE] to follow), as well as Femto Forum and RF products for radio front-end solutions. processing using VirtualLogix real-time API-compliant, while also including cognitive Other products include power management, virtualization software optimized for radio sniffers and advanced scheduling timing, backplane interface and standard logic wireless infrastructure applications. functions for optimal femtocell performance. components. TI has a complete end-to-end, The software is provided in a modular analog-to-digital hardware solution for all fem- Transmit chip-rate fashion for customization, feature tocell base station derivatives in all frequency accelerator using RSA differentiation, and a path for future ranges, bandwidths and capabilities. The DSP subsystem and its associated RSA standards upgrades or modifications. It also extensions implement transmit chip-rate supports the Linux operating system for For more information processing. The DSP core generates both portions of the control plane functionality www.ti.com/femtocell OVSF and PN codes and provides the and higher layers as required. multiplied result of these two codes as input to the RSA. The modulated user symbols are also Other TI components for provided as input to the RSA. The RSA applies femtocell base stations the code values to the modulated symbols to TI offers the industry’s broadest portfolio of achieve spreading and scrambling. It is also products for wireless infrastructures, including capable of carrying
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