Software and Hardware Supports for Multi-OS Environment

Total Page:16

File Type:pdf, Size:1020Kb

Software and Hardware Supports for Multi-OS Environment Software and Hardware Supports for Multi-OS Environment マルチ OS 環境を支援するソフトウェア およびハードウェア機能の提案 February 2012 Waseda University Graduate School of Fundamental Science and Engineering Major in Computer Science and Engineering Research on Distributed Systems Yuki KINEBUCHI 2 c Copyright by Yuki Kinebuchi 2012 All rights reserved 2 Acknowledgements This is a great opportunity to express my respect to my thesis advisor, Prof. Tatsuo Nakajima. My research and this dissertation would not exist without his support and patience. I would also like to thank all the members at Distributed Computing Laboratory in Waseda University for encouraging me. 3 4 Abstract Personal mobile devices are rapidly enhancing their functionalities. Not limited to phone and text messages, they offer web browsing via the Internet, free to install applications on the users’ requests, play musics and videos, etc. Now they are capable of running multiple OS instances with support of virtualization. Like the use in desktop/enterprise systems, virtualization for embedded mobile devices allows consolidating multiple OS instances and enhancing the security of hosted OS environment. In addition, there are applications specific to embedded systems such as hosting real-time OS (RTOS) and application OS (GPOS) concurrently without spoiling the real-time responsiveness of the RTOS. There is no doubt that virtualization brings many benefits to the embedded mobile devices, however virtualization is not a panacea. Additional layer of virtualization incurs additional complexity to the software stack of devices. Some extra engineering efforts of developing such device might make the system prone to bugs and security risks. In this dissertation we take the position that some applications of embedded virtualization can be supported with more light-weight methods. The methods leverages architecture specific features that are common or expected to be common among embedded mobile devices. We first focus on real-time and application OS consolidation, for which we propose a thin abstraction layer that achieves better interrupt responsiveness than virtualization. Next we focus on hosting a kernel integrity monitor for rootkit detection. The monitor is hosted within an isolated memory region that is protected by means of processor architecture. 5 6 Contents 1 Introduction 1 1.1 Motivation . 1 1.2 Contributions................................... 2 1.3 Organization of the Dissertation . 2 2 Discussions on Embedded System Virtualization 5 2.1 The Use of Embedded System Virtualization . 5 2.2 Performance and Real-time Responsiveness . 6 2.3 EngineeringCost ................................. 7 2.4 Security ...................................... 8 3 Microkernel-based Multi-OS Architecture 11 3.1 Background . 11 3.2 Implementation.................................. 13 3.2.1 L4-embedded . 14 3.2.2 Wombat . 15 3.2.3 L4/TOPPERS . 16 3.3 TaskGrainScheduling.............................. 17 3.3.1 Full- and Para-virtualization . 17 3.3.2 Scheduling Algorithm . 18 3.3.3 Global Priority . 18 3.3.4 Global Scheduler . 19 3.3.5 Task Grained Scheduling in L4-embedded . 19 3.3.6 Task Grained Scheduling in Wombat . 20 3.3.7 Task Grained Scheduling in L4/TOPPERS . 20 3.4 Evaluation . 21 3.4.1 Context Switch Overhead . 22 3.4.2 InterruptDelayOverhead . 22 3.4.3 Task Grain Scheduling . 24 3.4.4 InterruptDelayJitters. 26 3.5 RelatedWork................................... 27 7 3.5.1 Improving OS Real-time Performance . 27 3.5.2 Hybrid Architecture . 28 3.5.3 Hypervisor-based Systems . 28 3.6 Summary ..................................... 29 4 Software-based Processor Core Multiplexing 31 4.1 Background . 31 4.2 Design and Implementation . 33 4.2.1 SPUMONE . 33 4.2.2 ModifyingOSKernels .......................... 35 4.3 InterruptDelayReduction. 37 4.3.1 Interrupt Priority Level Assignment . 37 4.3.2 Virtual Processor Core Migration . 38 4.4 Evaluation . 39 4.4.1 Basic Overhead . 39 4.4.2 Engineering Cost . 40 4.4.3 The Effect of Linux Load to TOPPERS Real-time Responsiveness . 41 4.4.4 The Effect of TOPPERS Periodic Task Load to Linux Throughput . 47 4.5 RelatedWork................................... 47 4.6 Summary ..................................... 50 5 Core-local Memory Assisted Protection 51 5.1 Background . 51 5.2 The LLM Architecture . 52 5.3 TheSecurePaging ................................ 54 5.3.1 Threat Detections . 61 5.4 Implementation.................................. 62 5.5 Evaluations . 63 5.5.1 Case study . 64 5.5.2 Performance . 66 5.5.3 Engineering Cost . 67 5.6 RelatedWork................................... 68 5.7 Summary ..................................... 69 6 Conclusion 71 8 List of Figures 1.1 Organization of the Dissertation . 3 3.1 Task grain scheduling . 13 3.2 Wombat . 15 3.3 L4/TOPPERS . 16 3.4 Mapping the local priorities to the global priority . 18 3.5 Globalscheduler ................................. 19 3.6 Serialinterruptdelays .............................. 22 3.7 Directandindirectinterruptdelays. 23 3.8 Dummy tasks without and with task grain scheduling . 25 3.9 Testing task grain scheduling . 26 3.10 The intervals of TOPPERS’s 2ms periodic task. 27 4.1 SPUMONE based system on a single-core processor . 33 4.2 SPUMONE based system on a multi-core processor . 33 4.3 InterruptDeliveryMechanism. 38 4.4 Theinterruptprioritylevelsassignment . 38 4.5 Virtual core migration . 39 4.6 The dispatch delay of 1ms periodic task on native TOPPERS) . 42 4.7 Dispatch delay (CPU stress on Linux without IPL modification) . 43 4.8 Dispatch delay (CPU stress on Linux with IPL modification) . 43 4.9 Dispatch delay (CF read/write stress on Linux without IPL modification) 44 4.10 Dispatch delay (CF read/write stress on Linux with IPL modification) . 44 4.11 Dispatch delay (NFS r/w stress on Linux without virt. core migration) . 45 4.12 Dispatch delay (NFS r/w stress on Linux with virt. core migration) . 45 4.13 Dispatch delay on SMP (frequent IPC on Linux without virt. core migration) 46 4.14 Dispatch delay on SMP (frequent IPC on Linux with virt. core migration) . 46 4.15 The effect of load on TOPPERS to Linux’s DMIPS score (y-axis in DMIPS, largerisbetter).................................. 48 4.16 The effect of load on TOPPERS to Linux’s hackbench (y-axis in seconds, smallerisbetter) ................................. 48 9 5.1 Loading the pager, the monitor and the target OS. 55 5.2 The pager calculates the hash value of each page. The target OS is not activated at this point. 56 5.3 Execute the entry of the monitor and trap into the pager. 57 5.4 The pager swaps in a page while calculating its hash value, and checks if thepageisaltered................................. 58 5.5 The pagers maps the checked page into the address space. 59 5.6 The pager tries to evict a page contained in the local memory to the main memory....................................... 60 5.7 The pager detects a data page that is tampered by a malicious application runningonthetargetOS. ............................ 61 5.8 The memory layout of the pseudo LLM architecture. 64 5.9 The result of Unixbench on Linux with 3 cores running beside the monitor and the secure pager. Normalized to the score of native Linux with 3 cores. 66 5.10 The result of Unixbench on Linux with 3 cores running beside the monitor and the secure pager. Normalized to the score of native Linux with 4 cores. 67 10 List of Tables 3.1 Evaluation settings . 21 3.2 Average interrupt delay: in microseconds (cycles) . 23 3.3 Worst interrupt delay: in microseconds (cycles) . 23 3.4 Average indirect timer interrupt delay: in microseconds . 24 3.5 Dummytasks................................... 25 4.1 A list of the modifications to the Linux kernel . 37 4.2 The delay of handling the timer interrupts in TOPPERS. 40 4.3 Linuxkernelbuildtime ............................. 40 4.4 The total number of modified LoC in *.c, *.S, *.h, Makefiles . 41 5.1 Lines of code modified in xv6 (rev4) to create the monitor OS. 67 5.2 Lines of code modified in Linux to run on the LLM architecture. 68 11 12 Chapter 1 Introduction Personal mobile devices are rapidly enhancing their functionalities. Not limited to phone and text messages, they offer web browsing via the Internet, free to install applications on the users’ requests, play musics and videos, etc. At this point writing this thesis the latest device is equipped with multiple processor cores run with over 1.4GHz frequency and a gigabyte of memory [6]. This outstrips the performance of desktop computers those were available in 1990s. As their hardware advances, now they are capable of running multiple OS instances with support of virtualization [9, 17, 32]. Like the use in desktop/enterprise systems, virtualization for embedded mobile devices allows consolidating multiple OS instances and enhancing the security of hosted OS environment. In addition, there are applications specific to embedded systems such as hosting real-time OS (RTOS) and application OS (GPOS) concurrently without spoiling the real-time responsiveness of the RTOS. These benefits of virtualization motivated the ARM architecture to add a hardware virtualization support to their upcoming instruction set architecture (ISA) [62]. 1.1 Motivation There is no doubt that virtualization brings many benefits to the embedded mobile de- vices, however virtualization is not a panacea. Additional layer of virtualization incurs additional complexity to the software stack of devices. The hypervisor should be designed carefully to achieve reasonable performance. The straightforward port of an existing hy- pervisor from the desktop/enterprise field to embedded field does not perform well [34]. Extra engineering efforts of developing such device might make the system prone to bugs and security risks. In Chapter 2, we discuss the advantages and disadvantage of using hypervisors for embedded systems to accomodate multiple OS kernels in detail. In this dissertation we take the position that some applications of embedded vir- tualization can be supported with more light-weight methods. The hybrid architecture [24, 66, 44, 59] and the logical partitioning of OS kernels [54] suggest the feasibility of 1 running multiple-OS system without support of hypervisors.
Recommended publications
  • UG1046 Ultrafast Embedded Design Methodology Guide
    UltraFast Embedded Design Methodology Guide UG1046 (v2.3) April 20, 2018 Revision History The following table shows the revision history for this document. Date Version Revision 04/20/2018 2.3 • Added a note in the Overview section of Chapter 5. • Replaced BFM terminology with VIP across the user guide. 07/27/2017 2.2 • Vivado IDE updates and minor editorial changes. 04/22/2015 2.1 • Added Embedded Design Methodology Checklist. • Added Accessing Documentation and Training. 03/26/2015 2.0 • Added SDSoC Environment. • Added Related Design Hubs. 10/20/2014 1.1 • Removed outdated information. •In System Level Considerations, added information to the following sections: ° Performance ° Clocking and Reset 10/08/2014 1.0 Initial Release of document. UltraFast Embedded Design Methodology Guide Send Feedback 2 UG1046 (v2.3) April 20, 2018 www.xilinx.com Table of Contents Chapter 1: Introduction Embedded Design Methodology Checklist. 9 Accessing Documentation and Training . 10 Chapter 2: System Level Considerations Performance. 13 Power Consumption . 18 Clocking and Reset. 36 Interrupts . 41 Embedded Device Security . 45 Profiling and Partitioning . 51 Chapter 3: Hardware Design Considerations Configuration and Boot Devices . 63 Memory Interfaces . 69 Peripherals . 76 Designing IP Blocks . 94 Hardware Performance Considerations . 102 Dataflow . 108 PL Clocking Methodology . 112 ACP and Cache Coherency. 116 PL High-Performance Port Access. 120 System Management Hardware Assistance. 124 Managing Hardware Reconfiguration . 127 GPs and Direct PL Access from APU . 133 Chapter 4: Software Design Considerations Processor Configuration . 137 OS and RTOS Choices . 142 Libraries and Middleware . 152 Boot Loaders . 156 Software Development Tools . 162 UltraFast Embedded Design Methodology GuideSend Feedback 3 UG1046 (v2.3) April 20, 2018 www.xilinx.com Chapter 5: Hardware Design Flow Overview .
    [Show full text]
  • The OKL4 Microvisor: Convergence Point of Microkernels and Hypervisors
    The OKL4 Microvisor: Convergence Point of Microkernels and Hypervisors Gernot Heiser, Ben Leslie Open Kernel Labs and NICTA and UNSW Sydney, Australia ok-labs.com ©2010 Open Kernel Labs and NICTA. All rights reserved. Microkernels vs Hypervisors > Hypervisors = “microkernels done right?” [Hand et al, HotOS ‘05] • Talks about “liability inversion”, “IPC irrelevance” … > What’s the difference anyway? ok-labs.com ©2010 Open Kernel Labs and NICTA. All rights reserved. 2 What are Hypervisors? > Hypervisor = “virtual machine monitor” • Designed to multiplex multiple virtual machines on single physical machine VM1 VM2 Apps Apps AppsApps AppsApps OS OS Hypervisor > Invented in ‘60s to time-share with single-user OSes > Re-discovered in ‘00s to work around broken OS resource management ok-labs.com ©2010 Open Kernel Labs and NICTA. All rights reserved. 3 What are Microkernels? > Designed to minimise kernel code • Remove policy, services, retain mechanisms • Run OS services in user-mode • Software-engineering and dependability reasons • L4: ≈ 10 kLOC, Xen ≈ 100 kLOC, Linux: ≈ 10,000 kLOC ServersServers ServersServers Apps Servers Device AppsApps Drivers Microkernel > IPC performance critical (highly optimised) • Achieved by API simplicity, cache-friendly implementation > Invented 1970 [Brinch Hansen], popularised late ‘80s (Mach, Chorus) ok-labs.com ©2010 Open Kernel Labs and NICTA. All rights reserved. 4 What’s the Difference? > Both contain all code executing at highest privilege level • Although hypervisor may contain user-mode code as well > Both need to abstract hardware resources • Hypervisor: abstraction closely models hardware • Microkernel: abstraction designed to support wide range of systems > What must be abstracted? • Memory • CPU • I/O • Communication ok-labs.com ©2010 Open Kernel Labs and NICTA.
    [Show full text]
  • Carrier Grade Virtualization
    Carrier Grade Virtualization Leveraging virtualization in Carrier Grade Systems Abstract Network Equipment Providers (NEPs) have been building networking infrastructure equipment able to deliver “carrier grade” services, typically mission-critical services such as voice telephony. In decades past, NEPs have achieved high degrees of availability through purpose-built hardware and software implementations. Today they increasingly build on COTS (Commercial Off The Shelf) hardware and Open Source Software (OSS), freeing their engineering resources to focus on core telephony competencies. The move to COTS and OSS requires that these hardware and software components be available from an ecosystem of suppliers, and that they interoperate seamlessly. Bodies such as The Linux Foundation (LF), the Service Availability Forum (SA Forum) and PICMG have defined standards and specifications such as carrier grade OSes (CGLinux), Service Availability Forum APIs and AdvancedTCA hardware to target carrier grade applications. Recent advances have made virtualization appealing for carrier class equipment by permitting significant cost reduction through consolidation of workloads and of physical hardware. Virtualization also transparently lets NEPs and other OEMs (Original Equipment Manufacturers) leverage multi-core processors to run legacy software designed for uniprocessor hardware. However, virtualization needs to meet specific requirements to enable network equipment deploying this technology to meet industry expectations for carrier grade systems. This
    [Show full text]
  • Sel4: Formal Verification of an Operating-System Kernel
    seL4: Formal Verification of an Operating-System Kernel Gerwin Klein1;2, June Andronick1;2, Kevin Elphinstone1;2, Gernot Heiser1;2;3 1 1 1;2 1;2 David Cock , Philip Derrin ∗, Dhammika Elkaduwe ,z Kai Engelhardt 1;2 1;4 1 1;2 1;2 Rafal Kolanski , Michael Norrish , Thomas Sewell , Harvey Tuch y, Simon Winwood 1 NICTA, 2 UNSW, 3 Open Kernel Labs, 4 ANU [email protected] ABSTRACT We report on the formal, machine-checked verification of the seL4 microkernel from an abstract specification down to its C implementation. We assume correctness of compiler, assembly code, hardware, and boot code. seL4 is a third-generation microkernel of L4 provenance, comprising 8,700 lines of C and 600 lines of assembler. Its performance is comparable to other high-performance L4 kernels. We prove that the implementation always strictly follows our high-level abstract specification of kernel behaviour. This encompasses traditional design and implementation safety properties such as that the kernel will never crash, and it will never perform an unsafe operation. It also implies much more: we can predict precisely how the kernel will behave in every possible situation. 1. INTRODUCTION Almost every paper on formal verification starts with the observation that software complexity is increasing, that this Figure 1: Call graph of the seL4 microkernel. Ver- leads to errors, and that this is a problem for mission and tices represent functions, and edges invocations. safety critical software. We agree, as do most. Here, we report on the full formal verification of a critical system from a high-level model down to very low-level C kernel, and every single bug can potentially cause arbitrary code.
    [Show full text]
  • Operating System Support for Run-Time Security with a Trusted Execution Environment
    Operating System Support for Run-Time Security with a Trusted Execution Environment - Usage Control and Trusted Storage for Linux-based Systems - by Javier Gonz´alez Ph.D Thesis IT University of Copenhagen Advisor: Philippe Bonnet Submitted: January 31, 2015 Last Revision: May 30, 2015 ITU DS-nummer: D-2015-107 ISSN: 1602-3536 ISBN: 978-87-7949-302-5 1 Contents Preface8 1 Introduction 10 1.1 Context....................................... 10 1.2 Problem....................................... 12 1.3 Approach...................................... 14 1.4 Contribution.................................... 15 1.5 Thesis Structure.................................. 16 I State of the Art 18 2 Trusted Execution Environments 20 2.1 Smart Cards.................................... 21 2.1.1 Secure Element............................... 23 2.2 Trusted Platform Module (TPM)......................... 23 2.3 Intel Security Extensions.............................. 26 2.3.1 Intel TXT.................................. 26 2.3.2 Intel SGX.................................. 27 2.4 ARM TrustZone.................................. 29 2.5 Other Techniques.................................. 32 2.5.1 Hardware Replication........................... 32 2.5.2 Hardware Virtualization.......................... 33 2.5.3 Only Software............................... 33 2.6 Discussion...................................... 33 3 Run-Time Security 36 3.1 Access and Usage Control............................. 36 3.2 Data Protection................................... 39 3.3 Reference
    [Show full text]
  • Comparison of Platform Virtual Machines - Wikipedia
    Comparison of platform virtual machines - Wikipedia... http://en.wikipedia.org/wiki/Comparison_of_platform... Comparison of platform virtual machines From Wikipedia, the free encyclopedia The table below compares basic information about platform virtual machine (VM) packages. Contents 1 General Information 2 More details 3 Features 4 Other emulators 5 See also 6 References 7 External links General Information Name Creator Host CPU Guest CPU Bochs Kevin Lawton any x86, AMD64 CHARON-AXP Stromasys x86 (64 bit) DEC Alphaserver CHARON-VAX Stromasys x86, IA-64 VAX x86, x86-64, SPARC (portable: Contai ners (al so 'Zones') Sun Microsystems (Same as host) not tied to hardware) Dan Aloni helped by other Cooperati ve Li nux x86[1] (Same as parent) developers (1) Denal i University of Washington x86 x86 Peter Veenstra and Sjoerd with DOSBox any x86 community help DOSEMU Community Project x86, AMD64 x86 1 of 15 10/26/2009 12:50 PM Comparison of platform virtual machines - Wikipedia... http://en.wikipedia.org/wiki/Comparison_of_platform... FreeVPS PSoft (http://www.FreeVPS.com) x86, AMD64 compatible ARM, MIPS, M88K GXemul Anders Gavare any PowerPC, SuperH Written by Roger Bowler, Hercul es currently maintained by Jay any z/Architecture Maynard x64 + hardware-assisted Hyper-V Microsoft virtualization (Intel VT or x64,x86 AMD-V) OR1K, MIPS32, ARC600/ARC700, A (can use all OVP OVP Imperas [1] [2] Imperas OVP Tool s x86 (http://www.imperas.com) (http://www.ovpworld compliant models, u can write own to pu OVP APIs) i Core Vi rtual Accounts iCore Software
    [Show full text]
  • Partitioned System with Xtratum on Powerpc
    Tesina de M´asteren Autom´aticae Inform´aticaIndustrial Partitioned System with XtratuM on PowerPC Author: Rui Zhou Advisor: Prof. Alfons Crespo i Lorente December 2009 Contents 1. Introduction1 1.1. MILS......................................2 1.2. ARINC 653..................................3 1.3. PikeOS.....................................6 1.4. ADEOS....................................7 2. Overview of XtratuM 11 2.1. Virtualization and Hypervisor........................ 11 2.2. XtratuM.................................... 12 3. Overview of PowerPC 16 3.1. POWER.................................... 16 3.2. PowerPC.................................... 17 3.3. PowerPC in Safety-critical.......................... 19 4. Main PowerPC Drivers to Virtualize 20 4.1. Processors................................... 20 4.2. Timer..................................... 21 4.3. Interrupt.................................... 23 4.4. Memory.................................... 24 5. Porting Implementation 25 5.1. Hypercall................................... 26 5.2. Timer..................................... 27 5.3. Interrupt.................................... 28 5.4. Memory.................................... 31 5.5. Partition.................................... 32 6. Benchmark 34 7. Conclusions and Future Work 38 Abstract Nowadays, the diversity of embedded applications has been developed into a new stage with the availability of various new high-performance processors and low cost on-chip memory. As the result of these new advances in hardware, there is a
    [Show full text]
  • Operating System Verification—An Overview
    Sadhan¯ a¯ Vol. 34, Part 1, February 2009, pp. 27–69. © Printed in India Operating system verification—An overview GERWIN KLEIN Sydney Research Laboratory, NICTA,∗ Australia, School of Computer Science and Engineering, University of New South Wales, Sydney, Australia e-mail: [email protected] Abstract. This paper gives a high-level introduction to the topic of formal, interactive, machine-checked software verification in general, and the verification of operating systems code in particular. We survey the state of the art, the advantages and limitations of machine-checked code proofs, and describe two specific ongoing larger-scale verification projects in more detail. Keywords. Formal software verification; operating systems; theorem proving. 1. Introduction The fastest, cheapest and easiest way to build something is properly the first time (Parker 2007). This engineer’s credo has made it into popular literature, but it seems to be largely ignored in the world of software development. In the late 1960s a software crisis was diagnosed on a summit in the Bavarian Alps (Naur & Randell 1969): Software was getting more and more complex, and we had no structured way of building it. We ended up with projects that took significantly longer than planned, were more expensive than planned, delivered results that did not fully address customer needs, or at worst were useless. This summit in the late 1960s is widely seen as the birth of the discipline of software engineering. Now, almost 40 years later, we have come a long way. There are numerous books on software engineering, a plenitude of methodologies, programming languages, and processes to choose from.
    [Show full text]
  • A Practical Look at Micro-Kernels and Virtual Machine Monitors
    A Practical Look at Micro-Kernels and Virtual Machine Monitors François Armand, Michel Gien, Member, IEEE of the main drivers is the need to run new or feature-rich open Abstract — In this paper, we look at two different approaches system software while maintaining existing legacy software used to provide embedded system support for virtualization and that has been already tested and validated in their own virtual machine monitors for consumer electronics and mobile operating environment. Such open software commonly devices. We compare the micro-kernel approach, which has been includes Linux and more established operating systems such a popular choice for building embedded operating systems with the Virtual Machine Monitor (VMM) or hypervisor approach as Windows or Symbian where developers want to run the widely deployed in general purpose computing environments operating system unchanged while also extending their device such as desktops and data center servers. Comparison criteria security and manageability at all levels. are based on virtualization use cases that are typical of Consumer Co-existence of several operating environments on the same Electronics (CE) systems such as mobile devices and IPTV. These hardware platform is one of the main purposes of hardware approaches are further evaluated based on performance and on virtualization software, made possible by the provision of a their ability to allow re-use of existing (often real-time) software as well as modern open operating systems such as Linux while virtual image of the hardware to each operating system, which remaining as transparently as possible. Such transparency can believes it is running alone on the underlying hardware.
    [Show full text]
  • OKL4 Microkernel Reference Manual
    OKL4 Microkernel Reference Manual API Version 0316 Document Number: OK 10000:2006 (revision 12) Software Version: 3.0 Date: September 11, 2008 Copyright 2006–2008 Open Kernel Labs, Inc. Copyright 2006 National ICT Australia Limited This publication is distributed by Open Kernel Labs Pty Ltd, Australia. THIS DOCUMENT IS PROVIDED “AS IS” WITHOUT ANY WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFIRNGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copyright is by permission of the authors. To copy otherwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission and/or a fee. Authors: Open Kernel Labs Contact Details: Open Kernel Labs Pty Ltd Attention: Open Kernel Labs Suite 3, 540 Botany Road Alexandria, NSW 2015 Australia email: [email protected] web: http://www.ok-labs.com/ 3 Contents Preface 15 1 Introduction 17 1.1 Outline of This Manual 18 1.2 Definitions 18 1.3 Notation 19 1.4 Credits 20 PART A—GENERIC INTERFACE A-1 Overview 23 A-1.1 The OKL4 Programming Environment 23 A-1.2 OKL4 API Elements 24 A-1.3 Compatibility between OKL4 Versions 24 A-1.4 Variants of the OKL4 API 25 A-1.5 Microkernel Extensions and
    [Show full text]
  • Family of Solutions for HSPA Enterprise Femtocell Applications
    New single-chip, multicore DSP solution for HSPA enterprise femtocell applications Product Bulletin Key features The TMS320TCI6489 from Texas Instruments is a high-performance, cost-competitive, TMS320TCI6489 high-performance DSP single-chip digital signal processor (DSP) solution. Targeted at the demanding enterprise • Three 850-MHz, TMS320C64x+™ cores femtocell market, the TCI6489 is capable of supporting PHY and MAC layer processing provide flexible processing for supporting different standards for 2G, 3G and 4G femtocell base stations, and offers substantial development Built-in UMTS receiver accelerator coprocessor (RAC) benefits for manufacturers. Optimized for wireless baseband applications with turbo and Viterbi The TCI6489 DSP includes three cores and In the office femtocell base stations enhance decoder coprocessors is capable of supporting 32 users on a single the wireless experience by bringing higher 1 MB of internal L2 memory per core WCDMA carrier. Designed to run both PHY data rates, better coverage and lower cost sGMII Gigabit Ethernet and higher layer processing, it is also capable plans to the user. A typical femtocell network Four antenna interface lanes supporting of supporting 32 users on a single WCDMA architecture is shown on next page. The either OBSAI or CPRI carrier. With a broad selection of available femtocell architecture allows a mobile phone DDR2 667 MHz McBSP – Two McBSP links, each at analog RF components, the TCI6489 user in enterprise to be connected to a femto 100 Mbps enterprise platform is ideally suited for base station. This femto base station uses McBSP can be used for multichannel any femtocell original equipment the existing landline connection (typically clocked serial communications manufacturer (OEM).
    [Show full text]
  • Lltzvisor: a Lightweight Trustzone-Assisted Hypervisor for Low-End ARM Devices
    Hugo Miguel Eira Araújo lLTZVisor: A Lightweight TrustZone-assisted Hypervisor for low-end ARM Devices Outubro de 2018 Hugo Miguel Eira Araújo lLTZVisor: A Lightweight TrustZone-assisted Hypervisor for low-end ARM devices Dissertação de Mestrado em Engenharia Eletrónica Industrial e Computadores Trabalho efetuado sob a orientação do Doutor Sandro Pinto Outubro de 2018 Declaração do Autor Nome: Hugo Miguel Eira Araújo Correio Eletrónico: [email protected] Cartão de Cidadão: 14887613 Titulo da dissertação: lLTZVisor: A Lightweight TrustZone-assisted Hyper- visor for low-end ARM Devices Ano de conclusão: 2018 Orientador: Doutor Sandro Pinto Designação do Mestrado: Ciclo de Estudos Integrados Conducentes ao Grau de Mestre em Engenharia Eletrónica Industrial e Computadores Área de Especialização: Sistemas Embebidos e Computadores Escola de Engenharia Departamento de Eletrónica Industrial De acordo com a legislação em vigor, não é permitida a reprodução de qualquer parte desta dissertação. Universidade do Minho, 29/10/2018 Assinatura: Hugo Miguel Eira Araújo v Acknowledgements The accomplishment of this master’s thesis involved great contributions from sev- eral people, whom I will be eternally grateful. Foremost, I would like to express my gratitude to my advisor Dr. Sandro Pinto for giving me the opportunity to develop this groundbreaking work and for all the guidance and continuous support throughout this great journey. Thank you for all the confidence placed on me, and especially, for all the motivation and advices given during difficult times. I would like to also thank Dr. Adriano Tavares, my professor, whom I appreciate all the given advices and reviews. And of course, thanks for all the music tips that helped me to increase productivity.
    [Show full text]