Performance Analysis of Adiabatic Logic Gate Circuits Using 4T Dram Cells

PERFORMANCE ANALYSIS OF ADIABATIC LOGIC GATE CIRCUITS USING 4T DRAM CELLS

ANUPRIYA KRISHNAMOORTHY

A THESIS

Submitted in partial fulfillment of the requirements for the degree of

Master of Science in Engineering

The Department of Electrical and Computer Engineering

The School of Graduate Studies

The University of Alabama in Huntsville

HUNTSVILLE, ALABAMA

2016

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ACKNOWLEDGEMENTS

This thesis could not be completed without the assistance of several people who deserve special mention. First, I would like to thank Dr. Fat Duen Ho for his guidance throughout all the stages of the work. Second the members of my committee, Dr. David Wendi Pan and Dr. Jia Li, who have been helpful with comments and suggestions.

I would like to thank my family especially my parents Krishnamoorthy Vanchinathan(Father), Umamaheswari Jagadeesan (Mother) and my elder sibling Abinaya Krishnamoorthy (Sister) and my friend Ashish Ramesh, for tolerating me through the whole process.

TABLE OF CONTENTS

Page

List of Figures ...... viii

List of Symbols ...... xi

1. INTRODUCTION AND BACKGROUND 1.1 Overview ...... 1 1.2 Tank Oscillator Operation ...... 6

2. LITERATURE REVIEW ...... 8 2.1 Static Random Access Memory ...... 10 2.2 1T1C DRAM Cell ...... 12 2.3 4T DRAM Cell ...... 13 2.4 3T DRAM Cell ...... 14

2.5 3T1D DRAM Cell ...... 16

3. RESEARCH STATEMENT ...... 18

4. ADIABATIC GATES AND POWER CONSUMPTION ...... 19

4.1 Adiabatic Cells ...... 19 4.1.1 Gates using LTSpice ...... 20

4.1.1.1 Not Adiabatic Cell ...... 20

4.1.1.2 NOR-OR Adiabatic Cell ...... 23

4.1.1.3 NAND-AND Adiabatic Cell ...... 25

4.1.1.4 XNOR-XOR Adiabatic Cell ...... 27

4.2 Gates using PSPICE ...... 29

4.2.1. Not Adiabatic Cell ...... 29

4.2.2 NOR-OR Adiabatic Cell ...... 31

4.2.3 NAND-AND Adiabatic Cell ...... 33

4.2.4 XNOR-XOR Adiabatic Cell ...... 36 4.3 Gate Power Consumption ...... 38

4.4 Power Clock Power Consumption...... 44

5.ADIABATIC GATES (L=45NM & L=22NM )

5.1 Adiabatic Cells (L=45nm) ...... 49

5.1.1 Not- Adiabatic Cell ...... 50

5.1.2 NOR-OR Adiabatic Cell ...... 52

5.1.3 NAND-AND Adiabatic Cell ...... 55

5.1.4 XNOR-XOR Adiabatic Cell ...... 57

5.2 Adiabatic Cells (L=22nm) ...... 59

5.2.1 Not- Adiabatic Cell ...... 60

5.2.2 NOR-OR Adiabatic Cell ...... 62

5.2.3 NAND-AND Adiabatic Cell ...... 65

5.2.4 XNOR-XOR Adiabatic Cell ...... 67

5.3 Power Clock-Power Consumption ...... 69

6. POWER CLOCK FOR SMALLER TRANSISTORS ...... 74

6.1 Input Power clock for Smaller Transistors ...... 74 6.2 High Speed Comparator for Smaller Transistors ...... 76

7. CONCLUSIONS ...... 78

7.1 Suggestions for further research ...... 79

APPENDIX A: 180nm Transistor models LT Spice ...... 80

APPENDIX B: 45nm Transistor models LT Spice ...... 83

vii

APPENDIX C: 22nm Transistor models LT Spice ...... 88

APPENDIX D: Transistor Models PSPICE ...... 93

APPENDIX E: BSIM4v4.7 MOSFET Model ...... 94

REFERENCES ...... 106

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LIST OF FIGURES

Figure Page

1.1 CMOS vs ADIABATIC MODEL ...... 3 1.2 Adiabatic RC Model ...... 4

1.3 Tank Oscillator ...... 6 2.1 Schematic 6T SRAM ...... 11 2.2 Schematic 1T1C DRAM Cell ...... 13 2.3 4T DRAM Cell ...... 14 2.4 3T DRAM Cell ...... 16 2.5 3T1D DRAM Cell ...... 17 4.1 Not Adiabatic Cell(L=180nm) ...... 21 4.2 Not Input (L=180nm) ...... 22 4.3 Not Output (L=180nm)...... 22 4.4 NOR-OR Adiabatic Cell (L=180nm) ...... 23 4.5 NOR-OR Inputs(L=180nm) ...... 24 4.6 NOR-OR Output(L=180nm) ...... 24 4.7 NAND-AND Adiabatic Cell (L=180nm) ...... 25 4.8 NAND-AND Inputs(L=180nm) ...... 26 4.9 NAND-AND Output(L=180nm) ...... 26 4.10 XNOR-XOR Adiabatic Cell (L=180nm) ...... 27 4.11 XNOR-XOR Inputs(L=180nm) ...... 28 4.12 XNOR-XOR Output(L=180nm) ...... 29 4.13 Not Adiabatic Cell PSPICE(L=180nm) ...... 30 4.14 Not Input (L=180nm) ...... 31 4.15 Not Output (L=180nm)...... 31 4.16 NOR-OR Adiabatic Cell PSPICE(L=180nm) ...... 32 4.17 NOR-OR Inputs(L=180nm) ...... 33 4.18 NOR-OR Output(L=180nm) ...... 33 4.19 NAND-AND Adiabatic Cell PSPICE(L=180nm) ...... 34 4.20 NAND-AND Inputs(L=180nm) ...... 35 4.21 NAND-AND Output(L=180nm) ...... 35 4.22 XNOR-XOR Adiabatic Cell PSPICE(L=180nm) ...... 36 4.23 XNOR-XOR Inputs(L=180nm) ...... 37

4.24 XNOR-XOR Output(L=180nm) ...... 37 4.25 Power Consumption Circuit ...... 39 4.26 Voltage (Vc) ...... 41 4.27 Voltages of Primitive Gate ...... 42 4.28 Power Clock Transistor Power Consumption Circuit ...... 45 4.29 Power Clock Transistor Driving signals...... 45 4.30 Resistor Power Calculation Circuit ...... 48 5.1 Not Adiabatic Cell(L=45nm) ...... 50 5.2 Not Input (L=45nm) ...... 51 5.3 Not Output (L=45nm)...... 52 5.4 NOR-OR Adiabatic Cell (L=45nm) ...... 53 5.5 NOR-OR Inputs(L=45nm) ...... 54 5.6 NOR-OR Output(L=45nm) ...... 54 5.7 NAND-AND Adiabatic Cell (L=45nm) ...... 55 5.8 NAND-AND Inputs(L=45nm) ...... 56 5.9 NAND-AND Output(L=45nm) ...... 56 5.10 XNOR-XOR Adiabatic Cell (L=45nm) ...... 57 5.11 XNOR-XOR Inputs(L=45nm) ...... 58 5.12 XNOR-XOR Output(L=45nm) ...... 59 5.13 Not Adiabatic Cell(L=22nm) ...... 60 5.14 Not Input (L=22nm) ...... 61 5.15 Not Output (L=22nm)...... 62 5.16 NOR-OR Adiabatic Cell (L=22nm) ...... 63 5.17 NOR-OR Inputs(L=22nm) ...... 64 5.18 NOR-OR Output(L=22nm) ...... 64 5.19 NAND-AND Adiabatic Cell (L=22nm) ...... 65 5.20 NAND-AND Inputs(L=22nm) ...... 66 5.21 NAND-AND Output(L=22nm) ...... 66 5.22 XNOR-XOR Adiabatic Cell (L=22nm) ...... 67 5.23 XNOR-XOR Inputs(L=22nm) ...... 68 5.24 XNOR-XOR Output(L=22nm) ...... 68 5.25 Power Clock Transistor Power Consumption Circuit ...... 69 5.26 Power Clock Transistor Driving signals...... 70 5.27 Resistor Power Calculation Circuit ...... 72

6.1 Input Power Clock Smaller Transistors ...... 74 6.2 Input Power Clock Signals ...... 75 6.3 Output from Power Clock ...... 75 6.4 High Speed Comparator for Smaller Transistors ...... 76 6.5 Comparator Output Signal ...... 77

LIST OF SYMBOLS

Symbol Definition

β Transistor conductivity

C Capacitance

COX Oxide Capacitance

E Energy

IDS Transistor Drain Current

L Transistor Gate Length

PAVG Average Power

Q Device Charge

R Resistance

T Period

VT Transistor Threshold Voltage

VDD Peak Voltage

VBAT Battery Voltage

µn Electron mobility

xii

Chapter – 1

INTRODUCTION AND BACKGROUND

1.1 OVERVIEW

Lowering the power consumption of electronics has become an increasingly difficult task as our use of technology grows. With new technology emerging each day, we need electronic devices that dissipate less heat and achieve more power savings. The need for very large quantities of “on-chip memory” in the cache memory has fueled research and development in various forms of DRAM [1].

SDRAM (Synchronous Dynamic RAM) cells are widely used in mobile phones because they synchronize data transfer between the CPU and memory, thereby increasing efficiency. Researchers have combined adiabatic and standard CMOS circuit in a single chip [2] to consume less power. But, these circuits consume more power than adiabatic circuits which made them unavailable for modern use.

As we know that DRAM has better performance than SRAM the researchers have combined both DRAM and SRAM and used in modern day routers. They used

SRAM in the head and tail for reading and writing and DRAM in the middle for

buffering [3]. The combinational cache memory architecture (L1: SRAM, L2:

DRAM) offers 31% power savings than 6T SRAM [4].

In this thesis, DRAM cells were used to meet out more power savings. The reason that we have chosen DRAM over SRAM is that the retention time taken by

SRAM is higher than DRAM cell by 11.5% [5]. Lower the retention time, higher will be the power savings. We have chosen adiabatic logic method to build our circuit since the energy consumption of the adiabatic circuit operating at low voltage regime has larger savings as compared to the nominal source voltage [6].

The input to the logic gate communicates with the DRAM cells in the form of bits.

In addition, multiplexers can be built in to steer the bits to the output or other logic gates. The ability of these devices to assume most logic sequences makes them ideal for replacing custom-integrated circuits. The drawback to these devices is their size, since each gate needs at least four transistors, which consume more space and are larger than the custom-integrated circuits. The power savings will be greater because of its adiabatic form.

This thesis shows that DRAM cells can be reconstructed using adiabatic logic to reduce the power requirements, although with some impairment to area and time. Therefore, this method will be more useful in places where power is more important than area or speed.

The circuit in Figure 1.1 is constructed so that the gates acted like a tank oscillator, and the clock is in sinusoidal form. This form is the most efficient because it allows the MOSFETs to be turned on and off slowly.

Figure 1.1 CMOS vs. Adiabatic Model

The RC model shows how much power can be saved using adiabatic form.

Figure 1.1 shows a comparison of the adiabatic model and the CMOS model. The

CMOS model [7] consumed more power as it acted quickly to change the input of the gate. Almost all the adiabatic circuits work as Positive Feedback Adiabatic

Logic (PFAL), this method is more energy efficient [8] compared to the conventional CMOS technique. The adiabatic model acts slowly as the input power is raised from 0 to VDD. The gradual increase of the signal lowers the heat in the transistor. Adiabatic form indicates that the process occurred without the

transfer of heat. Figure 1.2 shows the RC model, which is used to save power. The following derivation can be found in [7].

Figure 1.2 Adiabatic RC Model

The equation for Figure 1.2 is given as

푑푉 푉 = 푅퐶 푐 + 푉 . (1.1) 퐶퐿퐾 푑푡 퐶

푉퐷퐷푡 For simplification, VCLK is modeled as a ramp function between 푇

0 < t < T.

The solution for VC is

푅퐶 −푡 푉 = 푉 − 푉 (1 − 푒 ⁄푅푐) (1.2) 푐 퐶퐿퐾 푇 퐷퐷 between 0 < t < T.

The energy consumed by the circuit is then found using Equation 1.2 and integrating it as

푇 푇 (푉 −푉 )2 퐸 = ∫ 푖푉 푑푡 = ∫ 퐶퐿퐾 푐 푑푡. (1.3) 0 푅 0 푅

The result of Equation 1.3 is

푅퐶 푅퐶 푅퐶 −푇 퐸 = ( ) 퐶푉2 (1 − + 푒 ⁄푅퐶) . (1.4) 푇 퐷퐷 푇 푇

Equation 1.4 shows that, when T >> RC, a power savings would occur, as described in

푅퐶 퐸 = ( ) 퐶푉2 , (1.5) 푇 퐷퐷 and when T << RC, the power used would compare to that consumed by the

CMOS, as shown by

1 퐸 = ( ) 퐶푉2 . (1.6) 2 퐷퐷

Thus, when the frequency is low, less power is consumed in the adiabatic circuitry. When the frequency is high, the power consumption matches the CMOS gate. These adiabatic circuits which utilize AC power supply to recycle the energy

of node capacitance [9]. Chapter 4 presents a similar power equation to show the consumption of power using transistors.

1.2 TANK OSCILLATOR OPERATION

The tank oscillator circuit [10] is shown in Figure 1.3. The battery aids in starting and maintaining the oscillation, despite some energy loss in the form of heat. Otherwise, the oscillator will provide a highly efficient circuit. The two

Figure 1.3 Tank Oscillator Circuit oscillators need to be out of phase with each other. This is the basis for the adiabatic circuit. The logic operations were performed in the capacitive part of the circuit.

In general, MOSFET transistors are capacitive in their input gates, and the charges from the oscillation is used to charge the gate.

The tank circuit requires that the capacitance, resistance, and inductance remains constant. The adiabatic logic circuit fulfills the constant capacitance of the circuit, C1 and C2. The oscillation from this circuit is used to power the circuit and propagate the signal through the logic. The energy lost by the capacitance (mostly dissipated as heat) is recovered in the inductor. There are two sets of oscillators since each gate has to be 180 degrees out of phase with each other. Finally, the sinusoidal clock is used because it is the most efficient clock for energy recovery.

Chapter – 2

LITERATURE REVIEW

This thesis seeks to compare different simulations of DRAM cells in an adiabatic model with submicron technology, which offers significant power savings compared to conventional CMOS. All the circuits used in this research are in adiabatic form to take advantage of the power savings associated with this method’s slow turn-on. Power-saving techniques were researched from the

Institute of Electrical and Electronic Engineers (IEEE) journals and transactions as well as from published books. To increase the capacity of conventional DRAM without modifying its physical structure, a multi-level DRAM [11] cell is used.

However, this type of DRAM cell has lots of design challenges which makes it unavailable for modern day use. The methods employed in this project involves various power-saving techniques using CMOS or a variation of CMOS logic, all in adiabatic form. This thesis shows the viability of adiabatic DRAM cells and the power savings that can result from the use of a larger device.

There are many journal articles that include work on different methods of adiabatic logic. In [12], Pass transistor CMOS Adiabatic Logic (PAL) is examined

for power savings. The power consumed by this method is analyzed and is found that it consumes 10% lower than conventional method [13]. This method has been implemented to design low voltage flip-flop using different optimization technique

[14]. An adiabatic circuitry called TSEL (True Single Phase adiabatic logic) is also introduced, and a comparison of the power savings of these circuits to both

PAL and CMOS adiabatic Logic (CAL) is discussed. The result is derived from inverter cascades and has an average power efficiency 2.5 times greater than

CMOS. Notably, TSEL increases the power clock, which causes a greater loss in efficiency. Another two types of adiabatic logics 2PASCL (Two Phase Adiabatic

Logic) and ECRL (Efficient Charge Recovery Logic) are compared with conventional CMOS circuit. Thus, these two adiabatic logic circuits consume less power than the conventional CMOS [15]. The single-phase clock is achieved by alternating stages with PMOS and NMOS transistors. The gate requires a 4- transistor (4T) cross-coupled pair inverter and a power clock.

The work in this thesis is based on the work in [16]. The clocking schemes and the inverter are the basis for the other primitives discussed in the thesis. The

NAND gate, shown in [17], is a two-input gate. This gate is not based on the cross-coupled model, but it is optimized for connecting with a cross-coupled inverter to obtain a proper output.

An adiabatic SRAM core is discussed in [7]. It is a modification of a standard six-transistor SRAM cell. However, in this thesis, the standard SRAM cell was first converted into a 3T DRAM cell and then is used as a 4T DRAM cell using cross-coupling. The power saving is achieved by connecting VDD and the ground connections of the cell to a variable source. This would require a circuitry that could vary these voltages depending on whether the cell is in the read or write phase.

The simplest form of clock used in [7] is also used for the simulation and power comparisons of this work. In this thesis, four power clock circuits are discussed, each based on the circuitry established in Chapter 1. The differences are the transistor connections to the circuit, which affects the shape of the sinusoidal waveform.

2.1 Static Random Access Memory (SRAM)

SRAM provides static random access memory implementation. Here, six transistors were used to store bits of data. Six-transistor (6T) SRAM creates an

L1 data cache in microprocessors. Since SRAM offers a short access time, it can retain data for tens of microseconds. The current level of device miniaturizations made it difficult to model 6T SRAM memories with the required level of reliability. 6T SRAM also suffers from instability, which results in reduced

performance and greater technology scaling [17]. Process variation directly attacks the weaknesses of 6T SRAM-producing transistors that deviate from their sizes, causing device mismatches and limiting the operating speed of individual cells and memory lines [18]. A new type of SRAM named super SRAM had been implemented using 6T DRAM and 2T DRAM. This device worked as 2T

DRAM during active state and 6T SRAM during stand by state [19].

Figure 2.1 shows the schematic of a standard 6T cell. To perform a read operation, both bit-lines must be precharged to high; then the word line is strobed and the discharging bit-line is determined. If the bit-line that discharges is inverted, then ‘1’ is read; if it is regular, then ‘0’ is read. Variations in the gate length and threshold voltages of these transistors change the current driving capabilities.

Figure 2.1 Schematic 6T SRAM

Process variation can also attack the stability of a 6T SRAM cell. For example, transistor T2 was designed to be strong while transistor T1 was moderately strong and transistor T3 was weak. In read, this allowed T2 to quickly discharge the necessary bit-line while ensuring that the intermediate node between T2 and T3 did not rise enough to store a 1 when it should store a 0.

Any variation within the cell changed the strength of each transistor and may have led to a weaker T2 that did not discharge the bit-line quickly enough. Such variation allowed the value at the intermediate node to rise completely and flip the bit stored in the circuit, causing a pseudo-destructive read. The same

analysis held true for transistors T4, T5, and T6. Variation also caused instability in the write operations [20].

2.2 1T1C DRAM Cell

Information is stored as different charge levels in a capacitor in conventional 1Transistor1Capacitor (1T1C) DRAM (see Figure 2.2). The advantage of using DRAM is that it is structurally simple: only one transistor and one capacitor are required for storing one bit, compared to the six transistors that are required in SRAM. The DRAM industry has advanced over time, packing more and more memory bits per unit area onto a silicon. 1T1C DRAM cells are widely used because of its decreased size, complexity and power consumption relative to SRAM cells [21]. But the scaling for the conventional

1T1C DRAM has become increasingly difficult, because the capacitor is harder to scale as device geometries shrink. Apart from the problems associated with the scaling of the capacitor, scaling also introduces another major problem for

DRAM manufacturers in the form of leakage current.

Figure 2.2 Schematic 1T1C DRAM cell 2.3 4T DRAM Cell

The cell structure shown in Figure 2.3 is that of a 4T DRAM cell. This

DRAM cell design consisted of four transistors: one used as a write transistor and the other used as a read transistor. The rest two acts as output transistors. As previously mentioned, data in DRAM is stored as a charge in the capacitive structure that is attached to the transistor structure. Since the storage nodes lack a current path for restoring the data, data is lost to leakage over certain periods of time [22]. The read operation for a 4T DRAM cell is non-destructive, as the voltage at the storage node is maintained. One of the reason we have chosen 4T

DRAM is its power savings compared to all the other DRAM cells, its power consumption is 20.4% lower than similar sized 3T DRAM [23]. Another reason to choose 4T-DRAM cells is that these cells have lower noise margin and higher susceptibility to radiation effects [24]. This DRAM cell can be implemented in a generic logic process achieving roughly two times higher bit cell densities compared to 6T SRAM cells [25]. 4T DRAM cells have leakage power of 152.4 mW [26].

Figure 2.3 4T DRAM CELL

2.4 3T DRAM Cell The simplest DRAM cell is the 3T scheme. A 3T DRAM cell has a higher density than a SRAM cell. Moreover, in a 3T DRAM cell, there is no constraint on device ratios, and the read operation is nondestructive. The power consumption of this cell when 45nm transistor is used is almost similar to the power consumed by 4T DRAM cell [27]. In this cell, the storage capacitance is the gate capacitance of the readout device, making this scheme attractive for embedded memory applications. However, a 3T DRAM still offers limited performance and low retention time, both of which severely limit its use in advanced integrated circuits. 3T DRAM cell has a 43.6% faster write speed than

3T1D cell and uses less dynamic current which is 30.4% [28]. 3T DRAM utilizes the transistor gate and a capacitance to store the data value. A new technique has been proposed named as sleep transistor power technique [29]

which helps in reducing the leakage power and noise of 3T DRAM. Higher the voltage lower will be the leakage power and noise measurement [29]. Compared to the classical 6T SRAM this 3T DRAM has 40% smaller area and leakage is reduced up to 14 times while access time is approximately the same [30] which helps in achieving higher retention time. When data is to be written, a write signal is enabled, and the data from the bit-line is fed into the cell. When data is to be read from the cell, a read line is enabled, and data is read through the bit- line. The power consumption of this cell is higher than our 4T DRAM cell [31].

Using HSPICE an extensive evaluation has been pursued at nano feature sizes

(from 45nm to 22nm) [32] which proves that 3T DRAM has higher retention than 3T1D DRAM cell. A 3T DRAM cell also occupies less area than a 4T

DRAM cell (see Figure 2.4). This DRAM cell has leakage power of 217.9 mW

[26].

Figure 2.4 3T DRAM CELL

2.5 3T1D DRAM Cell In 3T1D DRAM the diode acts a storage device and an amplifier [33].

When compared 3T1D DRAM cell with 3T DRAM cell the former achieved longer retention than the latter. At higher temperature, these DRAM cells tend to be instable [34]. These DRAM cells are faster than our conventional 6T SRAM cells, which means the cell performance would be increased [35]. As far as size is concerned increasing the width of read related transistors in 3T1D DRAM cell decreases the access time most of the time [36]. But for transistor sizes below

65nm it is not the same case since the transistor shows a vast limitation. This would still help in decreasing initial access time. The average power consumed by 3T1D

DRAM cell is compared with conventional 6T SRAM and this DRAM consumes less power. The analysis of 3T1D DRAM for average power consumption and timing, that is, retention time, read and write access time was done by varying supply voltage from 0.7V to 1.1V [37]. Threats on reliability and performance of

6T SRAM cells led to the design of 3T1D DRAM cell as a potential replacement

[38].

Figure 2.5 3T1D DRAM CELL

Chapter – 3

RESEARCH STATEMENT This thesis seeks to accomplish three primary tasks. The first is to design gates based on DRAM cells in the widely-used inverter form. Within the literature

examined for this project, only the inverter and an adder are described in any of the texts. Thus, this thesis works to produce designs such as Not, NAND_AND,

NOR_OR, and XNOR_XOR in adiabatic form. These designs are described in

Chapter 4.

The second task is to implement these designs in ultra-low micron transistors, which will help to compare the voltage between these transistors and the normal MOSFETs. A power clock is generated in this method.

The third task involves using the gates developed in Chapter 5 to create a power clock circuit. Therefore, this work will add to adiabatic circuitry. The gates that are built include a power comparator and power clock generator for smaller transistors (such as those used in Chapter 5).

Chapter – 4

ADIABATIC GATES AND POWER CONSUMPTION

This section explains the following list of gates that were developed with the adiabatic method, using graphs to show the inputs and outputs of each gate: NOT,

NAND_AND, NOR_OR, and XNOR_XOR. These gates were based on 4T

DRAM cells, shown in [17]. The DRAM cell proposed in [17] is a sensing amplifier that is different from those found in this thesis. Of the journals examined, none show more than an inverter or an adder in adiabatic form. This thesis uses an inverter structure mentioned in [16]. All the primitive gates shown in this chapter are simulated using different software. This chapter also provides the calculation for each gate’s power consumption.

4.1 ADIABATIC CELLS

Adiabatic circuitry is a method of charge sharing. Adiabatic logic gates save

86% to 93% power as compared to conventional CMOS logic gates [39]. An adiabatic gate has differential inputs and outputs. A NOR gate becomes an OR gate, and a NAND gate becomes an AND gate by reversing the leads on the output.

In addition, the inverter becomes a buffer, and the XNOR becomes an XOR.

Complex logic gates like NAND-AND, NOR-OR, XNOR-XOR can be made using pass-transistor logic, since it is simple and fast [40]. Finally, the clocks must be sinusoidal, and the stages that follow must have a clock that is 180 degrees out of phase. For the simulations in this chapter, a pure sinusoidal clock with a source in

LTSpice and PSpice are used.

4.1.1 Gates Using LTSpice

The following section deals with adiabatic cells that are simulated using

LTSpice. The transistor parameter values used for the simulation are derived using the formulae from [41].

4.1.1.1 NOT Adiabatic Cell

The circuit shown in Figure 4.1 is the basis of all the other gates that were used in this research. During the rising edge of clock pulse 1, M4 and M2 allowed the current to flow to the OUT (M1:d) and NOUT (M4:s) signals. Each of these outputs needed to be loaded down by a capacitance.

Figure 4.1 NOT Adiabatic Cell

In the above circuit, the pulsed voltage source acts like a clock, and two clocks are used. When pulse 2 is on, the charge could not flow back through the

input transistors. At this point, M1 and M3 are off. If the input X is high, then M4 would be on, and M2 would be off. The charge on the capacitance then flows back down through M2. Thus, when the output on X is high, the capacitance on the circuit connected to OUT lost its charge while the NOUT capacitance kept its charge. Figure 4.2 shows the input into the gate, and Figure 4.3 shows the output of the NOT gate.

Figure 4.2 NOT Input

Figure 4.3 NOT Output

4.1.1.2 NOR-OR Adiabatic Cell

The NOR-OR gate is shown in Figure 4.4. During the rising edge of clock pulse 1, M5, M6 and M2, M3 allowed the current to flow to the OUT (M1:d) and

NOUT (M4:s) signals. As with the NOT cells, each of these outputs are loaded down by a capacitance.

Figure 4.4 NOR-OR Adiabatic Cell

In the above circuit, the pulsed voltage source acts as a clock, with two clocks being used. When pulse 2 is on, the charge is unable to flow back through the input transistors. At that time, M1 and M4 are on. If the input X is high, then one of the two paths back to the clock line made by M1 and M3 or M2 is on or through M4, and M5 or M6 is closed, allowing the charge to leave on the transistor of the following stage. See Figure 4.5 below for the NOR-OR input. As shown in

Figure 4.6, the OUT signal is on the high side for the NOR gate, and the NOUT signal is on the low side. When either of the input is high, the output is low. When both inputs are low, the output is high. The gate depicted in this section operates as a NOR gate.

Figure 4.5 NOR-OR Input

Figure 4.6 NOR-OR Output NOUT

4.1.1.3 NAND-AND Adiabatic Cell OUT

The NAND-AND gate is shown in Figure 4.7. During the rising edge of the clock pulse 1, M5, M6 and M2, M3 allowed the current to flow to the OUT (M1:d)

and NOUT (M4:s) signals. In addition, these outputs are loaded down by a capacitance.

Figure 4.7 NAND-AND Adiabatic Cell

In the circuit shown in Figure 4.7, the pulsed voltage source acts as a clock

(two total). When pulse 2 is on, the charge is not able to flow back through the input transistors. At that point, M1 and M4 are on. If the input X is high, then one of the two paths back to the clock line made by M1 and M3 or M2 will be on or through M4, and M5 or M6 will be closed, allowing the charge to leave on the transistor of the following stage. In Figure 4.8, the input to the NAND-AND gate is shown. Figure 4.9 illustrates that, when the signal is high, the output will try to rise, but when the output is low, the signal will be dropped and followed the clock.

Figure 4.8 NAND-AND Input

Figure 4.9 NAND-AND Output NOUT

OUT

4.1.1.4 XNOR-XOR Adiabatic Cell

The XNOR-XOR gate is shown in Figure 4.10. This circuit behaves almost identical to the NOR-OR and NAND-AND gates. During the rising edge of clock pulse 1, M2, M3, M4, M5, and M7, M8, M9, M10 allowed the current to flow to the OUT (M1:d) and NOUT (M6:s) signals. These outputs are loaded down by a capacitance.

Figure 4.10 XNOR-XOR Adiabatic cell

In this circuit, the pulsed voltage source provides a clock, with two clocks being used. When pulse 2 is on, the charge could not flow back through the input transistors. At this point, M1 and M6 are on. If the input X is high, then one of the two paths back to the clock line made by M1 and M3 or M2 is on or through M6, and M7 or M8 is closed, allowing the charge to leave on the transistor of the following stage. See Figure 4.11 below for a depiction of the input of this gate.

As shown in Figure 4.12, the OUT signal is high for the XNOR gate, and the

NOUT signal is low. When either input is high, the output is low. However, when both inputs are low, the output is high. Finally, the gate operates as an XNOR gate.

Figure 4.11 XNOR-XOR Input

Figure 4.12 XNOR-XOR Output NOUT

OUT

4.2 Gates Using PSPICE

The following section consists of adiabatic cells that are simulated using Pspice technology. The transistor parameter values used for the simulation are derived by using [42].

4.2.1. NOT Adiabatic cell

In Figure 4.13, the circuit is the same as the circuit that was used with

PSpice technology. During the rising edge of clock pulse 1, M4 and M2 allowed the current to flow to the OUT (M2:d) and NOUT (M4:s) signals. These outputs are each loaded down by a capacitance.

Figure 4.13 NOT Adiabatic Cell

In this circuit, the pulsed voltage source functions as a clock, and two clocks are used. When the DSTM1 (Digital Clock) is on, the charge is unable to flow back through the input transistors. At this point, M1 and M3 are on. If the input X is high, then M4 is on, and M2 is off. The charge on the capacitance flows back down through M2. Thus, when the output on X is high, the capacitance on the circuit connected to OUT loses its charge while the NOUT capacitance keeps its charge. Figure 4.14 shows the input into the gate, and Figure 4.15 shows the output on both signals.

Figure 4.14 NOT Input

Figure 4.15 NOT Output

4.2.2 NOR-OR Adiabatic cell

The NOR-OR gate is shown in Figure 4.16. During the rising edge of the clock, M1 and M5 allowed current to flow through the OUT and NOUT lines to the following stage. This charges the gate and turns the transistor on. During the evaluation stage or falling edge, one of the two paths back to the line made by M3 and M1 or M2 is on or through M6, and M4 or M5 is closed, allowing the charge

to leave on the following stage.

Figure 4.16 NOR-OR Adiabatic Cell

As shown in Figure 4.18, the OUT signal is high for the NOR gate. When either of the input is high (see Figure 4.17), the output is high and forms an OR gate. During the evaluation stage, only one side of the gate is on while the other side is off. Therefore, the off portion of the gate do not consume power, which makes the circuit more efficient than the LTSpice.

Figure 4.17 NOR-OR Input

Figure 4.18 NOR-OR Output

4.2.3 NAND-AND Adiabatic cell

The NAND-AND gate is shown in Figure 4.19. During the rising edge of the clock, M7 and M8 allow current to flow through the OUT and NOUT lines to

the following stage. This charges the gate and turns the transistor on. During the evaluation stage or falling edge, one of the two paths back to the line made by M8 and M1 or M2 is on or through M7, and M6 or M5 is closed, allowing the charge to leave on the following stage.

Figure 4.19 NAND-AND Adiabatic Cell

The input for the NAND-AND gate is shown in Figure 4.20 while the output is shown in Figure 4.21. As the illustration of the output (Figure 4.21) makes clear, an NOUT signal would be high for a NAND gate if either of the inputs needs to be high. When both inputs are high, the output is high and forms an AND gate.

During the evaluation stage, only one side of the gate is on while the other side was off. The off portion of the gate did not consume power, which makes the circuit more efficient than the LTSpice.

Figure 4.20 NAND-AND Input

Figure 4.21 NAND-AND Output

4.2.4 XNOR-XOR-Adiabatic cell

Figure 4.22 shows the XNOR-XOR gate. During the rising edge of the clock, M10 and M5 allowed current to flow through the OUT and NOUT lines to the following stage. This charges the gate and turns the transistor on. During the evaluation stage or falling edge, one of the two paths back to the line made by M10 and M6, M7, M8 or M9 would be on or through M5, and M1, M2, M4 or M3 would be closed, allowing the charge to leave on the following stage.

Figure 4.22 XNOR-XOR Adiabatic Cell

The input for the XNOR gate is shown in Figure 4.23 and the output in

Figure 4.24. As Figure 4.24 shows, an OUT signal would be high for an XOR gate

if either of the input needs to be high. When both inputs were high, the output is high and forms an XNOR gate. During the evaluation stage, only one side of the gate is on, and the other side is off.

Figure 4.23 XNOR-XOR Input

Figure 4.24 XNOR-XOR Output

4.3 GATE POWER CONSUMPTION

The equation used to determine power consumption (based on the simplification that the input is a ramp and the transistor that is passing the current is a resistor) is shown in Chapter 1. This method appears in [7] for determining the energy consumption of the cell. As we have been stating in this thesis, adiabatic circuits consume less power than conventional CMOS but at the cost of frequency

[43].

The individual gates use the same equation for calculating power consumption since they all charge a transistor on the following gate. In addition, since they use the same transistor setup as a diode through which a charge is passed, they only differ by the amount of capacitance that is loading the circuit. A simplification of this circuit is shown in Figure 4.25. It is not necessary to show the other transistors since they are off during the charging phase. Only one of the charging transistors is on because the other capacitance was already at full charge.

M1 represents the charging transistor that was connected as the diode, and C1 represents the load capacitance of the following gate or output circuit.

Figure 4.25 Power Consumption Circuit

The voltages of the circuit are described by

푉퐶퐿퐾 = 푉퐷푆 + 푉퐶 . (4.1)

Since M1 will always include 푉퐺푆 = 푉퐷푆, then

퐶 푊 퐼 = 휇 표푥 (푉 − 푉 )2 . (4.2) 퐷푆 푛 2퐿 퐺푆 푇

This applies for the current through the transistor. The input is a cosine

푉 푡 wave clock signal, but for simplification, a ramp function 퐷퐷 is used. 푇

Substituting the ramp function and the differential for the capacitor leads to

푉퐷퐷푡 1 = 푉퐷푆 + ∫ 퐼퐷푆푑푡. (4.3) 푇 퐶

In this situation, 푉퐷푆 will rise to 푉푥 + 푉푇 . The 푉푥 value will be constant after a certain time if T is not too small, leading to

푉 푡 1 훽푊 2 퐷퐷 = 푉 + 푉 + ∫ 푉 푑푡 . (4.4) 푇 푥 푇 퐶 퐿 푥

Equation 4.4 is differentiated with respect to t, resulting in

푑푉푥 푉 1 훽푊 2 ′ = 퐷퐷 − 푉 푡 < 푡 < 푇 . (4.5) 푑푡 푇 퐶 퐿 푥

′ The 푉푥 term is at 0V until 푡 , which is the time that it takes for 푉퐷푆 to reach

푉푟. This is a separable equation, which yields

−퐶퐿 1 ∫ 푉 퐶퐿 푑푉푥 = ∫ 푑푡 . (4.6) 훽푊 푉2− 퐷퐷 푥 훽푊푇

The solution obtained for Equation 4.6 is

−푡⁄ 1−푒 푘2 푉 = −√푘 , (4.7) 푥 1 −푡⁄ 1+푒 푘2

푉퐷퐷퐶퐿 훽푊 where 푘1 = and 푘2 = . The voltage on the capacitor can then 훽푊푇 퐶퐿2√푘1 be written as

−푡⁄ 푉 푡 1−푒 푘2 푉 = 푉 − 푉 − 푉 = 퐷퐷 + √푘 − 푉 푡′ < 푡 < 푇 (4.8) 퐶 퐶퐿퐾 푥 푇 1 −푡⁄ 푇 푇 1+푒 푘2

and 푉퐷푆 as,

−푡⁄ 1−푒 푘2 푉 = 푉 + 푉 = −√푘 + 푉 푡′ < 푡 < 푇 . (4.9) 퐷푆 푥 푇 1 −푡⁄ 푇 1+푒 푘2

′ 푉푐 will equal 0V until 푡 , and 푉퐷푆 will equal 푉푐. The previous equations for voltage are plotted in Figure 4.26 below while Figure 4.27 shows the voltages of the primitive gate.

Figure 4.26 Voltage (Vc)

Figure 4.27 Voltages of Primitive Gate

In Figure 4.27 the y axis for 푉푥 is on the right side, and the others are on the left. 푉푥 will rise to a constant and remain that way for the full charging phase.

Once the charging phase has ended, 푉푥 returns to 0V. A fast clock will generate a steep ramp. 푉푥 will follow the ramp upward because the current through the transistor will not be able to charge the capacitor quickly enough. This allows 푉푥 to be large. The slower the ramp is, the lower 푉푥 will be and the sooner it will reach its constant value.

푇 ∫ 퐼퐷푆푉퐷푆푑푡 The average power consumption is 푃 = 0 . This creates the 퐴푉퐺 푇 integral form

푇 훽푊 푃 = ∫ ( 푉 + 푉 ) 푉2 푑푡 . (4.10) 퐴푉퐺 푡′ 푇퐿 푥 푇 푥

Expanding and simplifying Equation 4.10 leads to

3 2 −푡⁄ −푡⁄ 훽푊 푇 1−푒 푘2 1−푒 푘2 푃 = (−√푘 ) + 푉 (−√푘 ) 푑푡. (4.11) 퐴푉퐺 ∫푡′ 1 −푡⁄ 푇 1 −푡⁄ 푇퐿 1+푒 푘2 1+푒 푘2

If 푡′ is redefined as 0 and the integration is from 0 to T-푡′, the power

equation is as follows:

3 푡 훽푊 ⁄ − ⁄ 4푘2 4푘2 2 푘2 푃퐴푉퐺 = [−푘 (2푘2 ln (1 + 푒 ) + 푡 − 푡 − 2) + 푇퐿 1 − ⁄푘 −푡⁄ 1+푒 2 (1+푒 푘2)

4푘 푉 푘 (푡 − 2 )] (4.12) 푇 1 −푡⁄ 1+푒 푘2

−푡⁄ A simplification of Equation 4.12 must be performed since 1>>푒 푘2 for

the parameters used in this thesis. After the simplification,

푉 퐶2퐿 퐶푉 푉 퐶퐿 푉 푉 퐶 푉 푉 퐶2퐿 1 푃 = 퐷퐷 + 퐷퐷 √ 퐷퐷 + 퐷퐷 푇 + 퐷퐷 푇 (4.13) 퐴푉퐺 (푇−푡′)2훽푊 푇−푡′ (푇−푡′)훽푊 푇−푡′ 2(푇−푡′)2훽푊 푉 퐶퐿 √ 퐷퐷 (푇−푡′)훽푊

results, where t’ is time when 푉퐷푆 = 푉푇. 푉퐷퐷 is the peak voltage of the ramp

function. Equation 4.13 shows that the amount of power consumed by the gates

depends on the NMOS transistor that is charging the cell and the input capacitance

of the NMOS on the following gate. To lower the power consumption of the

adiabatic cells and slow it down (thereby making T larger), reduce the capacitance,

or make the gate smaller on the input gates, one must lower the peak amplitude of

the input clock and increase the width of the charging transistor. Increasing the width of the charging transistor would be the least-desirable option because it would result in an area penalty. The MOSFET parameters used in this thesis for the PSpice level 2 model are calculated using this power equation. The result was that 9.49 x 10-7 watts would be used per gate. When compared to a CMOS power consumption, this resulted in a 97% power savings, which aligned with the results seen in [7] when using their RC model. This value is calculated with a frequency of 100 MHz and a peak amplitude of 1.2 V.

4.4 POWER CLOCK POWER CONSUMPTION

The power clock loses power through the transistor and the other passive components. Adiabatic circuits which adopt a gradual rising and falling of power clock can result in a considerable energy saving. However, the operational constraint that the output signal should track the power clock’s slow ranging behavior to accomplish the adiabatic charging and discharging creates a major difficulty in the circuit design [44]. Figure 4.28 depicts a simplified circuit to calculate the power consumption of the power clock transistor [45].

Figure 4.28 Power Clock Transistor Power Consumption Circuit

V1 represents the voltage created by the other oscillator on this power clock output while V2 is the source power clock signal. These two voltages are out of phase with each other, as shown in Figure 4.29.

Figure 4.29 Power Clock Transistors Driving Signals

As Figure 4.29 shows, when 푉퐺푆 is at its peak, 푉퐷푆 is at its lowest value.

During almost half of the cycle, the transistor is in the linear region. For a short

period, the device is in saturation, but for most of the second half, it is in cutoff.

For the triode region,

푉퐺푆 ≥ 푉푇 푉퐷푆 ≤ 푉퐺푆 − 푉푇 must be true. The goal is to limit the amount of time that the transistor is in the saturation region to limit the charge that is lost. To keep the transistor completely out of the saturation region, the threshold voltage could be raised until it is equal to the value of the input DC source on the oscillator. Thus, the transistor would be completely in the triode region and would be conducting on only half of the cycle when 푉퐷푆 is below the battery voltage. The power consumption of this transistor could be determined using the equations below. The gate voltage is described by

−휋푡 푉 = 푉 푐표푠 ( ) + 푉 (4.15) 1 퐵퐴푇 푇 퐵퐴푇 and the drain voltage by

휋푡 푉 = 푉 푐표푠 ( ) + 푉 . (4.16) 2 퐵퐴푇 푇 퐵퐴푇

푉퐵퐴푇 refers to the battery or DC source that is applied to the oscillating circuit. The current through the transistor in the linear region is found in

훽푊 1 −2휋푡 −휋푡 휋푡 1 2휋푡 −2휋푡 퐼 = [푉2 ( 푐표푠 ( ) + 푐표푠 ( ) + 푐표푠 ( ) − 푐표푠 ( ) − 2푐표푠 ( )) − 퐷퐿 2퐿 퐵퐴푇 2 푇 푇 푇 2 푇 푇

휋푡 푉 푉 (푐표푠 ( ) + 1)] . (4.17) 퐵퐴푇 푇 푇

Meanwhile, the power consumed is shown as

1 푇⁄ 푃 = ∫ 2 퐼 푉 푑푡 . (4.18) 퐴푉퐺푙 푇 0 퐷퐿 퐷푆

When substituting Equations 4.16 and 4.17 into Equation 4.18 the result is

푇⁄ −휋푡 훽푊 1 −2휋푡 −휋푡 푃 = ∫ 2 (푉 푐표푠 ( ) + 푉 ) ( ) [푉2 ( 푐표푠 ( ) + 푐표푠 ( ) + 퐴푉퐺푙 0 퐵퐴푇 푇 퐵퐴푇 2퐿 퐵퐴푇 2 푇 푇

휋푡 1 2휋푡 −2휋푡 휋푡 푐표푠 ( ) − 푐표푠 ( ) − 2푐표푠 ( )) − 푉 푉 (푐표푠 ( ) + 1)] 푑푡 . (4.19) 푇 2 푇 푇 퐵퐴푇 푇 푇

All the cosine terms will integrate to 0 since sin(n휋)=0. Therefore, the average power consumed by the clock circuit is

푇⁄ 훽푊 푃 = ∫ 2 ( 푉 푉 )푉 푑푡. (4.20) 퐴푉퐺푙 0 2퐿 퐵퐴푇 푇 퐵퐴푇

After integration, the result is as follows:

훽푊 푃 = 푉 푉2 (4.21) 퐴푉퐺푙 푇 퐵퐴푇 4퐿

The resistor and capacitor are also used in the circuit. The power in the resistor could be found by using the circuit shown in Figure 4.30 below.

Figure 4.30 Resistor Power Calculation Circuit

If V1 is modeled as a ramp function, this would be the same as the derivation from Chapter 1. Therefore, the average power consumed in this circuit

1 can be found using Equation 1.4 and then multiplying by , resulting in 푇

푅퐶 푅퐶 푅퐶 −푇⁄ 푃 = 퐶푉2 (1 − + 푒 푅퐶). (4.23) 퐴푉퐺푅 푇2 1 푇 푇

If the small saturation region is ignored, then the total power consumed can be found by

푃푇푂푇퐴푉퐺 = 2 푃퐴푉퐺퐿 + 푁 푃퐴푉퐺퐺퐴푇퐸 + 2 푃퐴푉퐺푅, (4.24) where N represents the number of gates in the circuit.

Chapter – 5

ADIABATIC GATES (L=45 nm & L=22 nm)

This chapter explains each gate developed with the adiabatic method using graphs to show the inputs and outputs. The gates that are developed included

NOT, NAND_AND, NOR_OR and XNOR_XOR gates. These gates are based on

4T DRAM cells shown in [17]. The DRAM cell proposed in [17] is a sensing amplifier, which is different from those found in this thesis. None of the journals examined for this project shows more than an inverter or an adder in adiabatic form. In this thesis, the structure used is an inverter, and all of the primitive gates are shown. This chapters shows the same gates that are simulated using LTSpice software and states the calculation of the power consumed by each gate.

5.1 ADIABATIC CELLS (L=45 nm)

Adiabatic circuitry is a method of charge sharing. The adiabatic gate has differential inputs and outputs. A NOR gate becomes an OR gate, and NAND gate becomes an AND gate by reversing the leads on the output. In addition, the inverter becomes a buffer, and the XNOR becomes an XOR. The clock must be sinusoidal, and the following stages must have a clock that is 180 degrees out of phase. The clock used in the simulations shown in this chapter is a pure sinusoidal

clock using a source in LTSpice. The transistor parameters are calculated using the methods explained in [46].

5.1.1 NOT Adiabatic Cell

The circuit shown in Figure 5.1 is the basis of all the other gates that are used in this section. During the rising edge of clock pulse 1, M4 and M2 allow the current to flow to the OUT (M1:d) and NOUT (M4:s) signals. Each output must be loaded down by a capacitance.

Figure 5.1 NOT Adiabatic Cell (L=45 nm)

In this circuit, the pulsed voltage source acted as a clock, with two clocks being used. When pulse 2 was on, the charge could not flow back through the input transistors. At this point M1 and M3 are on. If the input X is high, then M4 is

on, and M2 is off. The charge on the capacitance flows back down through M2.

Thus, when the output on X is high, the capacitance on the circuit connected to

OUT lost its charge while the NOUT capacitance kept its charge. Figure 5.2 shows the input into the NOT gate, and Figure 5.3 shows the output of the NOT gate.

Figure 5.2 NOT Input

Figure 5.3 NOT Output

5.1.2 NOR-OR Adiabatic Cell

The NOR-OR gate is shown in Figure 5.4. During the rising edge of clock pulse 1, M5, M6 and M2, M3 allowed the current to flow to the OUT (M1:d) and

NOUT (M4:s) signals. These outputs had to each be loaded down by a capacitance.

Figure 5.4 NOR-OR Adiabatic Cell (L=45 nm)

In the above circuit, the pulsed voltage source acted as clock, and two clocks are used. When pulse 2 is on, the charge could not flow back through the input transistors. At that point, M1 and M4 are on. If the input X is high, then one of the two paths back to the clock line made by M1 and M3 or M2 is on or through M4, and M5 or M6 is closed, allowing the charge to leave on the transistor of the following stage. As shown in Figure 5.6, the OUT signal is high for the NOR gate and low for the NOUT gate. When either input is high, the output is low. When both inputs are low, the output is high. This gate operates as a NOR gate.

Figure 5.5 NOR-OR Input

Figure 5.6 NOR-OR Output NOUT

OUT

5.1.3 NAND-AND Adiabatic Cell

The NAND-AND gate is shown in Figure 5.7. During the rising edge of clock pulse 1, M5, M6 and M2, M3 allowed the current to flow to the OUT (M1:d) and NOUT (M4:s) signals. These outputs had to be loaded down by a capacitance.

Figure 5.7 NAND-AND Adiabatic Cell(L=45 nm)

The pulsed voltage source in the above circuit acted as a clock; there are two clocks used. When pulse 2 is on, then the charge could not flow back through the input transistors. At that time, M1 and M4 are on. If the input X is high, one of the two paths back to the clock line made by M1 and M3 or M2 was on or through M4, and M5 or M6 is closed, allowing the charge to leave on the transistor of the following stage. In Figure 5.8 below, the inputs to the NAND-AND gate are

shown. Figure 5.9 shows that, when the signal is high, the output would attempt to rise. When the output is low, the signal will drop and follow the clock.

Figure 5.8 NAND-AND Input

NOUT Figure 5.9 NAND-AND Output OUT

5.1.4 XNOR-XOR Adiabatic Cell

Figure 5.10 shows the XNOR-XOR gate. This circuit acted much like the

NOR-OR and NAND-AND gates. During the rising edge of the clock pulse 1, M2,

M3, M4, M5 and M7, M8, M9, M10 allowed the current to flow to the OUT

(M1:d) and NOUT (M6:s) signals. As like the others, these outputs had to be loaded down by a capacitance.

Figure 5.10 XNOR-XOR Adiabatic Cell (L=45 nm)

In this circuit, the pulsed voltage source acted as a clock (two total). When pulse 2 is on, the charge is unable to flow back through the input transistors. At this point, M1 and M6 are on. If the input X is high, then one of the two paths

back to the clock line made by M1 and M3 or M2 is on or through M6, and M7 or

M8 was closed, allowing the charge to leave on the transistor of the following stage. As Figure 5.12 shows, the OUT signal is high for the XNOR gate and the

NOUT signal is low. When either input is high, the output is low, but when both inputs are low, the output is high. The gate operated as an XNOR gate.

Figure 5.11 XNOR-XOR Input

Figure 5.12 XNOR-XOR Output NOUT OUT

5.2 ADIABATIC CELLS (L=22 nm)

Adiabatic circuitry is a method of charge sharing. An adiabatic gate has differential inputs and outputs. A NOR gate becomes an OR gate, and NAND becomes an AND by reversing the leads on the output. The inverter becomes a buffer while the XNOR becomes an XOR. The clock must be sinusoidal, and the following stages must have a clock that is 180 degrees out of phase. The clock used in the simulations shown in this section is a pure sinusoidal clock using a source in LTSpice. This is the optimal transistor length for achieving better accuracy.

5.2.1 NOT Adiabatic Cell (L=22 nm)

The circuit in Figure 5.13 is the basis of all the other gates that are used in this section. During the rising edge of clock pulse 1, M4 and M2 allowed the current to flow to the OUT (M1:d) and NOUT (M4:s) signals. These outputs are loaded down by a capacitance.

Figure 5.13 NOT Adiabatic Cell (L=22 nm)

In the above circuit, the pulsed voltage source acted as a clock with two clocks being used. When pulse 2 is on, the charge could not flow back through the input transistors. At this point, M1 and M3 are on. If the input X is high, then M4

is on, and M2 is off. The charge on the capacitance flow back down through M2.

Thus, when the output on X is high, the capacitance on the circuit connected to

OUT loses its charge, and the NOUT capacitance keeps its charge. Figure 5.14 shows the input into the gate while Figure 5.15 shows the output of the NOT gate.

Figure 5.14 NOT Input

Figure 5.15 NOT Output

5.2.2 NOR-OR Adiabatic Cell

Figure 5.16 below shows the NOR-OR gate. During the rising edge of clock pulse 1, M5, M6 and M2, M3 allowed the current to flow to the OUT (M1:d) and

NOUT (M4:s) signals. These outputs have to each be loaded down by a capacitance.

Figure 5.16 NOR-OR Adiabatic Cell (L=22 nm)

In this circuit, the pulsed voltage source acted as a clock (two total). When pulse 2 is on, the charge could not flow back through the input transistors. At that time, M1 and M4 were on. If the input X is high, one of the two paths back to the clock line made by M1 and M3 or M2 is on or through M4, and M5 or M6 is closed, allowing the charge to leave on the transistor of the following stage. Figure

5.18 shows that the OUT signal was high for the NOR gate and that the NOUT signal is low. When either of the input is high, the output is low. When both inputs are low, the output is high. The gate operates as a NOR gate.

Figure 5.17 NOR-OR Input

NOUT Figure 5.18 NOR-OR Output OUT

5.2.3 NAND-AND Adiabatic Cell

The NAND-AND gate is shown in Figure 5.19. During the rising edge of clock pulse 1, M5, M6 and M2, M3 allowed the current to flow to the OUT (M1:d) and NOUT (M4:s) signals. These outputs are loaded down by a capacitance.

Figure 5.19 NAND-AND Adiabatic Cell (L=22 nm)

The pulsed voltage source acted as a clock, and there are two clocks used in this circuit. When pulse 2 is on, the charge is unable to flow back through the input transistor. At that point, M1 and M4 are on. If the input X is high, then one of the two paths back to the clock line made by M1 and M3 or M2 is on or through

M4, and M5 or M6 is closed, allowing the charge to leave on the transistor of the following stage. Figure 5.20 shows the inputs to the NAND-AND while Figure

5.21 shows that, when the signal is high, the output tries to rise as well. When the output is low, the signal is dropped and followed the clock.

Figure 5.20 NAND-AND Input

Figure 5.21 NAND-AND Output NOUT

OUT

5.2.4 XNOR-XOR Adiabatic Cell

The XNOR-XOR gate is shown in Figure 5.22. This circuit acts almost identical to the NOR-OR and NAND-AND gates. During the rising edge of clock pulse 1, M2, M3, M4, M5 and M7, M8, M9, M10 allowed the current to flow to the OUT (M1:d) and NOUT (M6:s) signals. These outputs should be loaded down by a capacitance.

Figure 5.22 XNOR-XOR Adiabatic Cell (L=22 nm)

In this circuit, the pulsed voltage source acted as clock with two clocks total.

When pulse 2 is on, the charge could not flow back through the input transistor. At that point, M1 and M6 are on. If the input X is high, then one of the two paths back to the clock line made by M1 and M3 or M2 is on or through M6, and M7 or

M8 is closed, allowing the charge to leave on the transistor of the following stage.

As shown in Figure 5.24, the OUT signal is high for the XNOR gate while the

NOUT signal is low. When either input is high, the output is low. When both inputs are low, the output is high. This gate operates as an XNOR gate.

Figure 5.23 XNOR-XOR Input

Figure 5.24 XNOR-XOR Output NOUT

OUT

5.3 POWER CLOCK-POWER CONSUMPTION

The power clock loses power through the transistor and the other passive components. Figure 5.25 is a simplified circuit used to calculate the power consumption of the power clock transistor.

Figure 5.25 Power Clock Transistor Power Consumption Circuit

V1 is the voltage created by the other oscillator on this power clock output while V2 is the source power clock signal. These two voltages are out of phase with each other, as shown in Figure 5.26.

Figure 5.26 Power Clock Transistors Driving Signals

As can be seen from Figure 5.26, when 푉퐺푆 is at its peak, 푉퐷푆 is at its lowest value. During almost half of the cycle, the transistor is in the linear region.

For a short period, the device is in saturation, but the majority of the second half, it is in cutoff. For the linear region,

푉퐷푆 ≥ 푉푇 푉퐷푆 ≤ 푉퐺푆 − 푉푇 must be true. The goal is to limit the amount of time that the transistor is in the saturation region in order to limit the charge that will be lost. To keep the transistor completely out of the saturation region, the threshold voltage could be raised until it equals the value of the input DC source on the oscillator. Thus, the transistor would be completely in the linear region and conducting on only half of the cycle when 푉퐷푆 is below the battery voltage. The power consumption of this transistor could be determined using the equations below. The gate voltage is described as

−휋푡 푉 = 푉 푐표푠 ( ) + 푉 (5.1) 1 퐵퐴푇 푇 퐵퐴푇 and the drain voltage as

휋푡 푉 = 푉 푐표푠 ( ) + 푉 . (5.2) 2 퐵퐴푇 푇 퐵퐴푇

푉퐵퐴푇 is the battery or DC source that is applied to the oscillating circuit.

The current through the transistor in the linear region is found in

휋푡 푉 푉 (푐표푠 ( ) + 1)] (5.3) 퐵퐴푇 푇 푇

The power consumed can be shown as

1 푇⁄ 푃 = ∫ 2 퐼 푉 푑푡 . (5.4) 퐴푉퐺푙 푇 0 퐷퐿 퐷푆

When substituting Equations 5.3 and 5.4 into Equation 5.5, the result yields

푇⁄ −휋푡 훽푊 1 −2휋푡 −휋푡 푃 = ∫ 2 (푉 푐표푠 ( ) + 푉 ) ( ) [푉2 ( 푐표푠 ( ) + 푐표푠 ( ) + 퐴푉퐺푙 0 퐵퐴푇 푇 퐵퐴푇 2퐿 퐵퐴푇 2 푇 푇

휋푡 1 2휋푡 −2휋푡 휋푡 푐표푠 ( ) − 푐표푠 ( ) − 2푐표푠 ( )) − 푉 푉 (푐표푠 ( ) + 1)] 푑푡 . (5.5) 푇 2 푇 푇 퐵퐴푇 푇 푇

All the cosine terms will integrate to 0 since sin(n휋)=0. Therefore, the average power consumed by the clock circuit is

푇⁄ 훽푊 푃 = ∫ 2 ( 푉 푉 )푉 푑푡. (5.6) 퐴푉퐺푙 0 2퐿 퐵퐴푇 푇 퐵퐴푇

After integration, the result is

훽푊 푃 = 푉 푉2 . (5.7) 퐴푉퐺푙 푇 퐵퐴푇 4퐿

The resistor and the capacitor are left in the circuit. The power in the resistor can be found by using the circuit shown in Figure 5.27 below.

Figure 5.27 Resistor Power Calculation Circuit

If V1 is modeled as a ramp function, this would align with the derivation from Chapter 1. Therefore, the average power consumed in this circuit can be

1 found from Equation 1.4 and multiplied by . The result is 푇

푅퐶 푅퐶 푅퐶 −푇⁄ 푃 = 퐶푉2 (1 − + 푒 푅퐶) . (5.8) 퐴푉퐺푅 푇2 1 푇 푇

If the small saturation region is ignored, then the total consumed power can be found by

푃푇푂푇퐴푉퐺 = 2 푃퐴푉퐺퐿 + 푁 푃퐴푉퐺퐺퐴푇퐸 + 2 푃퐴푉퐺푅 (5.9) where N represents the number of gates in the circuit.

Chapter – 6

POWER CLOCK FOR SMALLER TRANSISTORS

6.1 Input Power Clock for Smaller Transistors

Since the transistors discussed in the previous chapter are smaller in size, the input clock for those transistors is different from the ones that would be used for normal transistors. For smaller transistors, the clock circuit would be like that shown in Figure 6.1. In this circuit, we have added additional resistors: R2, R3, and R5 the clock signal amplitude shrink over time and gives an output like the output of a half-wave rectifier. Two clock signals are used, both of which are 180 degrees out of phase. Figures 6.2 and 6.3 show the input and output of the power clock signals, respectively.

Figure 6.1 Input Power Clock for Smaller Transistors

Figure 6.2 Input Power Clock Signals

Figure 6.3 Output Power Clock Signals

6.2 High Speed Comparator for Smaller Transistors

Normal transistors use a comparator called TLV2352, but this comparator does not work at the higher frequencies at which smaller transistors can operate.

For frequencies, higher than 1MHz, another comparator is developed, which is shown in Figure 6.4 below.

Figure 6.4 High Speed Comparator for Small Transistors

The comparator input is connected to the V1 signal. This side of the clocking circuit has the least number of transistors connected to it. The two resistors R1 and R2 are used to adjust the width of the clock signal. By placing R2 closer to R1, the time is shortened. When both resistors are lowered, the signal

level of the clock input is lower to produce a high output. The output is shown in

Figure 6.5.

Figure 6.5 Comparator Output Signal

Chapter – 7

CONCLUSIONS

Three tasks were accomplished in this thesis. First, the adiabatic primitives— including NOT, NOR-OR, NAND-AND, and XNOR-XOR—were constructed and simulated. These reflected the new design based on the circuit shown in [1]. Second, the same adiabatic cells were constructed, but the transistors used in this work were small in length, which again proved that the output would be more efficient and the power consumption would be lowered compared to normal transistors. Third, a power clock was constructed for smaller transistors and high-speed comparator circuits. These circuits could be used in identifying the input power signals given to the transistors.

Chapter 4 shows the detailed schematics, including the simulated input and output of each gate and the voltage power consumption of a long-channel transistor. Chapter 5 covers the detailed schematics of all the adiabatic gates, which uses a smaller-length transistor. Since the technology is emerging rapidly, the use of transistors of smaller lengths would be more useful in obtaining accurate outputs. This chapter also covers the voltage power consumption of short-channel transistors. Two different shorter lengths were taken into consideration, revealing that the MOSFET, with a length of 22 nm, was the optimum selection. Chapter 6

covers the power clock of smaller transistors, which could be extended for further work.

7.1 SUGGESTIONS FOR FURTHER RESEARCH

This study could be expanded to include complex logic blocks to form different multiplexers and to form a Field Programmable Gate Array. The dynamic RAM cell used in this thesis had a 4T structure, which could be modified.

A SDRAM cell could be used in its place, which would reduce further power and the excess need of the transistor. The same research could be done in Finfet using

LTSpice. Due to the unavailability of a library file in LTSpice, this thesis could not complete that task.

Appendix : A

TRANSISTOR MODELS (LTSPICE)

* 180nm NMOS SPICE Parameters (normal one)

.model NMOS NMOS +Level = 49

+Lint = 4.e-08 Tox = 4.e-09 +Vth0 = 0.3999 Rdsw = 250

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1 +Xj= 6.0000000E-08 Nch= 5.9500000E+17 +lln= 1.0000000 lwn= 1.0000000 wln= 0.00 +wwn= 0.00 ll= 0.00 +lw= 0.00 lwl= 0.00 wint= 0.00 +wl= 0.00 ww= 0.00 wwl= 0.00 +Mobmod= 1 binunit= 2 xl= 0 +xw= 0 binflag= 0 +Dwg= 0.00 Dwb= 0.00

+K1= 0.5613000 K2= 1.0000000E-02 +K3= 0.00 Dvt0= 8.0000000 Dvt1= 0.7500000 +Dvt2= 8.0000000E-03 Dvt0w= 0.00 Dvt1w= 0.00 +Dvt2w= 0.00 Nlx= 1.6500000E-07 W0= 0.00 +K3b= 0.00 Ngate= 5.0000000E+20

+Vsat= 1.3800000E+05 Ua= -7.0000000E-10 Ub= 3.5000000E-18 +Uc= -5.2500000E-11 Prwb= 0.00 +Prwg= 0.00 Wr= 1.0000000 U0= 3.5000000E-02 +A0= 1.1000000 Keta= 4.0000000E-02 A1= 0.00 +A2= 1.0000000 Ags= -1.0000000E-02 B0= 0.00 +B1= 0.00

+Voff= -0.12350000 NFactor= 0.9000000 Cit= 0.00 +Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00 +Eta0= 0.2200000 Etab= 0.00 Dsub= 0.8000000

+Pclm= 5.0000000E-02 Pdiblc1= 1.2000000E-02 Pdiblc2= 7.5000000E-03 +Pdiblcb= -1.3500000E-02 Drout= 1.7999999E-02 Pscbe1= 8.6600000E+08 +Pscbe2= 1.0000000E-20 Pvag= -0.2800000 Delta= 1.0000000E-02 +Alpha0= 0.00 Beta0= 30.0000000

+kt1= -0.3700000 kt2= -4.0000000E-02 At= 5.5000000E+04 +Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1= -3.3473000E-19 +Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00

+Cj= 0.00365 Mj= 0.54 Pb= 0.982 +Cjsw= 7.9E-10 Mjsw= 0.31 Php= 0.841 +Cta= 0 Ctp= 0 Pta= 0 +Ptp= 0 JS=1.50E-08 JSW=2.50E-13

+N=1.0 Xti=3.0 Cgdo=2.786E-10 +Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2 +NQSMOD= 0 Elm= 5 Xpart= 1 +Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886 +Cf= 1.069e-10 Clc= 0.0000001 Cle= 0.6 +Dlc= 4E-08 Dwc= 0 Vfbcv= -1

* * Predictive Technology Model Beta Version * 180nm PMOS SPICE Parametersv (normal one) *

.model PMOS PMOS +Level = 49

+Lint = 3.e-08 Tox = 4.2e-09 +Vth0 = -0.42 Rdsw = 450

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1 +Xj= 7.0000000E-08 Nch= 5.9200000E+17 +lln= 1.0000000 lwn= 1.0000000 wln= 0.00 +wwn= 0.00 ll= 0.00 +lw= 0.00 lwl= 0.00 wint= 0.00 +wl= 0.00 ww= 0.00 wwl= 0.00 +Mobmod= 1 binunit= 2 xl= 0.00 +xw= 0.00 +binflag= 0 Dwg= 0.00 Dwb= 0.00

+ACM= 0 ldif=0.00 hdif=0.00 +rsh= 0 rd= 0 rs= 0 +rsc= 0 rdc= 0

+K1= 0.5560000 K2= 0.00 +K3= 0.00 Dvt0= 11.2000000 Dvt1= 0.7200000 +Dvt2= -1.0000000E-02 Dvt0w= 0.00 Dvt1w= 0.00 +Dvt2w= 0.00 Nlx= 9.5000000E-08 W0= 0.00 +K3b= 0.00 Ngate= 5.0000000E+20

+Vsat= 1.0500000E+05 Ua= -1.2000000E-10 Ub= 1.0000000E-18 +Uc= -2.9999999E-11 Prwb= 0.00 +Prwg= 0.00 Wr= 1.0000000 U0= 8.0000000E-03 +A0= 2.1199999 Keta= 2.9999999E-02 A1= 0.00 +A2= 0.4000000 Ags= -0.1000000 B0= 0.00 +B1= 0.00

+Voff= -6.40000000E-02 NFactor= 1.4000000 Cit= 0.00 +Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00 +Eta0= 8.5000000 Etab= 0.00 Dsub= 2.8000000

+Pclm= 2.0000000 Pdiblc1= 0.1200000 Pdiblc2= 8.0000000E-05 +Pdiblcb= 0.1450000 Drout= 5.0000000E-02 Pscbe1= 1.0000000E-20 +Pscbe2= 1.0000000E-20 Pvag= -6.0000000E-02 Delta= 1.0000000E-02 +Alpha0= 0.00 Beta0= 30.0000000

+kt1= -0.3700000 kt2= -4.0000000E-02 At= 5.5000000E+04 +Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1= -3.3473000E-19

+Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00

+Cj= 0.00138 Mj= 1.05 Pb= 1.24 +Cjsw= 1.44E-09 Mjsw= 0.43 Php= 0.841 +Cta= 0.00093 Ctp= 0 Pta= 0.00153 +Ptp= 0 JS=1.50E-08 JSW=2.50E-13 +N=1.0 Xti=3.0 Cgdo=2.786E-10 +Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2 +NQSMOD= 0 Elm= 5 Xpart= 1 +Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886 +Cf= 1.058e-10 Clc= 0.0000001 Cle= 0.6 +Dlc= 3E-08 Dwc= 0 Vfbcv= -1

Appendix : B

45nm MOS SPICE Parameters .model nmos nmos level = 54

+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 +permod = 1 acnqsmod= 0 trnqsmod= 0

+tnom = 27 toxe = 1.8e-009 toxp = 1.5e-009 toxm = 1.8e-009 +dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 0 +ll = 0 wl = 0 lln = 1 wln = 1 +lw = 0 ww = 0 lwn = 1 wwn = 1 +lwl = 0 wwl = 0 xpart = 0 toxref = 1.8e-009

+vth0 = 0.62261 k1 = 0.4 k2 = 0 k3 = 0 +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 1.4e-008 +ngate = 1e+023 ndep = 3.24e+018 nsd = 2e+020 phin = 0 +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 +voff = -0.13 nfactor = 1.6 eta0 = 0.0125 etab = 0 +vfb = -0.55 u0 = 0.049 ua = 6e-010 ub = 1.2e-018 +uc = 0 vsat = 130000 a0 = 1 ags = 0 +a1 = 0 a2 = 1 b0 = 0 b1 = 0 +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007

+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 +rsh = 5 rdsw = 210 rsw = 80 rdw = 80 +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 +eigbinv = 1.1 nigbinv = 3 aigc = 0.015211 bigc = 0.0027432 +cigc = 0.002 aigsd = 0.015211 bigsd = 0.0027432 cigsd = 0.002 +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 +xrcrg1 = 12 xrcrg2 = 5

+cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 +moin = 15 noff = 0.9 voffcv = 0.02

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 +at = 33000

+fnoimod = 1 tnoimod = 0

+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 +xtis = 3 xtid = 3

+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 +dwj = 0 xgw = 0 xgl = 0

+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

.model pmos pmos level = 54

+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 +permod = 1 acnqsmod= 0 trnqsmod= 0

+tnom = 27 toxe = 1.82e-009 toxp = 1.5e-009 toxm = 1.82e-009 +dtox = 3.2e-010 epsrox = 3.9 wint = 5e-009 lint = 0 +ll = 0 wl = 0 lln = 1 wln = 1 +lw = 0 ww = 0 lwn = 1 wwn = 1 +lwl = 0 wwl = 0 xpart = 0 toxref = 1.82e-009

+vth0 = -0.587 k1 = 0.4 k2 = -0.01 k3 = 0 +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.4e-008 +ngate = 1e+023 ndep = 2.44e+018 nsd = 2e+020 phin = 0 +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 +voff = -0.126 nfactor = 1.8 eta0 = 0.0125 etab = 0 +vfb = 0.55 u0 = 0.021 ua = 2e-009 ub = 5e-019 +uc = 0 vsat = 90000 a0 = 1 ags = 1e-020 +a1 = 0 a2 = 1 b0 = 0 b1 = 0 +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12

+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 +rsh = 5 rdsw = 250 rsw = 75 rdw = 75 +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 +eigbinv = 1.1 nigbinv = 3 aigc = 0.0097 bigc = 0.00125 +cigc = 0.0008 aigsd = 0.0097 bigsd = 0.00125 cigsd = 0.0008 +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 +xrcrg1 = 12 xrcrg2 = 5

+cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 +moin = 15 noff = 0.9 voffcv = 0.02

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 +at = 33000

+fnoimod = 1 tnoimod = 0

+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 +xtis = 3 xtid = 3

+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 +dwj = 0 xgw = 0 xgl = 0

+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

Appendix : C

22nm MOS SPICE Parameters

.model nmos nmos level = 54

+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 +permod = 1 acnqsmod= 0 trnqsmod= 0

+tnom = 27 toxe = 1.4e-009 toxp = 1.1e-009 toxm = 1.4e-009 +dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 0 +ll = 0 wl = 0 lln = 1 wln = 1 +lw = 0 ww = 0 lwn = 1 wwn = 1 +lwl = 0 wwl = 0 xpart = 0 toxref = 1.4e-009

+vth0 = 0.68858 k1 = 0.4 k2 = 0 k3 = 0 +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 7.2e-009 +ngate = 1e+023 ndep = 5.5e+018 nsd = 2e+020 phin = 0 +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 +voff = -0.1092 nfactor = 1.6 eta0 = 0.0105 etab = 0 +vfb = -0.55 u0 = 0.035 ua = 6e-010 ub = 1.2e-018 +uc = 0 vsat = 170000 a0 = 1 ags = 0 +a1 = 0 a2 = 1 b0 = 0 b1 = 0 +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5

+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 +fprout = 0.2 pdits = 0.01 pditsd = 0.23 pditsl = 2300000 +rsh = 5 rdsw = 180 rsw = 75 rdw = 75 +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 +eigbinv = 1.1 nigbinv = 3 aigc = 0.015211 bigc = 0.0027432 +cigc = 0.002 aigsd = 0.015211 bigsd = 0.0027432 cigsd = 0.002 +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 +xrcrg1 = 12 xrcrg2 = 5

+cgso = 6.5e-011 cgdo = 6.5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 +moin = 15 noff = 0.9 voffcv = 0.02

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 +at = 33000

+fnoimod = 1 tnoimod = 0

+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 +xtis = 3 xtid = 3

+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 +dwj = 0 xgw = 0 xgl = 0

+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

.model pmos pmos level = 54

+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 +permod = 1 acnqsmod= 0 trnqsmod= 0

+tnom = 27 toxe = 1.4e-009 toxp = 1.08e-009 toxm = 1.42e-009 +dtox = 3.2e-010 epsrox = 3.9 wint = 5e-009 lint = 0 +ll = 0 wl = 0 lln = 1 wln = 1 +lw = 0 ww = 0 lwn = 1 wwn = 1 +lwl = 0 wwl = 0 xpart = 0 toxref = 1.42e-009

+vth0 = -0.63745 k1 = 0.4 k2 = -0.01 k3 = 0 +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 7.2e-009 +ngate = 1e+023 ndep = 4.4e+018 nsd = 2e+020 phin = 0 +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 +voff = -0.09 nfactor = 1.8 eta0 = 0.0105 etab = 0 +vfb = 0.55 u0 = 0.011 ua = 2e-009 ub = 5e-019 +uc = 0 vsat = 170000 a0 = 1 ags = 1e-020 +a1 = 0 a2 = 1 b0 = 0 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 +rsh = 5 rdsw = 230 rsw = 72.5 rdw = 72.5 +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 +eigbinv = 1.1 nigbinv = 3 aigc = 0.0097 bigc = 0.00125 +cigc = 0.0008 aigsd = 0.0097 bigsd = 0.00125 cigsd = 0.0008 +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 +xrcrg1 = 12 xrcrg2 = 5

+cgso = 6.5e-011 cgdo = 6.5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 +moin = 15 noff = 0.9 voffcv = 0.02

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 +at = 33000

+fnoimod = 1 tnoimod = 0

+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 +xtis = 3 xtid = 3

+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 +dwj = 0 xgw = 0 xgl = 0

+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

Appendix : D

TRANSISTOR MODELS PSPICE

.model MND1 NMOS Level=2 LD=0.15u TOX=200E-10 NSUB=5.37E+15 VTO=0.74 KP=8.0E-05

GAMMA=0.54 PHI=0.6 U0=656 UEXP=0.157 UCRIT=31444 DELTA=2.34 VMAX=55261 XJ=0.25U

LAMBDA=0.037 NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00 CGDO=4.34E-10

CGSO=4.3E-10 CJ=0.0003 MJ=0.66 CJSW=8.0E-10 MJSW=0.24 PB=0.58 l=0.7u w=1.2u

.model MND2 NMOS Level=2 LD=0.15u TOX=200E-10 NSUB=5.37E+15 VTO=0.74 KP=8.0E-05

GAMMA=0.54 PHI=0.6 U0=656 UEXP=0.157 UCRIT=31444 DELTA=2.34 VMAX=55261 XJ=0.25U

LAMBDA=0.037 NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00 CGDO=4.34E-10

CGSO=4.3E-10 CJ=0.0003 MJ=0.66 CJSW=8.0E-10 MJSW=0.24 PB=0.58 l=0.7u w=9u

.model MbreakND NMOS Level=2 LD=0.15u TOX=200E-10 NSUB=5.37E+15 VTO=0.74 KP=8.0E-05

GAMMA=0.54 PHI=0.6 U0=656 UEXP=0.157 UCRIT=31444 DELTA=2.34 VMAX=55261 XJ=0.25U

LAMBDA=0.037 NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00 CGDO=4.34E-10

CGSO=4.3E-10 CJ=0.0003 MJ=0.66 CJSW=8.0E-10 MJSW=0.24 PB=0.58 l=0.7u w=2.2u

.model MPSER PMOS Level=2 LD=0.15u TOX=200E-10 NSUB=4.37E+15 VTO=-0.74 KP=2.7E-05

GAMMA=0.58 PHI=0.6 U0=262 UEXP=0.324 UCRIT=65720 DELTA=1.79 VMAX=25694 XJ=0.25U

LAMBDA=0.061 NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=121 CGDO=4.34E-10

CGSO=4.3E-10 CJ=0.0005 MJ=0.51 CJSW=1.35E-10 MJSW=0.24 PB=0.58 l=0.7u w=15u

.model MbreakPD PMOS Level=2 LD=0.15u TOX=200E-10 NSUB=4.37E+15 VTO=-0.74 KP=2.7E-05

GAMMA=0.58 PHI=0.6 U0=262 UEXP=0.324 UCRIT=65720 DELTA=1.79 VMAX=25694 XJ=0.25U

LAMBDA=0.061 NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=121 CGDO=4.34E-10

CGSO=4.3E-10 CJ=0.0005 MJ=0.51 CJSW=1.35E-10 MJSW=0.24 PB=0.58 l=0.7u w=2.2u

Appendix : E

BSIM4v4.7 MOSFET Model

BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical effects into sub-100nm regime. The continuous scaling of minimum feature size brought challenges to compact modeling in two ways: One is that to push barriers in making transistors with shorter gate length, advanced process technologies are used such as non-uniform substrate doping. the second is its opportunities to RF applications.

To meet these challenges BSIM3 has the following major improvements and additions over BSIM3v3: (1) an accurate new model of the intrinsic input resistance for RF and high frequency analog and high speed digital applications.

(2) flexible substrate resistance network for RF modeling; (3) a new accurate channel thermal noise model and a noise partition for the induced gate noise. (4) a non-quasi-static(NQS) model that is consistent with the Rg-based RF model for multiple layer gate dielectrics; (6) a comprehensive and versatile geometry dependent parasitic model for various source/drain connections and multi-finger devices; (7) improved model for steep vertical retrograde doping profiles; (8) better model for pocket implanted devices in Vth, bulk charge effect model and Rout; (9) asymmetrical and bias-dependent source/drain resistance, either internal or

external to the intrinsic MOSFET at the user’s discretion; (10) acceptance of anyone of the electrical, physical gate oxide thickness or equivalent oxide thickness as the model input at the user’s choice in a physically accurate manner;

(11) the quantum mechanical charge layer thickness model for both IV and CV;

(12) a more accurate mobility model for predictive modeling (13) a improved gate induced drain/source leakage (GIDL/GISL) current model considering the work function difference between drain/source and gate (14) an improved unified flicker noise model, which is smooth over all bias regions and considers the bulk charge effect; (15) different diode IV and CB chrematistics for source and drain junctions;

(16) junction diode breakdown with or without current limiting; (17) dielectric constant of the gate dielectric as a model parameter; (18) A new scalable stress effect model for proves induced stress effect; device performance becoming thus a function of the active area geometry and the location of the device in the active area; (19) A unified current-saturation model that includes all mechanisms of the current saturation velocity saturation, velocity overshoot and source end velocity limit;(20) A new temperature model format that allows convenient prediction of the temperature effect on the saturation velocity, mobility and S/D resistances; (21)

A improved material model that is suitable to describe non-SiO2 gate insulator, non-poly-Si gate and non-Si-channel; (22) A new threshold voltage definition introduced C-V model to improve sub-threshold fitting; (23) an improved model

predicts well the mobility behavior in high k/metal gate structure; (24) a width dependent trap assistant tunneling model is introduced to describe the current density enhancement in narrow device; (25) Correlation Coefficient of fate and drain noise implemented in holistic noise model (tnoiMod=2); (26) The new thermal noise model shows much better physical behavior in all bias conditions

(tnoiMod=3); (27) Improved DIBL/ROUT model.

Spice Simulator

Simulation Program with Integrated Circuit Emphasis (SPICE).

SPICE is a computer program that accepts a circuit schematic as input and outputs the simulated circuit behavior. The simulation can be performed under the nonlinear dc, nonlinear transient and linearized ac operating conditions. The circuit may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, dependent sources, lossless and lossy transmission lines, switches, uniform distributed RC lines, and various semiconductor devices including MOSFETs (metal oxide semiconductor field-effect transistors). The original SPICE program, SPICE1, was developed at University of California,

Berkeley, and released for public use in May, 1972. By 1975, after the next major release, called SPICE2, SPICE was in widespread use and adopted by most integrated circuit manufacturers. SPICE2 was written in Fortran (a high-level

computer programming language used especially for scientific computation). With the advent of UNIX computers in the 1980s it became increasingly obvious that

SPICE would benefit from the C-shell utilities that come with UNIX computers.

This prompted the rewriting of SPICE program in the C-language, although the basic algorithms remain largely intact. The revised SPICE program, called

SPICE3, was released in public domain in March, 1985.

The free distribution by Berkeley is a key factor contributing to the universal acceptance of SPICE. Accompanying with this free launch, however, is the inevitable lack of “product” support. Several large companies have written their own version of the circuit simulation program to better serve their companies’ particular interests. One notable proprietary SPICE, which pioneered the use of charge-based device model as the solution to the charge non-conservation problem, is the TI-SPICE, still in use in Texas Instruments. In a charge-based approach, the charge (instead of voltage) becomes the state variable in calculating the transient behavior of MOSFET. This ensured charge conservation . There are also several developers who developed commercial versions of the SPICE according to the need of small companies without a CAD(Computer Aided Design) group of their own. One of the commercial version is HSPICE. It is a robust SPICE program combined with an excellent graphic interactive interface. HSPICE is used extensively on UNIX-based workstations. Another example is PSPICE, introduced

in 1984, which runs on PC and Macintosh platforms (but a significantly slower speed than UNIX-based SPICE programs). Because of the proliferation of the personal computers, this PC based SPICE program has attracted many users and

SPICE software had a major leap and played a major role in introduction of another version of SPICE as SPICE2. These various versions of SPICE program introduce improvements in user interfaces, user support, numerical convergence, and device modeling. Although the non-Berkeley versions contain several differences in the implementation of the numerical routines or device models, they nonetheless retain the original SPICE’s programming structure. There are some notable SPICE versions that are being explained as follows,

• Berkeley SPICE The original SPICE. This is the first ever version of

SPICE that has been used in simulations. It can be run on UNIX platforms and

the most newer versions can also be run on Windows and Mac OS (Operating

Systems). The latest version of SPICE supports BSIM4v4.7.

• HSPICE Created by meta software and it is now owned by Avant.

It was popular within UNIX-based users, and known for it’s interactive user

interfaces. BSIM2, BSIM3V2, BSIM3v3 and BSIM4v4.7 are implemented as

levels 39, 47, 49 and 54 respectively.

• LT SPICE This is a simple software used to import third party

models. The importance of this software is that it can be used in all linearized

simulations and it is widely used in Windows OS and Mac OS. The newer

version of LTSPICE IV supports BSIM4v4.7 and are implemented as level

54.LT SPICE was formerly called as switcher CAD and it is now maintained by

Mike Engelhardt.

• PSPICE PC-based version SPICE created by Micro-Sim, which was

recently acquired by Orcad. It has evolved to support BSIM models as well as

complete IC models.

Now there are almost 100,000 copies of SPICE in active use at universities and some trial versions can be found in the internet. There are currently about 20 companies provide SPICE products and supports commercially. As far now we have discussed various derivatives of the Berkeley SPICE, we did not make a clear distinction between the SPICE simulator and the SPICE device model. Together, these two parts form the overall SPICE program. The SPICE simulator is the mathematical engine of SPICE, consisting of several basic SPICE subroutines to perform numerical analyses. One exemplar numerical subroutine is matrix inversion, which is the backbone of the algorithm to solve n linearly independent equations with n unknowns. This routine is combined with Newton-Raphson iteration technique, allows the solution of non-linear equations which govern static nodal voltages and the branch currents of a given circuit.

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Another basic SPICE subroutine solves ordinary differential equations. This type of routine is in a transient analysis involving time as the independent variable.

The transient analysis is a one-dimensional problem in which the voltages and currents are functions of time only. Other simulation programs, notably

PSICES(Stanford University CAD program). Or its commercial version –

MEDICI, which simultaneously solve the Poisson equation and current continuity equations, address four-dimensional problems involving space (x, y, z) and time (t) as the independent variables. As far as numerical analysis is concerned , it is inherently more difficult to solve multi-dimensional partial differential equations than a one-dimensional ordinary differential equation. Therefore, SPICE simulation of a circuit is generally faster and enjoys less convergence problems than PISCES simulation of a device. If the simulation results of SPICE simulation deviate from PISCES we conclude that either the SPICE model used in the simulation is imperfect or the model parameters are not properly extracted.

Spice Model:

The second part of a SPICE program is the device model. There can be many semiconductor devices in a circuit, such as a diode, a bipolar transistor, or a capacitor. Since this thesis is based on MOSFET, we shall concentrate on the

MOSFET device in particular. A model mathematically represents the device

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characteristics under various bias conditions. In dc and ac analyses, the inputs of the device model are drain-to-source, gate-to-source, bulk-to-source and the device temperature. The outputs are the various terminal currents. In a transient analysis we can think that the SPICE model accepts time derivative of the bias voltages in addition to the absolute values of the biases themselves at an instant of time. The output of the SPICE model is then the terminal currents at the particular instant of time. If a noise analysis is specified in the input deck, the SPICE model also computes the noise voltages at a particular set of bias condition and frequency.

We have mentioned several SPICE simulators, including Berkeley SPICE,

HSPICE, LTSPICE and PSPICE. They are not complete without SPICE models.

Some notable SPICE models for MOSFET are explained below.

• Level 1 Also known as the Shichman-Hodges model, this is the original

model since the dawn of Berkeley SPICE. The model equations are simple,

resembling those used in some textbooks, and are applicable mainly to long-

channel devices. The C-V portion of the model is the Meyer model. Which

Is not a charge-conserved model.

• Level 2 This model addresses several short-channel effects such as the

velocity saturation. However, the mathematical implementation of the model

was complicated leading to many convergence problems. For C-V

calculation, either the Meyer model of Level 1 or the Ward-Dutton model

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can be used. The Ward-Dutton model is a charge-conserved model, which

forms the backbone of all present models.

• Level 3 This semi-empirical model is regarded as a simplified version

of level 2. This model has proven to be robust and is popular for digital

circuit design. However, this model is not very scalable. Discontinuities in

the first derivative of the drain current exist.

• BSIM It is the Berkeley Short-Channel IGFET Model, sometimes

referred to as Level 4. The model places less emphasis on the exact physical

formulation of the device, but instead relies on empirical parameters and

polynomial equations to handle various physical effects. This generally leads

to improved circuit simulation considered to previous models, although its

accuracy degrades in sub-micron FETs. Furthermore, the polynomial

equations can behave poorly causing negative output conductance and

convergence problems.

• HSPICE Level 28 This model is developed by Meta-Software which is like

BSIM. However, with proper modification in binning strategy and

mathematical transcription region, Level 28 has been made suitable for

analog design and remains popular to date.

• BSIM2 This is an extension of BSIM, with comprehensive

modifications which make it suitable for analog circuit design. Although

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BSIM2 improves upon BSIM in terms of model accuracy as well as

convergence behavior in circuit simulation, it still breaks the transistor

operation into several-regions. This leads to discontinuity in the first

derivative in I-V and C-V characteristics, a result that can cause numerical

problems in simulation.

• BSIM3 With the help of smoothing functions, BSIM3 adopts a

single-equation to describe device characteristics in various operating

regions. This eliminates the discontinuity in I-V and C-V characteristics.

BSIM3 has evolved in three versions as BSIM3v1, BSIM3v2, BSIM3v3.

But the first two has many mathematical problems so they are replaced by

third version. The third version itself has several variations including

BSIM3v3.1, BSIM3v3.2 and BSIM3v3.3. These variations of BSIM3v3

have minor differences, and have been demonstrated for accurate use in

180nm technologies.

• Model 9 MOS Model 9 is the primary non-Berkeley model

available for public use. The model also employs some function to employ

continuity inn device characteristics. The model is accurate for sub-quarter

micron technologies and exhibits good behaviors in circuit simulation.

Model 9 is probably as good as BSIM3. However, companies opted for

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BSIM3 because of its accuracy and it was not obvious whether there were

intellectual property issues associated with MOS9.

• EKV Model This model is unique in its use of bulk-referencing,

while all other mentioned model employs source -referencing. This

fundamental philosophical change allows the EKV model a greater hope of

fundamentally eliminating the asymmetry problems unavoidable in source-

referencing models. Despite its adoption of a more physical modeling

approach, the EKV model is not popular, partly because of its relatively late

arrival compared to other models and the accuracy of BSIM made all the

companies to use that model.

• BSIM4 The newest addition to the BSIM family, made in public

in the year 2000. BSIM4 offers several improvements over BSIM3, not just

in the traditional I-V modeling of the intrinsic transistor, but also in the

transistor’s noise modeling and in the incorporation of extrinsic parasitic.

BSIM4, is also known as level 14 model. It has 4 versions as BSIM4v1,

BSIM4v2, BSIM4v3 and BSIM4v4. There are several variations in the

version BSIM4v4 that has almost 7 variations BSIM4v4.7 and the newest

one is BSIM4v4.8 this one is yet to be released. In this thesis we have used

BSIM4v4.7

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Some SPICE programs are basically known for their SPICE simulators. For example, PSPICE is well known because its SPICE simulators run on the PC platform. PSPICE’s SPICE models for MOSFETs are those public domain models created by Berkeley over the years. However, occasionally the SPICE model is well known as its SPICE simulator. Considering LTSpice this is well known because of its flexibility to muse third party models and all the non-linear and linear simulations can be done in this simulator. Take HSPICE, for example. Its

Level 28 MOSFET model was introduced at a time when there was no good analog model. This model is used as a vehicle to gain widespread acceptance of

HSPICE simulator.

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REFERENCES

[1]. Y. Liang, K. Gopalakrishnan, P. B. Griffin and J. D. Plummer, “From DRAM to SRAM with a novel siege-based negative differential resistance(NDR) device”,

IEEE transactions on IEDM, 2005, pp 959-962.

[2]. J. Hu, Ling Wang and Huiying Dong, “Interface circuits between adiabatic and standard CMOS circuits”, IEEE transactions, vol.no. 07, 2007, pp 562-565.

[3]. Feng Wang and Mounir Hamdi, “Matching the speed gap between SRAM and

DRAM”, IEEE transactions on ICHPSR 2008, pp 104-109.

[4]. S. Lee, J. Jung and C. M. Kyung, “Hybrid cache architecture replacing SRAM cache with future memory technology”, IEEE transactions, 2012, pp-2481-2484.

[5]. Cagla Cakir, Mudit Bhargava and Ken Mai, “6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS”, IEEE transactions, 2012, pp. 1-4.

[6]. Monika Gautam, Uma Nirmal and Raina Jain, “Low power sequential circuits using improved adiabatic logic in 180nm CMOS processes”, IEEE transactions on

RAINS, 2016, pp 1-4.

[7]. K. Roy and S. C Prasad, Low-Power CMOS VLSI Circuit Design, John Wiley and Sons, Inc., New York, 2000. ISBN: 978-0471114888.

107

[8]. Sakshi Goyal, Gurvinder Singh and Pushpinder Sharma, “Variation of power dissipation for Adiabatic CMOS and Conventional CMOS digital circuits”, IEEE transactions on ICECS, vol. no.15, 2015, pp 162-166.

[9]. Jianping Hu, Tifeng Xu and Junjun Yu, “Low power dual transmission Gate

Adiabatic logic circuits and design of SRAM”, IEEE transactions vol.no.46, 2004, pp. 565-568.

[10]. S. M Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis and

Design, McGraw Hill, New York, 2003. ISBN: 978-0072460537.

[11]. J. C. Koob, S. A. Ung, B. F. Cockburn and D. G. Elliot, “Design and characterization of multilevel DRAM”, IEEE vol.no. 10, 2010, pp.1583-1596.

[12]. Suhwan Kim and Marios C. Papaefthymiou, “True-single phase Adiabatic circuitry”, IEEE Transactions on Very Large Scale Integration Systems, vol.no.9,

2001, pp.52-63.

[13]. Vojin G Oklobdzija, Dragan Maksimovic and Fengcheng Lin, “Pass

Transistor Adiabatic Logic Using Single Power Clock Supply”, IEEE Transactions on Circuits and Systems-II vol.no.44, 1997, pp.842-846.

[14]. Dhirajkumar S. Bhutada, “Design of Low Voltage Flipflop based on

Complementary Pass Transistor Adiabatic Logic Circuit”, IEEE Transactions on

WCFTR, vol.no.9, 2016, pp 1-5.

108

[15]. Yatin Gupta and Trailokya Nath Sasamal, “Implementation of Reversible

Logic Gates using Adiabatic Logic”, IEEE Transactions on PCITC, vol.no.59,

2015, pp 1-4.

[16]. Timothy Brian Medley and F.D. Ho, “Field Programmable Gate Array

Complex Logic Block in Adiabatic form”, a Master’s thesis work submitted on

March 2006.

[17]. Jan M. Rabaey, Digital Integrated Circuits Prentice Hall electronics and VLSI series, a design perspective, Prentice Hall Inc., New Jersey, 1996.

[18]. Prateek Asthana and Sangeeta Mangesh “Performance Comparison of 4T, 3T and 3T1D DRAM Cell design on 32nm Technology”, CSIT transactions on Very

Large Scale Integration Systems, 2014, pp 121-133.

[19]. Y. Kihara et.al. “ A 16M SRAM with improved characteristics using DRAM technology”, IEEE, 2005, pp 17-20.

[20]. SPICE simulator and SPICE Model citeseerx.ist.psu.edu.

[21]. M. R. Hunt, C. Mitchell, C. L. McCartney and F. D. Ho, “MFSFET two bit

1T1C DRAM memory design and empirical data”, IEEE vol.no.52, 2016, pp 477-

479.

109

[22]. Laxmi Singh and Ajay Somkuwar “4T DRAM based on Self-controllable

Voltage level technique for low leakage power in VLSI”, International Journal of

Emerging Technologies in Computational and Applied Sciences, 2012, pp 233-

237.

[23]. S. Ganapathy, R. Canal, D. Alexandrescu, E. Costenaro, A. Gonzalez and A.

Rubio, “A Novel Variation -Tolerant 4T DRAM Cell with Enhanced Soft-Error

Tolerance”, IEEE vol.no.12, 2012, pp 472-477.

[24]. R. Giterman, A. Teman, L. Atias and A. Fish, “A Soft Error Tolerant 4T Gain

Cell featuring a parity column for Ultra- Low Power Applications”, IEEE vol.no.15, 2015, pp 1-2.

[25]. W. Zhang et.al., “Variation aware performance analysis of gain cell embedded DRAMs”, ISLPED, 2010.

[26]. Peter Bukelani Musiiwa and Shyam Akashe, “Comparative Evaluation of different 3T DRAM cells at 45nm”, IEEE Transaction on ICCN vol.no.15, 2015, pp 77-83.

[27]. Ambrish Mudgal, Shyam Akashe and Shyam Babu Singh, “Power Analysis of 3T DRAM cell using FinFET at 45nm Process Technology” , IEEE

Transactions on ICT, 2012, pp 555-560.

110

[28]. C. M. Gerik, Michael A. Turi and Jose G. Delgado-Frias, “ FinFET 3T and

3T1D DRAM cells”, IEEE vol.no.12, 2012, pp 454-457.

[29].Priyanka Kushwah, Nikhil Saxena, Shyam Akashe and Saurabh Khandelwal,

“Reduction of Leakage Power and Noise for DRAM Design using Sleep Transistor

Technique”, IEEE Transactions on 5th International Communication on Advanced

Computing and Communication Technologies, vol.no.10, 2015, pp 80-83.

[30]. Zoran Jaksic and Ramon Canal, “Enhancing 3T DRAMs for SRAM replacement under 10nm”, IEEE Transactions on ICCD, 2012, pp 309-314.

[31]. M. S. B. S Shyam Akashe, “Analysis of Power in 3T DRAM and 4T DRAM cell design for different Technology”, IEEE vol.no.12, 2012, pp 18-21.

[32]. Weiwei, Kazuteru Namba and Fabrizio Lombardi, “Extending Non-Volatile

Operation to DRAM cells”, IEEE vol.no.1, 2013, pp 758-769.

[33]. W. K. Luk, Jin Cai, R. H. Dennard and M. J. Immediato, “A 3transistor

DRAM cell with Gate diode for enhanced speed and retention time”, IEEE

Transactions on VLSI Circuits, ed. 2006, pp 184-185.

[34]. S. G. R. C. Nivard Asymerich, “Impact of positive bias temperature instability on 3T1D DRAM cells”, IEEE transactions on VLSI, vol.no. 45, 2011, pp 246-252.

111

[35]. E. Amat, C. G. Almudever, N. Aymerich, R. Canal and A. Rubio, “Strain relevance on the improvement of 3T1D cell performance”, IEEE Transactions on

ICMDICS, 2012, pp 120-123.

[36]. M. A. G. Lorenzo, W. M. Tan, A. P. Ballesil and L.P. Alarion, “Experimental

Analysis read related transistors’ gate width sizing effects on 3T1D DRAM access time curve”, IEEE Transactions on ICSE, vol.no. 8, 2008, pp 450-454.

[37]. Prateek Asthana and Sangeeta Mangesh, “Capacitor less DRAM cell design for high performance embedded systems”, IEEE Transactions on ICACCI, vol.no.

14, 2014, pp 554-559.

[38]. K. Lovin, B. C. Lee, X. Liang, D. Brooks and G. Y. Wei, “Empirical performance models 3T1D memories”, IEEE Transactions on International

Conference on Computer Design, vol.no.9, 2009, pp 398-403.

[39]. H. Sharma and R. Singh, “Comparative Power Analysis of CMOS and

Adiabatic Logic Gates”, IEEE Transactions on IGCIT, 2015, pp 7-11.

[40]. Hee-Sup Song and Jin-Ku Kang, “A CMOS Adiabatic Logic for Low Power

Circuit Design”, IEEE Transactions on AP-ASIC, vol.no.17, 2004, pp 348-351.

[41]. Predictive Technology Model for SPICE Model Parameters, NIMO Group.

[42]. The Programmable Logic Book Data, Xilinx Corporation,1998, pp 4-10.

112

[43]. I. A. Pindoo , Tejinder Singh, Amritpal Singh , Ankit Chaudhary and P.

Mohan Kumar, “Power Dissipation Reduction using Adiabatic Logic Technique for CMOS inverter circuit”, IEEE Transactions on ICCCNT, vol.no.15, 2015, pp 1-

[44]. Guoqiang Hang, “Adiabatic CMOS Gate and Adiabatic Circuit design for low power applications”, IEEE, vol.no.2, 2005, pp 803-808.

[45]. Jone P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley &

Sons Inc., 2004, ISBN:978-0471127048.

[46]. BSIM4v4.7 MOSFET Model UC Berkeley device group by department of

ECE, University of California.

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