Low Noise Oscillator in ADPLL Toward Direct-To-RF All-Digital Polar Transmitter

Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter

JIAN CHEN

Doctoral Thesis in Electronic and Computer Systems Stockholm, Sweden 2012 TRITA-ICT/ECS AVH 13:03 KTH School of Information and ISSN 1653-6363 Communication Technology ISRN KTH/ICT/ECS/AVH-13/03-SE SE-164 40 Kista, Stockholm ISBN 978-91-7501-643-6 Sweden

Akademisk avhandling som med tillst˚and av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i Elektronik och Datorsystem onsdag den 13 mars 2013 klockan 9.00 i Sal D, Forum 120, Kungl Tekniska högskolan, Kista 164 40, Stockholma.

c Jian Chen, September 2012 Tryck: Universitetsservice US AB iii

Abstract

In recent years all-digital or digitally-intensive RF transmitters (TX) have attracted great attention in both literature and industry. The motivation is to implement RF circuits in a manner suiting advanced nanometer CMOS processes. To achieve that, information is encoded in the time-domain rather than voltage amplitude. This enables RF design to also benefit from CMOS process scaling. In this thesis an improved architecture of a digitally-intensive transmitter is proposed and validated experimentally. The techniques to lower oscillator phase noise and all-digital phase-locked loop (ADPLL) quantization noise are discussed and proved by both simulation and measurements. The impact of device sizing on 1/f 2 noise is analyzed and validated by measurements. Seven oscillators in 180-nm CMOS with the same LC-tank, operation frequency and power consumption but different core device width are compared. The conclusion clarifies the different suggestions on device sizing in the literature. It is illustrated that tail noise contribution is strongly positive dependent to core device sizing, while the contribution of core devices themselves is weakly dependent. Measurements demonstrate that there is a 14-dB phase noise increase when sizing core devices from 40 µm to 280 µm in the case of noisy tail current. If tail current is clean, the increase is only 4 dB. For 1/f 3 phase noise, the investigation reveals that the capacitance modulation is the dominant factor accounting for the 1/f or flick noise up- conversion, which is proved by measurements of 180-nm CMOS designs. A class-C oscillator with ensured start-up and constant amplitude is presented. It achieves a 3.9-dB phase noise reduction in theory and 5-dB reduction in measurements, compared to a conventional LC-tank oscillator operating at the same frequency and power. With the help of a digital bias voltage and bias current control loop, a 191 Figure-of-Merit (FoM) is achieved, showing the ability for low power and noise application. The previous oscillator optimization techniques have been applied in de- signing a digital controlled oscillator (DCO) for an ADPLL. A fine tuning varactor is proposed to reduce quantization noise, achieving a frequency step of only several hundreds Hz. In order to measure this small frequency step when the DCO is free-running, a method based on the narrow-band frequency modulation (FM) theory is proposed. The ADPLL wide-band FM is fulfilled by using a digital two-point modulation so that the modulation bandwidth is not limited by the ADPLL loop dynamic. Finally an all-digital polar TX is proposed based on an improved architecture. The ADPLL is used for FM while a one-bit low-pass Σ∆ modulator using the phase modulated ADPLL output as the clock accomplishes amplitude modulation. A simple AND gate is adopted to increase the fundamental power as mixers. A class-D power amplifier stages deliver 6.8-dBm power to antenna through a on-chip band-pass pre-filter. The filter also acts as single-ended to differential-end conversion and matching network. keywords: all-digital, digitally-intensive, frequency modualtion, phase modulation, amplitude modulation, polar, transmitter, oscillator, digital controled oscillator, DCO, VCO, voltage controled oscillator, class-C oscillator, class-D PA, ADPLL, phase noise, RF, CMOS.

Acknowledgement

It is a long but exciting journey (since 2006) to reach the destination of a PhD study. I would like to take this opportunity to appreciate sincerely all the people helping me during the road, although I might forget their names due to my bad memory. First I would like to thank my supervisors Prof. Li-Rong Zheng, Prof. Hannu Tenhunen and Prof. Dian Zhou for giving the opportunity to study at KTH, sup- porting me along the way and sharing with me their knowledge. Special thanks go to my technology supervisor Dr. Fredrik Jonsson, who opens the door of RF analog circuits for me, inspires me to progress by his deep insights and intuitive understanding on this field, and walks beside me during the way. The PhD journey would not be of such great fun if without his knowledge and advice. I wish to thank Dr. Qiang Chen for sharing his experience and suggestions for both work and life. I would like to thank Prof. Axel Jantsch, Agneta Herling, Alina Munteanu and Robin Gehrke for their support and assistance, and Prof. H˚akan Olsson for interesting discussion. I also want to thank all colleagues at KTH for their help who have made the PhD more enjoyable by complaining together and entertaining talks during lunch time: Geng Yang, Botao Shao, Dr. Huimin She, Qiansu Wan, Liang Rong, Jue Shen, Jie Gao, Yi Feng, Li Xie, Zhiying Liu, Jian Liu, Zhi Zhang, Peng Wang, Ning Ma, David S. Mendoza, Ana López Cabezas, Dr. Zuo Zhou, Qin Zhou, Jia Mao, Zhai Chuanying, Xueqian Zhao, Pei Liu, Ming Liu, Yasar Amin, Zhibo Pan, Shaoteng Liu, Yajie Qin, Xiaolong Yuan, Dr. Jinliang Huang, Dr.Jinfeng Du, Dr. Majid Baghaei Neijad, Dr. Saul Rodriguez Duenas, Dr. Roshan Weerasekera and Assoc. Prof. Zhonghai Lu. I also would like to express my sincere gratitude to Assoc. Prof. Svante Signell for reviewing the thesis, Prof. Georges Gielen from Katholieke Universiteit Leuven as my opponent, as well as Dr. Sven Mattisson from Ericsson, Assoc. Prof. Robert Bogdan Staszewski from TU Delft, Prof. Peter Händel and Prof. Mark Smith for serving as my committee members. I performed this PhD project together with Catena Wireless Electronics AB, Kista and after 2010 I fully worked there since I finished the PhD study except the defense. I sincerely thank my industry supervisors: Mats Carlsson and Dr. Char- lotta Hedenäs for their invaluable discussion. Also special thanks to Jan Rapp, KavéKianush and Rien Geurtsen for their support during writing the thesis and

v vi impressive talks, Paul Stephansson for cooperating an ADPLL project, Fredrik Pusa and Andreas Drejfert for the fun time together, Magnus Bohman and Giti Amozandeh for reviewing design, Rob Visser and Marcel van de Gevel at Delft for reviewing a manuscript, and all other colleagues for your help during that period. Since 2012, I work at Ericsson, Kista where I would like to thank all my colleagues and my manager Ali Ladjemi for helping me to involve into the new place, answer- ing my questions regarding to both work and life, encouraging me to pursue new technology, and sharing the fun time during work and Friday Fika. Finally I would like to thank my family, my wife, my parents, and my brother for your unconditional love and support, and for always encouraging me. I also want to thank my mother in-law for helping us to take care of my small son. You are always my motivation to move forward. Abbreviations

ACPR adjacent channel power ratio ADC analog to digital converter ADPLL all digital phase locked AM amplitudemodulation ASIC application specific integrated circuit ASK amplitude shift keying AWGN additive white Gaussian noise BER biterrorrate BW bandwidth CKR sampled reference clock CKV digitally-controlled oscillator clock CMOS complementary-metal-oxide semiconductor CNR carriertonoiseratio DAC digital-to-analog converter DCO digitally-controlled oscillator DSP digital signal processing ECG electrocardiography EEG electroencephalography FCW frequency control word FM frequencymodulation FoM figure of merit FPAA field-programmable analog array FPGA field-programmable gate array FSM finitestatemachine GMSK Gaussian filtered mnimum shift keying IC integratedcircuit IoT Internet-of-things ISF impulse sensitivity function IQ inphasequadrature KTH Royal Institute of Technology KDCO digitally-controlled oscillator gain LC-VCO LC-tank voltage-controlled oscillator LMS least-meansquare

vii viii

LNA lownoiseamplifier LTE long-term evolution LTI linear time-invariant LTV linear time-variant LO localoscillator MEMS micro-electro-mechanical systems NTF noise transfer function NMF noise modulation function OFDM orthogonal frequency division multiplexing PA power amplifier PAPR peak to average power ratio PM phasemodulation PLL phaselockedloop PSD powerspectraldensity PVT process voltage temperature PW-VCO pulse-wave voltage-controlled oscillator QoS qualityofservice REF referenceclock RF radiofrequency RF-DAC radio frequency digital-to-analog converter RFID radio frequency identification RX receiver SDR software-defined radio SoC system-on-chip SSB singlesideband TDC time-to-digital converter TX transmitter VPA variable phase accumulator VCO voltage-controled oscillator WCDMA wideband code division multiple access WIMAX worldwide interoperability for microwave access WLAN wireless local area network Contents

Contents ix

List of Figures xi

1 Introduction 5 1.1 Digitally-intensiveRFDesign ...... 7 1.2 ThesisInvestigationScope...... 8 1.3 ThesisOrganization ...... 11 1.4 IncludedPapersandContribution ...... 12

2 Phase Noise and Jitter 17 2.1 DeﬁnitionandMetrics ...... 17 2.2 PhaseNoisePropagationinSystems ...... 20 2.3 PhaseNoiseRequirementofOscillators ...... 22 2.4 FastOscillatorPhaseNoiseMeasurement ...... 25

3 PhaseNoiseOptimizationforCMOSLCOscillators 29 3.1 LargeSignalAnalysis ...... 29 3.2 Phase Noise Sources and Conversion Mechanisms ...... 33 3.3 Device Sizing for 1/f 2 PhaseNoise...... 38 3.4 Sizing for 1/f 3 PhaseNoise ...... 39 3.5 Pulse-waveorClass-COscillator ...... 41 3.6 HandCalculationsforaStartPoint ...... 44

4 QuantizationNoiseandSpursinADPLL 49 4.1 Introduction...... 49 4.2 ADPLL Noise Analysis: s-domain, z-domain and Time-domain . . . 51 4.3 QuantizationNoise...... 54 4.4 SpuriousTones ...... 56 4.5 Ill Condition: Steady-state Bandwidth Variation ...... 57 4.6 FrequencyTuningResolution ...... 58

5 DirectDigital-RFPolarTransmitter 63

ix x CONTENTS

5.1 Contemporary Transmitters: more digital ...... 64 5.2 The Proposed All-digital Polar Transmitter ...... 66 5.3 Phase Modulation: ADPLL with two-point modulation ...... 69 5.4 Amplitude Modulation: low-pass ∆Σ modulator ...... 70 5.5 H-bridge Class-D PA Stages and on-chip Matching Filter ...... 72

6 Summary and Future Work 75 6.1 Summary ...... 75 6.2 FutureWork ...... 76

A Phase spectral density and voltage spectral density 79

B Jitter and phase noise 81 B.1 Synchronousejitterandnoiseﬂoor ...... 81 B.2 Accumulating jitter and 1/f 2 phasenoise ...... 82

Bibliography 85

7 Included Papers 97 List of Figures

1.1 Communicationbasednetworking...... 5 1.2 Internetuserworldwide...... 6 1.3 Minimum feature size trend for Intel microprocessor technologies[1] . . 6 1.4 Digital polar transmitter with the D/A interface before antenna. . . . . 7 1.5 The die photographs and simpliﬁed schematics of (a) LC-tank VCO with the tail noise ﬁlter, (b) LC-tank VCO with a tail capacitor and (c) pulse-waveorclass-CVCO...... 8 1.6 (a) the ADPLL block diagram and (b) the die photograph...... 10 1.7 The all-digital TX die photograph and the block diagram...... 11

2.1 Phasenoiseinthefrequencydomain ...... 17 2.2 Normalizedsingle-side-band(SSB)PSD ...... 18 2.3 Synchronous jitter and accumulating jitter ...... 19 2.4 Phasenoisepropagationinbuﬀers...... 21 2.5 Phase noise propagation in frequency dividers...... 21 2.6 Phasenoisepropagationinbuﬀers...... 22 2.7 Phasenoisepropagationinmixers...... 22 2.8 Reciprocalmixing...... 23 2.9 (a) 8PSK Constellation, (b) symbol boundary and (c) probability dis- tributionfunction...... 24 2.10 TXleakageinaRFIDreader...... 25 2.11 TXleakagetoadjacentchannels...... 25 2.12 Phasenoisemeasurement...... 26

3.1 A simpliﬁed schematic of an all-PMOS LC-tank oscillator ...... 30 3.2 The feedback contained in a LC-tank oscillator ...... 30 3.3 The steady-state time domain waveforms of the drain current, the common- sourcevoltageandthegatevoltage...... 31 3.4 The schematic of the switched capacitor unit cell...... 32 3.5 (a) Tank voltage and (b) the ISF of active devices...... 33 3.6 The diﬀerent phase noise contributions in the LC-VCO...... 34

xi xii List of Figures

3.7 (a)Output voltage, (b) tail noise modulation function - Gtail and (c) eﬀective tail noise ISF - Γtail. ∆t istheconductiontime...... 36 3.8 (a) Output voltage, (b) switch pair noise modulation function - Gm and (c) eﬀective tail noise ISF - Γsp. ∆t istheconductiontime...... 37 3.9 Flicker noise up-conversion mechanism...... 40 3.10 TheschematicofPW-VCO...... 41 3.11 ThetimedomainwaveformofthePW-VCO...... 42 3.12 Start-upcircuitblockdiagram ...... 43

4.1 (a) Block diagram of ADPLLs and (b) phase accumulators and (c) the fractionalvariablephase ...... 50 4.2 QuantizationnoiseinADPLL...... 51 4.3 S-domainmodeloftheADPLL ...... 51 4.4 Z-domainmodeloftheADPLL ...... 53 4.5 Phase noise (1/f 2) of a time-domain free-running DCO: -120 dBc/Hz phase noise at 1-MHz offset from the 3.15-GHz center frequency and - 150dBc/Hznoisefloor...... 54 4.6 (a) phase noise and (b) phase error from a time-domain model with different bandwidth: 40 kHz (blue), 100 kHz (gree) and 300 kHz (red). DCO phase nosie: -120 dBc/Hz @ 1-MHz offset and - 150 dBc/Hz noise floor. Ideal DCO frequency tuning. Ideal TDC...... 55 4.7 Phase error code demonstrating a certain pattern...... 57 4.8 Phase noise when sweeping TDC resolution tres: 5 ps, 10 ps, 20 ps and 40 ps. DCO phase nosie: -100 dBc/Hz @ 1-MHz offset. Ideal DCO frequencytuning. ThePLLBW:100kHz...... 58 4.9 Finetuningarrangement...... 59 4.10 Measurementofthefinetuningstep ...... 60

5.1 (a) The polar transmitter and (b) the quadrature (IQ)transmitter . . . 63 5.2 Mobilestandards...... 64 5.3 The frequency up-conversion in digital transmitters ...... 65 5.4 The proposed all-digital polar transmitter ...... 67 5.5 The operation of the proposed all-digital polar transmitter...... 68 5.6 The two point modulation scheme of the ADPLL ...... 69 5.7 The linear z-domain model of the ﬁrst-order low-pass ∆Σ modulator . . 70 5.8 The noise shaping function of the ∆Σ modulators with diﬀerent orders. 71 5.9 H-bridge Class-D PA Stages and on-chip Matching Filter ...... 72

B.1 Synchronousjitter...... 81 B.2 Accumulatingjitter...... 82 List of Publications

Papers included in the thesis

Journal Papers 1. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenäs and Li-Rong Zheng. “Flicker Noise Conversion in CMOS LC Oscillators: Capacitance modulation dominance and core device sizing”. Journal of Analog Integrated Circuits and Signal Processing, vol. 68, no. 2, pp. 145-154, Aug. 2011. (Included Paper 3) 2. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenäs and Li-Rong Zheng. “A Low Power, Startup Ensured and Constant Amplitude Class-C VCO in 0.18 µm CMOS”. IEEE Microwave and Wireless Components Letters (MWCL), vol. 21, no. 8, pp. 427-429, Aug. 2011. (Included Paper 5) 3. Jian Chen, Liang Rong, Fredrik Jonsson, Geng Yang and Li-Rong Zheng. “The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ∆Σ Modulator ”. IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no. 5, pp. 1154-1164, May 2012. (Included Paper 7) 4. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenäs, Dian Zhou and Li-Rong Zheng. “Experimental Validation of Device Sizing on CMOS LC-VCO Phase Noise”. Manuscript. (Included Paper 2)

Conference Papers

5. Jian Chen, Fredrik Jonsson, Li-Rong Zheng, Hannu Tenhunen and Dian Zhou. “Sizing of MOS device in LC-tank Oscillators”. Proc. the 25th IEEE Norchip Conference, Denmark, pp. 1-6, Nov. 2007. (Included Paper 1) 6. Jian Chen, Fredrik Jonsson, Hakan Olsson, Li-Rong Zheng and Dian Zhou. “A Current Shaping Technique to Lower Phase Noise in LC Oscillators”. Proc. 15th IEEE International Conference on Electronics, Circuits and Sys- tems (ICECS), Malta, pp. 392-395, Aug. 31-Sept. 3, 2008. (Included Paper 4) 7. Jian Chen, Liang Rong, Fredrik Jonsson and Li-Rong Zheng. “All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator ”. Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC),pp. 1-4, Jul. 2011. (One of 16 best student paper ﬁnalists) (Included Paper 6)

1 Publications related but not included in the thesis:

Journal Papers

8. Geng Yang, Li Xie, M. M¨antysalo, Jian Chen, Fredrik Jonsson, Hannu Ten- hunen and Li-Rong Zheng. “Bio-Patch Design and Implementation Based on a Low-Power System-on-Chip and Paper-based Inkjet Printing Technology”. IEEE Transactions on Information Technology in Biomedicine (T-ITB), Vol. 16, No.6, pp. 1043-1050, Nov. 2012.

9. Geng Yang, Jian Chen, Li Xie, Jia Mao, Hannu Tenhunen and Li-Rong Zheng. “A Hybrid Low Power Bio-Patch for Body Surface Potential Mea- surement”. IEEE Transactions on Information Technology in Biomedicine (T-ITB), 2012 (second-round review with minor revision).

Conference Papers

10. Jian Chen, Fredrik Jonsson, Li-Rong Zheng, Mats Carlsson, Charlotta Heden¨as and Dian Zhou. ”Quantitative Comparison of 1/f Noise Upconversion in CMOS LC Oscillators”. Proc. the 8th IEEE Swedish System-on-Chip Con- ference, Arild, Sweden, May 4-5, 2009.

11. Jian Chen, Fredrik Jonsson and Li-Rong Zheng. “A Fast and Accurate Phase Noise Measurement of Free Running Oscillators Using a Single Spec- trum Analyzer ”. Proc. the 28th IEEE Norchip Conference, Tampere, Fin- land, pp. 1-4, Nov. 15-16, 2010.

12. Jia Mao, Sarmiento M, D., Qin Zhou, Jian Chen, Peng Wang, Zhuo Zou, Fredrik Jonsson and Li-Rong Zheng . “A 90nm CMOS UHF/UWB asymmet- ric transceiver for RFID readers”. Proc. IEEE European Solid-State Circuits Conference (ESSCIRC 2011),Helsinki, Finland, pp. 179 - 182, Sept. 12-16, 2011.

13. Chen Yao, Fredrik Jonsson, Jian Chen and Li-Rong Zheng. “A high- resolution Time-to-Digital Converter based on parallel delay elements”. Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2012),Seoul, Korea, pp. 3158 - 3161, May 20-23, 2012.

14. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng. “A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System”. Proc. Design Au- tomation & Test in Europe (DATE 2012),Dresden, German, pp. 443 - 448, March 12-16, 2012.

2 15. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng. “Bio-chip ASIC and printed ﬂexible cable on paper substrate for wearable healthcare applications”. ACM Proc. Of the 4th International Symposium on Applied Sciences in Biomedical and Communication Technologies (ISABEL 2011), Article No. 76, Oct. 2011. 16. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng. “A 1.0 V 78 µW reconﬁgurable ASIC embedded in an intelligent electrode for continuous remote ECG applications”. Proc. IEEE Engineering in Medicine and Biology Society (EMBC 2009), pp.2316-2319, Minneapolis, USA, Sept. 3-6,2009.

17. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng. ”Intelligent electrode design for long-term ECG monitoring at home: Pro- totype design using FPAA and FPGA”. Proc. the IEEE 3rd International Conference on Pervasive Computing Technologies for Healthcare (Pervasive- Health 2009), pp.1-4, Apr. 2009.

18. Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng. ”An ASIC Solution for Intelligent Electrodes and Active-Cable used in a Wearable ECG Monitoring System”. Proc. International Conference on Biomedical Electronics and Devices (BIODEVICES 2009), pp.209-213, Jan. 2009.

19. Geng Yang, Jian Chen, Ying Cao, Li-Rong Zheng, ”A Novel Wearable ECG Monitoring System Based on Active-Cable and Intelligent Electrodes”. Proc. IEEE 10th international conference on e-Health Networking, Applications and Services (Healthcom08). 2008.

20. Geng Yang, Ying Cao, Jian Chen, Hannu Tenhunen, Li-Rong Zheng, ”An Active-Cable Connected ECG Monitoring System for Ubiquitous Healthcare”. Proc. IEEE 3rd International Conference on Convergence and hybrid Infor- mation Technology (ICCIT08), 2008.

Chapter 1

Introduction

Internet Cloud Computing

Figure 1.1: Communication based networking.

Modern technologies have shaped our living style considerably. As one notice- able example, the Internet plays an important role in our daily life as shown in Figure 1.1. It connects people, personal computers (PCs) and mobile devices together allowing them to interact with each other real time, resulting in a smaller world. It has been reported that there are 2.3 billion global Internet users in 2011 as illustrated in Figure 1.2. The ubiquitous idea evolved from the internet is Internet- of-Thing (IoT) [2], which connects all uniquely identifiable objects (things). The IoT technology has been applied in different fields such as smart home, food track- ing, intelligent shopping and remote health care. Wireless communication is one of the backbone technologies for IoT, which

5 Figure 1.2: Internet user worldwide.

has been widely used for the interaction among PCs, mobile phones, servers, tags and readers. Useful data are both acquired and transferred wirelessly. Radio- Frequency (RF) transceiver System-on-Chips (SoCs) [3] are the key player to fulfill contemporary wireless communications such as GSM, Bluetooth, Zigbee, UWB, WiFi, WCDMA, WiMax, LTE and so on. The demand to design a general RF transceiver leads to the concept of software defined radios (SDRs) [4]. The SDRs can be programmed to meet most of applications, demonstrating high functionality and flexibility.

10 10000

1 1000

0.1 100 nm Micron

0.01 10

0.001 1 1970 1980 1990 2000 2010 2020

Figure 1.3: Minimum feature size trend for Intel microprocessor technologies [1]

6 Arising at the end of 1950’s, integrated circuits (ICs) have been embedded into each corner of the society. According to Moore’s law [5], the number of transistors on a IC will double approximately every two years, as in shown Figure 1.3. However, the size of tranditional Complementary Metal Oxide Semiconductor (CMOS) transistors will one day reach atomistic and quantum mechanical physics boundaries, and new materials and device structures are needed to extend the scaling [6, 7]. On the other hand, there is an another trend called More than Moore (MtM) [8] hav- ing been followed by the global semiconductor industry. As to MtM, added values are fulﬁlled by integrating more functionalities onto the die (SoC) or the package (System-in-Package, SiP). The functionalities can include MEMs, image sensors, power devices and RF blocks and so on, which do not necessary scale according to Moore’s Law. The topic of this theis covers the related design issues of fully-integrated CMOS RF transmitters for wireless communication applications.

1.1 Digitally-intensive RF Design

Digital Signal Domain Analog Signal Domain

I D/A Digital RF Interface Q

Figure 1.4: Digital polar transmitter with the D/A interface before antenna.

One enabling techology for SDRs is to digitize RF circuits making them all- digital or digitally-intensive. The digital RF design illustrates high programmability and can be integrated together with digital baseband. It enjoys shortened redesign time and performance improvements when processes are down-scaling, as it relies on the timing performance of transistors not the voltags. Due to the analog real world, analog signals can not be totally removed in RF transceivers. Hence the technology direction toward digital RF transceivers is to move digital-to-analog (D/A) interface closer to antennas, as shown in Figure 1.4 where most of signal processing in an all-digital polar transmitter is accomplished in digital domain and only analog signals appear in the interface. The goal of this thesis project is to achieve a RF all-digital transmitter, which should be highly programmable, compact and low power. It begins with the key building blocks such as oscillators and phase locked loops (PLLs) and then comes to transmitter system design.

7 1.2 Thesis Investigation Scope

IBIAS IBIAS IBIAS

VBIAS

(a) (b) (c)

Figure 1.5: The die photographs and simpliﬁed schematics of (a) LC-tank VCO with the tail noise ﬁlter, (b) LC-tank VCO with a tail capacitor and (c) pulse-wave or class-C VCO.

The content of the thesis is organized in the order of bottom-up design hierarchy, starting with oscillators, followed by ADPLLs and ﬁnally a transmitter. The theo- retical work is validated by both simulation and measurements of three oscillators in 0.18-µm CMOS, one ADPLL in 90-nm CMOS and one all-digital transmitter in 90-nm CMOS.

8 TX Building Block: oscillator Oscillators are one of the key building blocks in communication systems whose phase noise determines the overall performance. For a phase modulated scheme, phase noise damages phase information contained in carriers increasing the receiver bit error rate (BER) and it also contaminates the down-converted information through reciprocal mixing. Phase noise has received a great attention in the literature for example about model [9–15] and about phase noise reduction [16–25]. The first part of this thesis concerns phase noise reduction techniques in RF CMOS integrated oscillators. There are two topologies that can be adopted in CMOS integrated oscillator designs for low phase noise application: Colpitts and LC-tank. The LC-tank oscillators is discussed in this thesis since it is widely adopted in both academia or industry and shows better phase noise performance in the 1/f 2 region [26]. Three different LC-tank oscillators have been designed and taped out in 0.18 µm CMOS process as shown in Figure 1.5 to investigate how core device sizing, different noise filter techniques and different topologies will impact the phase noise performance and power consumption. To evaluate the oscillator design the widely adopted Figure-of-Merit (FoM) [27] in the literature is defined as phase noise normalized by power and frequency:

FoM(∆f)= (∆f) 20log (f /∆f) + 10log (P ) (1.1) L − o DC |mW where (∆f) is phase noise at the oﬀset frequency ∆f from the carrier fo and PDC is powerL consumption in mW unit.

TX Building Block: ADPLL Oscillators usually operate in the presence of a PLL in order to provide a clock signal with accurate frequency. Traditionally PLLs are analog designs where analog signals circulate within the loop. For an analog PLL, especially the one with a passive integrated loop filters, a large silicon area is needed. With process scaling the analog design will also suffer from lower voltage headroom. The motivations for saving silicon area, easing control and system integration, shortening redesign time and improving performance when process scaling make all digital PLLs (ADPLLs) in Figure 1.6 [28–31] being the new trend in future radio applications. The design is mixed-signal including both RF analog circuits and digital standard cells. All analog features of the building blocks in ADPLLs are terminated at the interface even though they are analog internally. Only the high frequency blocks such as digital controlled oscillator (DCO) and time-to-digital convertor (TDC) are custom-designed while rest of the system is digital standard cell implementation enjoying the digital design automation. The ADPLL design with fine tuning DCO and direct frequency modulation (FM) is the second part of the thesis.

9 Digital Std Cell Design RF Custom Design (MHz) (GHz)

+ Loop NI+F FCW + CKV Σ Filter -

NI+F CKR

TDC & Σ REF Σ: Phase Accumulator CKR FCW: Frequency Control Word (a)

(b)

Figure 1.6: (a) the ADPLL block diagram and (b) the die photograph.

ADPLL based All-digital Polar TX Based on the investigation made on the building blocks, a whole RF transmitter can be built. The proposed RF transmitter is digitally-intensive as illustrated brieﬂy in Figure 1.7. Compared to the conventional analog RF transmitter, signals are processed in the digital domain. All information is encoded into the timing

10 Digital Signal Domain Analog Domain

Envelope ρ 1bit Passive Phase θ ADPLL AND ∆Σ Filter

PM AM Shaper ClassD PA (a)

8 9 7

4 2

900 µm

(b)

Figure 1.7: The all-digital TX die photograph and the block diagram.

of waveforms such as the zero-crossing instants and the pulse density instead of voltage amplitudes. It demonstrates high programmability and is a compact design suitable for SoC integration.

1.3 Thesis Organization

In Chapter 2, phase noise definitions and the relation between phase noise and jitter are discussed. Followed by how phase noise propagates in systems and how to derive the phase noise specification from different requirements. Finally a fast and simple free-running oscillator phase noise measurement method is proposed.

11 In Chapter 3, different phase noise reduction methods for LC-tank oscillators are discussed and large signal behaviors are examined. Different noise sources and their phase noise conversion process are analyzed based on a time-variant method. Then the impact of device sizing on 1/f 2 and 1/f 3 phase noise are discussed and design implications are concluded. Class-C or pulse-wave VCOs are proposed demonstrating low phase noise and power consumption. The design procedure to obtain a quick start point is briefly discussed, which is based on a first-order analysis. In Chapter 4, the topics first cover the different models for analyzing the contribution of different noise sources in ADPLLs. Then quantization noise, spurious tone and ill condition are discussed. Finally a frequency tuning scheme with a small step size and the relevant measurement method are proposed. In Chapter 5, we present an all-digital transmitter based on ADPLL and phase synchronized ∆Σ modulator. It covers the operation principle, the phase path and amplitude path. In Chapter 6, we summarize the thesis and briefly introduce the included papers.

1.4 Included Papers and Contribution

Seven papers are included. In the following, we summarize the included papers and the authors’ contributions.

Oscillator optimization: device sizing Paper 1. Jian Chen, Fredrik Jonsson, Li-Rong Zheng, Hannu Tenhunen and • Dian Zhou. “Sizing of MOS device in LC-tank Oscillators”. Proc. the 25th IEEE Norchip Conference, Aalborg, Denmark, pp. 1-6, Nov. 19-20, 2007.

Paper 2. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenas, • Dian Zhou and Li-Rong Zheng. “Device Sizing and 1/f 2 Phase Noise in CMOS LC-tank Oscillators”. Manuscript.

Paper 3. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenas • and Li-Rong Zheng. “Flicker Noise Conversion in CMOS LC Oscillators: Ca- pacitance modulation dominance and core device sizing”. Journal of Analog Integrated Circuits and Signal Processing, vol. 68, no. 2, pp. 145-154, Aug. 2011. There are different opinions in the literature concerning core device sizing in LC-tank oscillators. The investigation in Paper 1 and paper 2 are aimed to clarify the different opinions. The relationship between 1/f 2 phase noise and core device sizing are examined based on closed-form expressions and intuitive explanations are given. Design implications are concluded, which are confirmed by measurement results of seven different width VCOs. The noise transfer functions are adopted to intuitively explain how different noise sources attack the LC-tank and hence induce phase noise.

12 Several 1/f noise up-conversion in oscillators have been proposed in the literature, however their relative weight is still under investigation. This information is important, since a certain 1/f noise suppression methods can mitigate the effect of one up-conversion mechanism but may increase the effects of others. Hence the dominant one should be identified. Paper 3 distinguishes the respective impact of different 1/f noise up-conversion mechanism by using a systematic simulation method in order to facilitate oscillator design in terms of reducing 1/f 3 phase noise. It demonstrates that capacitance modulation due to parasitic capacitance is the dominant mechanism, which leads designers to minimizing parasitic capacitance for a low 1/f 3 phase noise oscillator. This conclusion is validated by measuring fourteen VCOs with different core device size and a little different topology.

Oscillator optimization: Pulse-wave (class-C) oscillator Paper 4. Jian Chen, Fredrik Jonsson, Hakan Olsson, Li-Rong Zheng and • Dian Zhou. “A Current Shaping Technique to Lower Phase Noise in LC Os- cillators”. Proc. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Malta, pp. 392-395, Aug. 31-Sept. 3, 2008. Paper 5. Jian Chen, Fredrik Jonsson, Mats Carlsson, Charlotta Hedenas and • Li-Rong Zheng. “A Low Power, Startup Ensured and Constant Amplitude Class-C VCO in 0.18 µm CMOS”. IEEE Microwave and Wireless Components Letters, vol. 21, no. 8, pp. 427-429, Aug. 2011. Besides sizing device properly and increasing Q-value of LC-tanks another way to reduce phase noise is the topology improvement. Paper 4 proposes a modified topology calling PW-VCO or class-C VCO where the drain current is shaped into a pulse wave, so it generates a larger fundamental tone under the same bias current compared to conventional LC-tank oscillators (LC-VCOs). Closed-form equations are derived, showing that PW-VCOs can achieve a theoretic minimum phase noise reduction of 3.9 dB. Including the reduction in bias noise, the total phase noise reduction can be in the range of 5-10 dB. The class-C VCO may suffer from a startup difficulty since the gate bias voltage is lowered (NMOS VCO case) to fulfill the class-C operation. An automatic bias voltage control loop is also proposed to obtain a robust design. The stable amplitude is achieved during the whole tuning range by an inherently stable digital amplitude control loop. Paper 5 demonstrates the design details of both the bias voltage loop and the digital amplitude control loop. Measurement results of the design in a 0.18 µm validates the proposed ideas.

ADPLL based all-digital polar transmitter Paper 6. Jian Chen, Liang Rong, Fredrik Jonsson and Li-Rong Zheng. “All- • digital transmitter based on ADPLL and phase synchronized delta sigma

13 modulator ”. Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC),pp. 1-4, Jul. 2011. Paper 7. Jian Chen, Liang Rong, Fredrik Jonsson, Geng Yang and Li-Rong • Zheng. “The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ∆Σ Modulator ”. IEEE Journal of Solid-State Circuits, vol. 47, no. 5, pp. 1154-1164, May 2012.

The digitally-intensive RF demonstrates several advantages such as high flexibility or programmability, high integration and performace improving with process scaling. On the other hand analog intensive design will be trapped in a dilemma with scaling where the continousely lowered voltage leads to insufficient voltage headroom. Paper 6 proposes a digitally-intensively RF transmitter. It is a polar topology based on ADPLL and one-bit low-pass ∆Σ modulator. Only analog waveform appears at the last stage after on-chip filter. It is the interface between the digital transmitter and antenna. Paper 7 demonstrates the design detail of each building block of the digital transmitter. Measurements of the design in a 90nm CMOS process validates the concept and shows good performance in power efficiency and silicon area.

Chapter 2

Phase Noise and Jitter

2.1 Deﬁnition and Metrics

Phase Noise Noise is stochastic process, making signal behavior non-deterministic. As one sort of noise, phase noise [9–11, 13, 15, 32] gives rise to the non-deterministic behavior of signal phase. In the frequency domain, an ideal sinusoidal signal (v (t) = A o o cos(2πfot)) has all power concentrated at one frequency (fo) as shown in Figure 2.1(a). However when corrupted by phase noise, its power is spread to the neighbor frequency as “skirt” or “tail” shown in Figure 2.1(b). The degree of spreading indicates the level of phase noise.

Ao cos(2πfot) Aocos(2πfot + φ(t) )

a dB 1Hz

fo fo ∆f (a) Ideal Case (b) Real Case

Figure 2.1: Phase noise in the frequency domain

The signal contaminated by phase noise can be expressed as

v (t)= A cos(2πf t + ϕ(t)). (2.1) o o o 17 where (ϕ(t)) is phase error. Phase noise is characterized by the power spectral density (PSD) Sϕ of the phase error ϕ(t). However, it is not able to measure Sϕ directly using spectrum analyzers without the assistance of phase detectors [33–37], hence the normalized single-side-band (SSB) PSD of the signal vo(t) is commonly used for instead in both the industry and the academia to characterize phase noise:

S (f + ∆f) (∆f)= vo o (2.2) L po where Svo is the PSD of vo(t), po is the power of vo(t) and ∆f is the oﬀset frequency from the carrier frequency fo. The unit is dBc/Hz where dBc means it is normalized to the power of the carrier. For example, the signal shown in Figure 2.1(b) yields a dBc/Hz phase noise at ∆f oﬀset frequency from the carrier f . − o For RF CMOS integrated oscillators, there are three regions of interest in the normalized SSB PSD as shown in Figure 2.2.

-30dB/decade (1/f noise induced)

-20dB/decade (thermal noise induced)

Noise Floor (Buffers or instruments) Phase Noise (dBc/Hz) Noise Phase

0 Offset Frequency (Hz)

Figure 2.2: Normalized single-side-band(SSB) PSD

When ϕ(t) << 1 and at the moderate frequency oﬀset1, there is a relationship between phase noise S and the normalized SSB PSD (∆f): ϕ L

1 (∆ω)= S (∆ω) (2.3) L 2 ϕ

The derivation process of this relationship can be found in Appendix A.

1 The moderate frequency oﬀset is where the phase noise component of Svo dominates over the amplitude noise component.

18 as bs ba

tPD

To To To as PDF

tPD PDF bs To Ideal Case Ideal Case

tPD +Js

To+J1 To+J2 To+Jn

as PDF PDF tPD To bs Real Case Real Case (a) Synchronous Jitter (b) Accumulated Jitter

PDF: Probability density function tPD : Nominal propagation delay To: Nominal period

Figure 2.3: Synchronous jitter and accumulating jitter

Jitter Phase noise is a quantity in the frequency domain when examined in the time domain its equivalent is called jitter. Jitter causes non-deterministic behaviors of signals in the timing events such as the transition across a certain threshold. For oscillators or PLLs, there are two types of jitter of interest: synchronous jitter and accumulated jitter [38]. Synchronous jitter shows up in driven circuits where the output transition is the direct response of the input transition. The input is taken as a reference when calculating synchronous jitter. Synchronous jitter is the variation of the delay between the input transition and the corresponding output transition as illustrated in Figure 2.3(a). On the other hand, accumulated jitter exists in autonomous systems where there is no input and the current output transition depends on the previous output transition. It takes the previous timestamp as a reference. Hence the timing uncertainty accumulates along with time like a random wander, as shown in Figure 2.3(b).

Relation of Phase Noise and Jitter Phase noise and jitter convey the same information but expressed in different do- mains. Therefore it is intuitive that they are convertible to each other. Synchronous jitter relates to the flat region of the phase noise spectrum (noise floor in Figure 2.2), while accumulated jitter relates to the 1/f 2 region with a -20 dB/decade slope

19 as in Figure 2.2 if it is assumed that both jitter are caused by a white Gaussian stationary or T-cyclo-stationary random process [38]. 2 The equation relates the accumulated jitter ja and 1/f phase noise is

1 1 (f)= S (f)= (2πf )2S (f) (2.4) L 2 ϕ 2 o ja where Sja is the PSD of accumulated jitter. This equation is based on the fact that

ja(t) ϕ(t) = 2π = 2πfoja(t) (2.5) To

The synchronous jitter j is related to the noise ﬂoor as s Lo

j = T /2π f (2.6) s o Lo o p More information about how to derive the above equations can be found in Appendix B.

2.2 Phase Noise Propagation in Systems

In order to calculate phase noise at the output of systems, it is necessary to understand how phase noise propagates in different blocks such as buffers, frequency dividers, frequency multipliers and mixers. We will discuss them in this section. High order phenomenons are discarded in this first order analysis such as the AM-to-FM conversion or the frequency folding [37]. Although some information would be lost, the intuitive analysis establishes a reasonable baseline needed for the system design stage by merely hand calculation.

Buﬀers

Buffers are used [39] to isolate oscillators from other noisy circuits that degrades phase noise performance. Different kinds of buffers can be used depending on applications, such as the open drain buffer [40], the rail-to-rail buffer [41], and self-biased buffer [42]. Under the assumption that buffers are noiseless devices, the phase noise gain of buffers is unit, meaning the timing variation at the input will be transferred to the output without any amplification as shown in Figure 2.4. In reality, output phase noise shows a higher level and buffers can often be the dominating source of noise at large frequency offset [10, 13, 15].

20 vin (t) Noisless vout (t)

J1 J2 J3 J4 J1 J2 J3 J4 Buffer

Jitter: Jout = Jin

Phase Noise: ∆φ out = Jout 2πf out = Jin 2πf in = ∆φ in

Figure 2.4: Phase noise propagation in buﬀers.

Frequency Dividers

Frequency dividers are widely used in frequency synthesizers and transceivers. For a division ratio N, only one of N clock cycles is passed to the output while N-1 clock cycles are swallowed. During the time when the input is passed to the output, the same amount of the timing variation at the input will appear at the output. Since the output frequency is 1/N the frequency of the input, the resulting phase variation at the output is 1/N of that at the input [37] as shown in Figure 2.5.

vin (t) 1/N vout (t)

J1 J2 J3 J4 Frequency J1 J2 J3 J4 Divider N=2

Jitter: Jout = Jin

Phase Noise: ∆φ out = Jout 2πf out = Jin 2πf in /N = ∆φ in /N

Figure 2.5: Phase noise propagation in frequency dividers.

Frequency Multipliers

For frequency multipliers with the ratio N, the amount of the timing variation at the output is kept the same. However the output frequency is N times smaller than the inputs, phase variation at the output is N times larger than that at the input, as shown in Figure 2.6

21 x vin (t) N vout (t)

J1 J2 J3 J4 Frequency J1 J2 J3 J4 Multiplier N=2

Jitter: Jout = Jin

Phase Noise: ∆φ out = Jout 2πf out = Jin 2πf in N = ∆φ in N

Figure 2.6: Phase noise propagation in buﬀers.

Mixers For mixers the output demonstrates the phase variation either equal to the sub- traction or summation of the phase variations of two inputs due to their behaviors [43, 44], as shown in Figure 2.7. If these two inputs are independent to each other, phase noise at the output will be the sum of phase noise of the inputs. On the other hand, if the two inputs show some correlation, the output phase noise can be higher or lower than the sum of input phase noise depending on the phase relation of two inputs.

vin1(t), ∆φ in1

Mixer x vout (t), ∆φ out =∆φ in1±∆φ in2

vin2(t), ∆φ in2

Figure 2.7: Phase noise propagation in mixers.

2.3 Phase Noise Requirement of Oscillators

From Reciprocal Mixing Effects Phase noise will cause reciprocal mixing effects in receivers as shown in Figure 2.8. It occurs when a weak desired signal is accompanied by a strong interferer or a blocking signal at a small offset frequency ∆f. Because of phase noise (”tail” or side band) of local oscillators (LOs), the interferer is also down-converted to the frequency band of interest, decreasing the signal-to-noise (S/N) ratio. Given the received signal power Psig, the interference power Pint and the minimum signal-to-noise ratio S/N required at the output of mixers, the LO phase noise (∆f) requirement can be estimated [39]. The power of the desired signal L after down-conversion can be expressed as PsigGmixer where Gmixer is the conver-

22 sion gain of down-conversion mixers. The power of the down-converted interferer is PintGmixer. Due to LO phase noise, the sideband of the down-converted interferer will appear in the frequency band of interest with the power of PintGmixer (∆f)BW where BW is the noise bandwidth. With the above equations the phaseL noise requirement can be derived:

P G S/N = 10log sig mixer (2.7) P G (∆f)BW int mixerL

(∆f) = P S/N P BW (2.8) L |dB sig|dB − |dB − int|dB − |dB

Interference Noisy LO

Signal

fIF +fo fo ∆f ∆f

x Mixer

Downconverted Interference Downconverted Signal

Inband noise

fIF

Figure 2.8: Reciprocal mixing.

From RMS Phase Error Phase noise causes symbol points in a constellation diagram to spread from the ideal position on the angular axis as shown in Figure 2.9(a). When the phase spread (or phase error) is large enough to cross the symbol boundary as illustrated in Figure 2.9(b), the bit error occurs. From the statistics point of view, the phase spread can be characterize by the probability density function (PDF) as shown in Figure 2.9(c).

23 For wireless communication links the bit error rate (BER) is an important measure of the quality of service (QoS). BER is the ratio of bits received in error to bits sent correctly. Phase noise is one of the contributors to BER and is related to it through RMS phase error as

fH ϕ = 2 10L(∆f)/10df (2.9) rms sZfL where (∆f) is SSB normalized phase noise at the oﬀset frequency ∆f in dBc/Hz. One keyL relationship is that the RMS phase error is identical to the standard deviation (σ) of the phase error. So given the RMS phase error and the digital modulation scheme, the number of σ needing to cross the symbol boundary can be calculated and hence the probability of the bit error can be calculated by integrating the area of the PDF from the minus inﬁnity to the symbol boundary as shown in Figure 2.9(c). b Perr(v

Symbol Boundary

22.5o

Symbol (a) Boundary

b σ σ PDF

v b µ (b) (c)

Figure 2.9: (a) 8PSK Constellation, (b) symbol boundary and (c) probability distribution function

24 From TX Leakage

Circulator

LNA

BPF

Figure 2.10: TX leakage in a RFID reader.

The non-ideal isolation between the RX chain and the TX chain in transceivers causes part of the transmitted power to leak into the RX chain, degrading performance such as noise figure. The TX chain and the RX chain are connected through a duplexer with finite isolation and can operate simultaneously. Take the RF identification (RFID) systems with passive tags as an example. As seen in Figure 2.10, the reader receives the back-scattered information from tags and transmits power (a continuous wave signal from the LO at the same frequency) to tags simultaneously. Besides the high isolation requirement of duplexers, it also places a requirement on LO phase noise specification.

Leakage

LO CH1 CH2 CH3

Figure 2.11: TX leakage to adjacent channels.

For another kind of TX leakage, the transmitted power leaks into adjacent channels due to phase noise as in Figure 2.11. Especially in a narrowband application like the GSM with 200 kHz channel, this leakage imposes a strict speciﬁcation on phase noise.

2.4 Fast Oscillator Phase Noise Measurement

As mentioned in Section 2.1, the real phase noise of a sinusoidal signal v (t)= A cos(2πf t + ϕ(t)) (2.11) o o o 25 is the PSD Sϕ of phase error ϕ(t). When ϕ << 1 and at the moderate oﬀset frequency, (∆f) (the SSB normalized PSD of v (t)) is used to represent phase L o noise Sϕ, as there is a relationship as indicated by Equation 2.4 which is repeated here: S (f) (f)= ϕ (2.12) L 2

DUT o 90 X Spectrum

Reference Phase detector (mixer)

PLL

(a) Phase Decter

Delay Line

o 90 X Spectrum

ɸ (b) Frequency discriminator

Figure 2.12: Phase noise measurement.

The SSB normalized phase noise is easier to be measured using spectrum analyzers. There are several conventional methods to measure phase noise of free-running oscillators such as 1) a PLL based system to lock oscillators to a clear reference [33–35] as in Figure 2.12(a); 2) a delay line as frequency discriminators [35] as in Figure 2.12(b); 3) injection locking oscillators to a clear reference [36]. Some extra components are needed for all those methods such as clean stable reference sources with the same frequency (GHz) of oscillators under test, double balanced mixers, multiple long delay cables and low pass ﬁlters, which makes these methods a little bit expensive. For the injection locking method [36], the locking bandwidth should be as small as possible in order to read close-in phase noise directly. Within the

26 locking bandwidth, phase noise of the oscillators under test is suppressed so that some post-processes [36] are needed to retrieve original phase noise. In order to make a fast and simple setup without losing accuracy, we proposed a measurement method as published in our paper [45]. It only uses a modern spectrum analyzer without other assistant components. The basic idea is to calculate phase noise based on the measured I and Q data of the free-running oscillator output. The I and Q data are acquired by the spectrum analyzer and stored in its embedded memory. With the I/Q data, the instantaneous phase is calculated using the expression: I sin(ϕ) ϕ = actan = actan (2.13) Q cos(ϕ) Then the phase variation away from the ideal phase is calculated. Phase noise is the PSD of the phase variation. This method is simple and fast which is validated by measurements [45]. The limitation of how close-in phase noise can be measured depending on the long-term frequency instability or frequency drift of the oscillator under test and the size of the embedded memory. Also noise of spectrum analyzers should be small enough compared to oscillators under test.

Chapter 3

Phase Noise Optimization for CMOS LC Oscillators

Phase noise of oscillators impacts the performance of the whole radio front-end. It also consumes a large proportion of system power. That’s why researchers have been continuing to pay their eﬀorts to reduce both phase noise and power of oscillators such as [10, 11, 13–15, 17–27, 32, 46–55]. In this chapter, LC-tank oscillators are covered. First, the large signal behaviors are discussed. Second, the phase noise sources and their conversion mechanisms with time-variant operation points are handled. Based on these analyses, phase noise optimization by device sizing and an improved topology (pulse-wave or class- C oscillator) are presented. Finally a hand calculation based design procedure for a start point is presented.

3.1 Large Signal Analysis

Start Oscillation Oscillators are autonomous circuits, demonstrating positive feedbacks at certain bias conditions. It can generate continuous periodic signal without any input except noisy DC bias. For the LC-tank oscillator in Figure 3.1, the nominal oscillation frequency (fo) is determined by the equivalent tank inductance (Ltank) and the 1 equivalent tank capacitance (Ctank) as

1 fo = (3.1) 2π√L C tank tank 1The harmonic-rich drain current will change the oscillation frequency indicated by (3.1) known as Groszkowski effect [56]. This effect is neglected here without affecting the validation of the following analysis.

29 Vdd

Ibias

vs M1 M2 vg1 vg2 id1 id2

+ v - n o p Rp

Ctank

Ltank

Figure 3.1: A simpliﬁed schematic of an all-PMOS LC-tank oscillator

Vdd

IB H(s)

= X(s) + H(s) Y(s) noise +

FeedBack

Figure 3.2: The feedback contained in a LC-tank oscillator

Both Ctank and Ltank include the parasites from active devices and metal inter- connections of the layout. To understand the oscillation of LC-tank oscillators, it is examined as a feedback circuit shown in Figure 3.2: Y (s) H(s) = (3.2) X(s) 1+ H(s)

30 Current id2(t) id1(t)

IB E

0 t ∆t

Voltage vs(t)

Device Off Ao vth,p

0 t

vg1(t) vg2(t)

Figure 3.3: The steady-state time domain waveforms of the drain current, the common-source voltage and the gate voltage.

If there is a frequency ωo and so = jωo, the open loop gain H(s) meets the following conditions H(s ) 1 (3.3) | o | ≥ o H(so) = 180 (3.4) then self-oscillation can happen. Since the closed-loop feedback becomes positive, the small noise signal at ωo can be amplified infinitely. These two conditions are the Barkausen creteria, which are necessary [46] but not sufficient for oscillation. The oscilation frequency from the Barkhausen creteria agrees with (3.1). Though the LC-tank oscillator can start oscillation when H(s ) = 1, it is | o | better to design H(so) as 2 or 3 in reality to make sure it can oscillate under all process, voltage and| temperature| (PVT) variations.

Voltage Waveforms

In steady state the common-source node (vs) is assumed as virtual ground and the 2 output voltage (vo) is sinusoidal . The bias current (IB) is switched completely between two cross-coupled switch pair devices (M1 and M2), leading to the drain

2It is assumed that the Q-value of LC-tanks is so high that the output voltage waveform is sinusoidal.

31 Switched Capacitor Unit vM(t) 1 1 vM(t) Ron Ron 2 2 n p Equivalent n p C1 C1 Vc=VDD C1 C1

AC Ground Vc

(a)

Voltage vM(t) AM

0 t

(b)

Figure 3.4: The schematic of the switched capacitor unit cell.

current with a near rectangular shape. Figure 3.3 illustrates the time domain waveforms. The switch pair devices are turned oﬀ when the gate-source voltage (vg-vs) is smaller than the threshold (vth,p) as the shadowed area in Figure 3.3.

The output voltage vo = vg2 vg1 is the gate-drain voltage of the switch pair devices. High amplitude can cause− reliability problem of the switch pair devices, which should be taken in account at design stage. The switched capacitor bank is usually based on the unit cell [57] as shown in Figure 3.4(a). When the control signal Vc = VDD, the voltage swing (Figure 3.4(b)) at the node M can cause the PN junctions of drain-substrate and source-substrate to be positively biased. The swing (AM ) at M is

1 1 AM = Ao (3.5) 2 Qc + 1 where A is the diﬀerential oscillation amplitude, Q = 2/(ω C R ) is the quality o c o 1 on factor of the half branch when Vc = VDD as shown in the right of Figure 3.4(a) 3 . Although AM is small , oscillator designers should be aware positive biased PN junctions may appear.

32 Vo(t)

(a)

Γ(t)

(b)

Figure 3.5: (a) Tank voltage and (b) the ISF of active devices.

3.2 Phase Noise Sources and Conversion Mechanisms

Phase noise of oscillators has been widely studied in the literature using linear time invariant (LTI) analysis [58], linear timing varying analysis (LTV) [11, 49] or rigorous mathematical analysis [14]. Osicllators are time-varying systems, so LTV models are more accurate compared to LTI ones. Due to the intuitive feature, the LTV model - impulse sensitive function (ISF) [11, 12] is utilized here. The ISF describes how much phase shift is resulted when a unit current impulse is injected into one node of oscillators at a certain instant of one period. Figure 3.5(b) shows the ISF of active devices (switch pair devices) of LC-tank oscillators. As seen, oscillator phase is more sensitive to device noise when the tank voltage (Figure 3.5(b)) is at zero-crossing instants A. Given the noise current (n2/∆f) and the associated ISF (Γ), induced phase

3 Because Ron is usually small in order not to lower Q-value of LC-tanks, so most of the voltage is dropped over the capacitor C1

33 noise can be calculated as [11, 12]

2 in 2 1 (∆ω) = 10log Γrms 2 2 . (3.6) L ∆f 2qmax∆ω ! where Γrms is the root mean square (RMS) of Γ, ∆ω is the offset frequency from ωo and qmax is the maximum charge swing at the node where the noise current is injected. When the noise current is injected over LC-tanks, q = A C (A max o tank o is the oscillation amplitude and Ctank is the total capacitance in LC-tanks). 2 2 The second term in (3.6) 1/(2qmax∆ω ) is same for different noise current injecting the same node, so we only examine the first term (It is called effective noise [24]) in the following discussion:

N =Γ2 i2 /∆f. (3.7) eff rms n

Vdd

i IB tail

vs M1 M2

id1 id2

Vn,m1 Vn,m2

+ v - n o p

itank

Ctank

Ltank

Figure 3.6: The diﬀerent phase noise contributions in the LC-VCO.

34 Cyclo-stationary Noise

The cyclo-stationary noise in(t) can be expressed as a stationary part ino multiplied by a noise modulation function (NMF) α(t): i (t)= i α(t). (3.8) n no For the oscillator attacked by cyclo-stationary noise, it is taken as the stationary part ino attacks the oscillator with an eﬀective ISF Γeff [11]: Γ =Γ α(t). (3.9) eff where Γ is the ISF associated stationary noise.

LC-Tank

2 As to noise (itank/∆f) from the LC-tank loss as shown in Figure 3.6, the associated ISF can be approximated as the ﬁrst-order derivative of the normalized output voltage [11, 26]: Γtank(t)= sin(2πfot) (3.10)

So the RMS of Γtank is 1/2 and the eﬀective noise of LC-tanks is

1 i2 N = tank (3.11) eff,tank 2 ∆f

Tail Devices

When the bias current IB is incorporated with a small signal noise itail as IB +itail as in Figure 3.6, the diﬀerential output current Io injecting the LC-tank can be approximated using ﬁrst-order Taylor expansion as

∂Io Io(t,IB + itail)= Io(t,IB)+ itail = Io(t,IB)+ Gtail(t) itail (3.12) ∂IB where ∂Io Gtail(t)= (3.13) ∂IB is the tail noise modulation function (NMF) describing how tail current noise is propagated to LC-tanks. Figure 3.7(b) illustrates the waveform of Gtail. 2 So that the eﬀective ISF (Figure 3.7(c)) of itail/∆f is [11] Γ (t)= G (t) Γ (t) (3.14) tail tail tank 2 The eﬀective noise of tail noise itail/∆f is N =Γ i2 /∆f (3.15) eff,tail RMS,tail tail where ΓRMS,tail is the RMS of Γtail.

35 Vo(t)

0 t To/2 To

Ao (a)

Gtail (t)

Larger Width M 1,2 ∆t 1/2

0 t T /2 o To 1/2

Гtank (t) (b)

Гtail (t)

Larger Width M 1,2

To/2

Гtail (t) = Гtank (t)·Gtail (t)

(c)

Figure 3.7: (a)Output voltage, (b) tail noise modulation function - Gtail and (c) eﬀective tail noise ISF - Γtail. ∆t is the conduction time.

Switch Pair Device

Switch pair drain noise is modeled as input-referred gate voltage noise (vn,m1 and vn,m2) as shown in Figure 3.6. As the switch pair devices are switched on and oﬀ periodically, vn,m1 and vn,m2 are the cyclo-stationary noise expressed as

v (t)= v α (t) (3.16) n,m1 no,m m where vno,m is the stationary part of the cyclo-stationary noise and αm(t) is the noise modulation function. By using the similar ﬁrst-order analysis as in the above section, the diﬀerential

36 Vo(t)

0 t

To/2 To

Ao (a)

Gsp (t) Larger Width M 1,2

0 t

(b) Гtank (t)

Гsp (t)

Larger Width M 1,2

t 0

Гsp (t) = Гtank (t)·Gsp (t) (c)

Figure 3.8: (a) Output voltage, (b) switch pair noise modulation function - Gm and (c) eﬀective tail noise ISF - Γsp. ∆t is the conduction time.

output current Io (Figure 3.6) in the case of switch pair noise can be approximated

∂Io Io(t,vo + vn,m1 + vn,m2)= vo(t,vo)+ (vn,m1 + vn,m2) (3.17) ∂vo

37 Inserting all the expressions in (3.17), 3.17 can be simpliﬁed as

∂I I (t,v + v + v )= v (t,v )+ o v (3.18) o o n,m1 n,m2 o o ∂v no,m r o Hence the cyclo-stationary switch pair noise can be taken as the stationary noise vno,m with the noise modulation function (Gsp):

∂I G (t)= o (3.19) sp ∂V r o 2 Then the eﬀective ISF of isp/∆f is [11] Γ (t)= G (t) Γ (t) (3.20) sp sp tank

Figure 3.8(b) illustrates the waveform of Gsp. The eﬀective noise of switch pair noise is N =Γ v2 /∆f (3.21) eff,sp RMS,sp no,m where ΓRMS,sp is the RMS of Γsp.

3.3 Device Sizing for 1/f 2 Phase Noise

The impact of core device sizing on phase noise is discussed in this section. Three phase noise contributors as tail noise, switch pair noise and LC-tank noise are examined respectively.

Tail Noise As shown in Figure 3.7(a), the tail noise modulation function has the same period as the oscillator, meaning the tail noise components around even harmonics are folded to the vicinity of the fundamental tone at the LC-tank producing phase noise. This can also be seen from the effective ISF in Figure 3.7(c) where it shows half period of the oscillator and thus only contains power at even-order harmonics. The noise modulation function peaks when only one of the switch pair FETs is ON, meaning all tail noise injects and perturbs the LC-tank. On the other hand when both of the FETs are ON, the noise modulation function is small or even zero (at the equilibrium point A) , because only the differential part of drain noise current produces phase noise. Therefore there is an intuitive induction to lower tail phase noise that the switch pair devices should switch slowly or the time when only one switch pair device is ON should be reduced. It is verified in Figure 3.7(c) where the dotted line is the case of larger switch pair width. As ssen the smaller the width the smaller phase noise is, as 1/f 2 phase noise depends on the RMS value of the effective ISF (or the curve encompassed area) in Figure 3.7(c). As seen in Figure 3.7(c), the effective ISF Γtail is a odd harmonic function with a zero DC value, meaning no low-frequency noise is up-converted. It is not

38 true in reality, as the tail current source is usually the dominant 1/f 3 phase noise contributor [22]. This discrepancy comes from the assumption of the tank ISF in (3.10) and hence Γtail is not an odd harmonic function in reality.

Switch Pair Noise The noise modulation function for switch pair noise (Figure 3.8(b)) has a period two times of the oscillator, so that noise around the fundamental tone and other odd harmonics are folded and produces phase noise. This property is also demonstrated by the effective ISF Γsp in Figure 3.8(c), since it only contains power at the fundamental tone and odd harmonics. From Figure 3.8(b) when only one switch pair FET is ON, no noise is output and thus no phase noise, which is similar to the noise rejection mechanism in a cascaded configuration where output noise is dominated by tail current devices other than cascaded devices. It seems we should reduce the time when both devices are ON or have a fast switch by increasing the width of switch pair devices. However, this action will increase the peak of Gsp as shown in Figure 3.8(b). These two effects cancel each other, making the RMS of Γsp approximately same, so sizing switch pair devices has weak impact on the phase noise contribution of switch pair themselves.

LC-tank Noise Noise of the passive components in the LC resonator attacks the LC-tank directly, which is also not impacted by sizing of switch pair FETs [17]. To reduce its phase noise contribution, a method is to improve the Q-value of the LC-tank.

Sizing Strategy for 1/f 2 Phase Noise Based on the above discussions, phase noise due to LC-tank loss and switch pair FETs are relatively independent of the width of switch pair FETs and phase noise due to tail noise is positively dependent on it, therefore the width should be minimized for the optimal design as long as other design constraints are not violated such as the oscillator start-up constraint. Especially in the case when tail noise is the dominant contribution, the minimum switch pair width should be adopted. The sizing strategy is discussed and validated by measurements in our included Paper 1 [23] and Paper 2. Besides phase noise consideration, minimizing the width also help to increase the tuning range, since it reduces the parasitic capacitance from switch pair devices.

3.4 Sizing for 1/f 3 Phase Noise

1/f 3 phase noise is caused by ﬂicker noise or 1/f noise of CMOS devices. There are several up-conversion mechanisms as shown in Figure 3.9 to cause low frequency ﬂicker noise to appear in the 1/f 3 region of phase noise.

39 Vbias

Ctail 3 CM node

2fo M1 M2

Cvar =f(vnois ) 2 1 io

Cfixed

Figure 3.9: Flicker noise up-conversion mechanism.

1. Harmonic modulation or Groszkowski effect [17, 56]: flicker noise from tail FETs and switch pair FETs modulates the harmonic content of differential output current going into LC-tanks and hence modulates the oscillation frequency causing phase noise. 2. Capacitance modulation: tail flicker noise is up-converted to AM noise around the oscillation frequency fo by switch pair devices and then causes phase noise through AM-to-FM conversion [49]; tail flicker noise and switch pair flicker noise modulate the equivalent capacitance of tail capacitance (at common- mode node) seen by LC-tanks and hence modulates the oscillation frequency resulting in phase noise [17].

3. Common-mode modulation: tail flicker noise is up-converted to 2fo at the common-mode node by the channel length modulation effect of tail devices and then the up-converted flicker noise is down-converted to around fo at LC-tanks by switch pair devices resulting in both AM noise and FM noise [50].

Several up-conversion mechanisms account for low frequency flicker noise up- converted to be 1/f 3 phase noise. Different mechanisms can have different weights on phase noise contribution. A certain suppression method to mitigate one up- conversion mechanism may increase the effect of others, hence it is better to distinguish their relative weights and find the dominate one. We perform a two-step simulation in our included paper 3 [59] in order to distinguish their respective impacts: without device parasitic capacitance and with

40 Vdd

Ibias Ctail

vs M1 M2 vg1 vg2 id1 id2

Vbias

n + vo - p

Ctank

Ltank

Figure 3.10: The schematic of PW-VCO. device parasitic capacitance. Without device parasitic capacitance, the harmonic modulation and the common-mode modulation are the only two mechanisms4 for noise up-conversion. Comparing the results of each step, it has been demonstrated that the capacitance modulation is the dominant mechanism, which implies active devices should have small size to reduce the parasitic capacitance. This conclusion has been validated by measurements of fourteen VCOs in 0.18-µm CMOS in the included paper 3 [59].

3.5 Pulse-wave or Class-C Oscillator

1/f 2 phase noise of LC-VCOs can be expressed as [18, 26]:

1 1 (∆ω) F (3.22) LLC ∝ Q2 P LC sig

FLC =1+ γ + ηtail (3.23)

4There is no varactor in the simulated VCO, so the non-linear parasitic capacitance of active devices is the only source of capacitance modulation

41 Current id1(t)

id2(t)

0 t

Voltage Device Off

vs(t)

vth,p Vbias t

vg1(t) vg2(t)

Figure 3.11: The time domain waveform of the PW-VCO.

where Q the Q-value of LC-tanks, Psig the power consumption of LC-tanks and FLC the noise factor including the contributions of tank loss: 1, switch pair devices: γ, and tail devices: ηtail. If tail noise can be filtered out entirely, the best noise factor is FLC =1+ γ. Further improvement needs efforts paid on topology improvement. The pulse-wave (PW) VCO [24, 25, 60], shown in Figure 3.10, is proposed to further improve performance. The drain current (Id1 and Id2) are shaped into a pulse-wave (Fig. 3.11) so that higher amplitude is obtained under the same DC power consumption. High frequency tail noise is filtered out by the tail capacitor Ctail. The phase noise improvement can also be explained by the ISF theory [11]: oscillators are most sensitive at the zero-crossing instant of oscillation voltage vo(t) and insensitive at peak instants. The PW-VCO (Figure 3.11) delivers drain currents to LC-tanks mainly at the time when the oscillator is insensitive and hence small phase noise is induced.

Start-up Circuits

At the optimal operating point, the bias voltage Vbias may be so large (PMOS oscillator case) to cause the oscillator start-up failure. A start-up circuit is introduced as shown in Figure 3.12. The bias voltage is set to 0 when amplitude is small. As long as oscillation amplitude is larger than the pre-deﬁned value, the bias voltage is switched to Vop for the optimal phase noise performance.

42 0 Vbias Vop

Amplitude Detector

A_det

Vref Hysteresis Comparator

Figure 3.12: Start-up circuit block diagram

The low pass ﬁlter (LPF) is adopted to avoid fast transients in the bias voltage control loop, potentially stopping the oscillation. It can also ﬁlter out noise from the reference voltage and the switch.

Oscillation amplitude of PW-VCO Oscillators are designed to operate in the current limited region [13] where the oscillation amplitude is found as

A = I R (3.24) o 1 p where I1 is the fundamental tone of the output current Io across LC-tanks and Rp is equivalent LC-tank parallel resistance. The ﬁrst harmonic is found by Fourier expanding drain current

1 Φ I = I (φ)cos(φ)dφ (3.25) 1 π o Z−Φ When the drain current is a narrow pulses meaning a small conduction angle Φ. The oscillation amplitude can be approximated [25]:

I1,PW = Ibias (3.26) This result is identical to the oscillation amplitude of a Colpitts oscillator [26]. As to LC-VCOs, the drain current is a near rectangular waveform where the fundamental tone can be approximated as 2I I = bias (3.27) 1,LC π

43 Parameter Value Tuning Range 3.0 GHz - 4.2 GHz Phase Noise -125 dBc/Hz @ 1-MHz oﬀset from 3.6 GHz Power Consumption 4 mA from 1.2 V supply

Table 3.1: Example oscillator spec

So that pulse-wave VCOs produce an amplitude of 1.57 (=π/2) times higher than that of LC-VCOs, i.e. the reduction of 3.9-dB phase noise. The detailed analysis and relevant measurements of pulse-wave VCOs with an automatic start-up loop and a digital amplitude control are presented in our included paper 4 [25] and paper 5 [45].

3.6 Hand Calculations for a Start Point

Given the requirements of oscillators as shown in Table 3.1, quick hand calculations can be done to obtain a start point for further optimization. For the LC-tank oscillator as shown in Figure 3.1, these calculations give rise to rough estimation of the size of the transistors (M1,2), the amount of bias current (IB), the values of the differential inductor (L) and the total capacitance (C). For a first-order analysis, phase noise equations based on time-invariant assump- tions can be used. Since the negative resistance (Rn) provided by cross-coupled switch pair devices exactly cancel the loss of the parallel resistance (Rp) of LC- tanks at the oscillation frequency ω 5, i.e. R = R , the impedance of LC-tanks o n − p (Figure 3.1) at the frequency ωo + ∆ω can be simplified as 1 z(ωo + ∆ω) = (3.28) 1/R + 1/R + j(ω + ∆ω)C + 1 n p o j(ωo+∆ω)L 1 = (3.29) j(ω + ∆ω)C + 1 o j(ωo+∆ω)L R ω p o (3.30) ≈ j2Q∆ω where Q is the Q-value of the LC-tank equal to Rp ωoC = Rp/ωoL. The above 1 1 1 equation is simplified based on the relationship of ∆x 2 when xo+∆X ≈ xo − xo ∆x<

z(ω + ∆ω) 2 i2 /∆f (∆ω) = 10 log | o | n (3.31) L 2 v2 ! sig 5It is assumed that it is at steady state with constant amplitude.

44 2 2 where in/∆f the PSD of noise current and vsig the mean square value of signal voltage. 1/2 means half of the noise power causes phase noise [44]. Noise currents include the contributions of the LC-tank loss Rp and active devices, which can be expressed using a noise factor F : i2 n = F 4kT/R (3.32) ∆f p Inserting (3.32) into (3.31), we can get ω2 kTF (∆ω) = 10 log o (3.33) L Q2∆ω2 2P sig 2 2 where Psig = vsig/Rp = Ao/(2Rp) and Ao is the amplitude of the voltage across LC-tanks.

Design Step Oscillator design involvs several trade-oﬀs and often require a long optimization procedure. In the following discussion we derive an initial design as the start point for further improvement based on hand calculations. First it is assumed that the Q-value of LC-tanks as Q = 10 (there is no problem to achieve a Q-value larger than 10 in nowadays CMOS processes.), the noise factor F = 3 and temperature T = 300 K (27o). 1) Given the phase noise requirement in Table (3.1) that (1 MHz) 125 dBc/Hz at 3.6 GHz and (3.33), we can obtain L ≤ − P 2.55 mW sig ≥ 2) Given P = A2/(2R ), A = 4/π I R 6 and I = 4 mA, we get sig o p o B p B R 196.04 Ohm p ≥ 3) Given Q = Rp/(ωoL)= RpωoC, we have the total inductance and capacitance of the LC-tank: L 0.87 nH ≥ C 2.26 pF ≤ 4) The proper start-up margin is necessary, so that the loop gain should larger than unit as gm Rp/2 1: ≥ g 10.2 mS m ≥ 7 5) Since gm = µnCoxIB W/L = KnIB W/L where Kn = µnCox , we obtain p W pg2 = m L Kn 6It is assumed the oscillator operates in current-limited region [13]. 7 Where µn is the mobility of charge carriers and Cox is the gate capacitance per unit length.

45 After the above five steps we obtain a quick start point. Although some as- sumptions and first-order analysis are adopted, it gives a reasonable estimation of noise performance. Further refinements are performed using simulators.

Chapter 4

Quantization Noise and Spurs in ADPLL

All-digital Phase Locked Loops (ADPLLs) have attracted great attention in the literature [30, 31, 61–81]. It makes use of the timing resolution of CMOS transistors instead of the voltage resolution, so that the CMOS process scaling-down leads to performance improvements due to faster devices. It can also save silicon area, shorten redesign time and enhance high programmability and integration- level, since most of the building blocks are pure digital such as loop ﬁlters, phase detectors and so on. On the contrary, analog PLLs encounter several design diﬃ- culties with process scaling due to lower voltage headroom and higher leakage.

4.1 Introduction

The ADPLL shown in Figure 4.1(a) works in a similar way as analog ones [37, 82– 84]. The phase detector (PD) compares the phase of the reference clock (REF) ΦR and that of the digital controlled oscillator (DCO) clock (CKV) ΦV , and the resulting phase error Φe is feed back to the DCO to control its frequency until it being locked. The diﬀerence lies in that all the signals are expressed as ﬁnite- length digital numbers instead of analog values, which allows use of the digital signal processing. The reference phase ΦR is estimated by the reference phase accumulator (RPA) by counting in CKR clock with an increment of FCW (frequency control word) in each clock as shown in Figure 4.1(b). The DCO phase ΦV includes two parts. The integer part ΦV,I is estimated by the variable phase accumulator (VPA) as shown in Figure 4.1(b). The fractional part ΦV,F is estimated by the TDC as shown in Figure 4.1(c). The VPA counts in CKV clock with an increment of 1 in each clock. When locked, the DCO frequency is FCW times of the reference clock CKR. As to noise performance, ADPLLs are not contaminated by noise and spurious tones originating from charge pumps as in the case of analog PLLs where the charge

49 RPA Phase Decter FCW ΦR Φe Loop Σ + CKV + Filter -

CKR ΦV =ΦV,I -ΦV,F Σ : Accumulator VPA FF : D Flip Flop ΦV,F 1 FCW : Frequency Control Word FF Σ + ΦV,I TDC REF CKR REF FF CKR CKV

(a)

TDC ΦV,F = 4/6

Variable Phase Accumulator (VPA) ΦV,I CKV

REF FCW = 4 ΦR Reference Phase 1 Accumulator (RPA) 0 CKR

(b) (c)

Figure 4.1: (a) Block diagram of ADPLLs and (b) phase accumulators and (c) the fractional variable phase

pump is usually the dominant contribution of performance degradation. The AD- PLL is constituted by a linear phase detector and noise-immune digital circuits. As long as the quantization induced phase noise can be suppressed, ADPLLs are the preferred option in the contemporary fully integrated radio systems, illustrating high programmability or flexibility for multi-mode applications and high compact- ness for SOC integration. There are two quantization scenarios in ADPLLs: phase estimation and oscillator frequency tuning as shown in Figure 4.2. Time-to-digital converters (TDCs) are used to reduce the quantization effect in phase estimation and Σ∆ modulators are commonly used to alleviate frequency tuning quantization. Special frequency fine tuning schemes [85–88] can also help to lessen frequency tuning quantization

50 FCW KDCO /s + Φe ΦR x + LPF(s) - 2. Frequency Tuning Quantization

ΦV

1. Phase Quantization

Figure 4.2: Quantization noise in ADPLL issues. As the CMOS process scaling down, both the resolution of TDCs and frequency tuning will be improved making the ADPLL be a promising candidate for RF applications compared to its analog counterpart.

4.2 ADPLL Noise Analysis: s-domain, z-domain and Time-domain s-domain

1. Φn,TDC 2. Φn,fres

+ ΦE ΦR x + + x LFP(s) + 2π/S ΦV - KDCO FCW 1/2π

Figure 4.3: S-domain model of the ADPLL

All building blocks of an ADPLL have digital interface, though some of them such as DCOs and TDCs are internally analog and custom-designed but their analog features are terminated at their interfaces. Hence signals are processed or encoded in the digital domain. The s-domain model can still be used to predict the ADPLL behaviors as long as the concerned oﬀset frequency is much lower than that of the sampling frequency i.e. the reference clock REF [62, 84]. The s-domain model is proposed in [62, 63], reorganized in Figure 4.3. The unit of KDCO in the Figure 4.3 is Hz/second, so there is a 2π in the model of the DCO to represent the conversion from frequency (Hz) to phase (Radian). There is a 1/2π after the phase detector (PD) to make the phase error be an unit-

51 less digital number. In the following discussion it is assumed LPF (s)= α, so that it is a ﬁrst-order type-I PLL loop. The closed-loop noise transfer function of TDC quantization noise is 1 H (s)= (4.1) cl,TDC 1+ s/α K DCO

It illustrates a low-pass feature with the 3-dB cut-off frequency at αKDCO/2π Hz. The roll-off is 20 dB/decade. So there are two ways to suppress TDC quantization noise: 1) reduce loop bandwidth and 2) improve TDC resolution. The first method is to suppress the conversion and the second one is to suppress noise source itself. The noise transfer function for reference clock noise is FCW H (s)= (4.2) cl,F ref 1+ s/α K DCO

It is also a low-pass function with the 3-dB cut-off frequency at αKDCO/2π Hz and the roll-off of 20 dB/decade. As seen, both reference noise and TDC quantization noise show up within the ADPLL band. Hence it is better to make a narrow band PLL if they are the dominant in-band noise contributions. In most case TDC quantization noise contribution is much higher than reference noises within the frequency range from kHz upto the ADPLL bandwidth [88]. At low frequency offsets, for example < 1 kHz, reference noise becomes the dominant contribution. The noise transfer function of DCO frequency tuning quantization noise is 2π 1 H (s)= (4.3) cl,F res α K 1+ s/α K DCO DCO

It is a low-pass function with the 3-dB cut-off frequency at αKDCO/2π Hz and 20-dB/decade roll-off. The contribution to phase noise can be reduced by using ∆Σ modulators to push quantization noise to high offset frequency [30, 63] or other special varactor design [85–88] to reduce the tuning step size. The impact of this quantization noise is usually smaller than TDC quantization noise [63]. The noise transfer function of DCO phase noise is

s/α K H (s)= DCO (4.4) cl,F res 1+ s/α K DCO which demonstrates a high-pass function with the 3-dB cut-off frequency at αKDCO/2π Hz and 20-dB/decade roll-off. Note that from the oscillator phase noise point of view, the ADPLL band should be as wide as possible. As expected there is a trade- off between DCO noise suppression and TDC noise suppression, hence it is useful to make the ADPLL bandwidth programmable in order to achieve the near optimal performance. Due to the digital feature, the ADPLL bandwidth can be easily made programmable by changing the gain of digital loop filters using shift registers.

52 z-domain The z-domain model is accurate [62, 89] for the digital systems as ADPLL, as shown in Figure 4.4.

+ ΦE ∆fR/fR 1/(1+z) x + LFP(z) ∆fV/fV KDCO FCW

1/(1+z)

Figure 4.4: Z-domain model of the ADPLL

The z-domain model can be related to the s-domain by the following approximation [62]: z = es/fR = ej2πf/fR 1+ s/f (4.5) ≈ R which results in s = f (z 1) (4.6) R − Since the s-domain model is straightforward to use and it is well approximated within the frequency of interest. The s-domain analysis is adopted in this work.

Time-domain The s-domain model is a linear model with high-order effects ignored. The s- domain model can be used in early design stages to quickly check the feasibility of specifications and figure out the bottleneck of performance. On the other hand time-domain models [90–92], which include high-order effects such as quantization, TDC nonlinearity, DCO tuning nonliearity and so on, should be utilized to predict the real performance of ADPLLs. Since signals are digital in ADPLLs, the time-domain model can be fulfilled using hardware description language such as Verilog and VHDL. The time-driven simulators can be adopted to perform simulation, saving simulation time considerably. Digital building blocks can be modeled in both register-transfer level (RTL) level or behavioral level depending on the trade-off between speed, accuracy and complexity. The RF analog building blocks such as TDCs and DCOs are modeled behaviorally. As the most importance parameter in DCO, phase noise is modeled as jitter [38, 63, 90]. 1/f 2 phase noise of DCOs is modeled as the accumulated jitter. While noise floor is modeled as the synchronous jitter. Figure 4.5 illustrates simulated phase noise of the DCO time-domain model where the simulation agrees with modeling.

53 −60

−70

−80

−90

−100

−110

−120 Phase Noise (dBc/Hz) −130

−140

−150

−160 103 104 105 106 107 108 109 1010 Frequency (Hz)

Figure 4.5: Phase noise (1/f 2) of a time-domain free-running DCO: -120 dBc/Hz phase noise at 1-MHz oﬀset from the 3.15-GHz center frequency and - 150 dBc/Hz noise ﬂoor

As to TDC models, both nonlinearity and quantization eﬀects can be modeled in behavioral models. The nonlinearity is model by making the quantization level not equally spanned. Figure 4.6 demonstrates the simulation results of the ADPLL time-domain model with diﬀerent ADPLL bandwidths.

4.3 Quantization Noise

As mentioned before two quantization eﬀects exist in ADPLLs: phase estimation quantization and frequency tuning quantization as shown in Figure 4.2. TDCs cannot resolve the phase smaller than its resolution, leading to the phase estimation quantization. The ﬁnite capacitance step size achieved in a CMOS process causes the frequency tuning quantization in DCOs. If it is assumed that the variation of quantizer (TDC and DCO here) inputs spans several quantization levels, the power of the resulting quantization noise can be expressed as (double-sided) [63]

(∆)2 σ2 = . (4.7) ∆ 12

54 −90

−100

−110

−120

−130 Phase Noise (dBc/Hz)

−140

−150

−160 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 Frequency (Hz)

200

180

160

140

120

100

Phase Error 80

0 0 50 100 150 200 250 300 Reference Cycle

Figure 4.6: (a) phase noise and (b) phase error from a time-domain model with different bandwidth: 40 kHz (blue), 100 kHz (gree) and 300 kHz (red). DCO phase nosie: -120 dBc/Hz @ 1-MHz offset and - 150 dBc/Hz noise floor. Ideal DCO frequency tuning. Ideal TDC.

55 where ∆ is the quantization step. This noise power is spread up to the half of the sampling frequency( fR the frequency of the reference clock CKR in this case) as

σ2 = ∆ . (4.8) L fR When ADPLLs are not yet locked, the previous assumption is always met. The phase noise contribution of TDC quantization noise is

∆ 2 = 2π TDC /12/f (4.9) LTDC T R V where ∆TDC is the TDC resolution and TV is the period of DCO clocks. The phase noise contribution of DCO frequency tuning noise is

= (∆ )2/12/f (4.10) LDCO freq R where ∆freq is the frequency step of DCO frequency tuning. The impact of quantization noise of DCOs can be reduced using ∆Σ modulators [63] or special varactor design [85–88]. As a result the quantization of TDCs is usually the dominant cause of in-band phase noise [63]. It is one of the hot topics in the literature [76, 93–106] to design high performance TDCs with high resolution. When ADPLLs are locked, the assumption is not valid anymore. The phase variation or the DCO control word variation is smaller than the quantization level at most of time. The resulting quantizer output may demonstrate a certain repeating pattern, leading to spurious tones in the spectrum of the ADPLL.

4.4 Spurious Tones

The quantization of TDCs and DCOs may lead to spurious tones in output spec- trums. The quantization eﬀects (both TDCs and DCOs), phase noise or environmental changes cause the DCO frequency to drift away the nominal frequency, producing a certain phase error in each reference clock cycle. Only when the accumulated phase error exceeds the TDC quantization step (∆TDC ) can the TDC resolve it and hence activate ADPLL loops to correct the phase error. After the correction, ADPLL loops keep quiet again until the new accumulated phase error is large enough to be resolved by TDCs. In this way, TDC outputs may demonstrate a certain repeating pattern as shown in Figure 4.7, producing spurious tones. Dither method can be adopted to suppress this sort of the spurious tones [68, 71–74, 107]. It perturbs the phase error in purpose, making it crossing the TDC quantization level more frequently. If the introduced perturbation noise degrades performance too much then noise cancellation methods should be utilized [68, 71, 73, 74] at the cost of design complexity. The non-linearity of TDCs is also the cause of spurious tones [107]. These spurious tones are located at the oﬀset frequency usually lower than the spurs

56 Phase Error code Error Phase

0 500 1000 1500 2000 Reference Clock Cycle

Figure 4.7: Phase error code demonstrating a certain pattern.

caused by TDC quantizations since the impact of the TDC non-linearity can only show up when the TDC inputs traverse the whole TDC dynamic range, which needs more number of reference clock cycles. The DCO clock CKV rotating method is proposed in [107] to address this kind of spurious tones.

4.5 Ill Condition: Steady-state Bandwidth Variation

When the ADPLL is locked, the variation of the phase error may much smaller than the TDC resolution, leading to such scenario where the TDC keep quiet at most of time. Then the gain of the quantizer (the TDC) is not one as being modeled in the s-domain model in the previous section but smaller than one. This conclusion can be forecasted by Figure 4.8 where the loop dynamics of the ADPLL are same for diﬀerent cuvers and the only diﬀerence is TDC resolution. As seen the ADPLL output spectrum illustrates a smaller loop bandwidth when the TDC resolution is increased.

57 −40 5 ps 10 ps 20 ps 40 ps −60

−80

−100 Phase Noise (dBc/Hz) −120

−140

−160 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 Frequency (Hz)

Figure 4.8: Phase noise when sweeping TDC resolution tres: 5 ps, 10 ps, 20 ps and 40 ps. DCO phase nosie: -100 dBc/Hz @ 1-MHz oﬀset. Ideal DCO frequency tuning. The PLL BW: 100 kHz.

4.6 Frequency Tuning Resolution

MASH ∆Σ Modulator To reduce the phase noise contribution of the discrete frequency tuning of DCOs, one method is using ∆Σ Modulators to push or shape low frequency noise to high frequency. The shaped noise is then ﬁltered by the 1/s eﬀect of DCOs. The noise transfer function (NTF) of a n order ∆Σ Modulator is

∆ω ∆ω ∆ω n −1 n −j 2 −j 2 j 2 NTF = 1 z = e fdth e fdth e fdth − − n h ∆ω i −j 2 ∆ω = e fdth 2j sin( ) 2f dth where fdth is the sampling frequency of ∆Σ Modulators. The spectrum of frequency tuning quantization noise (4.10) is shaped by the NTF and then the DCO’s 1/s effect. Hence the phase noise contribution is ∆2 1 π∆f 2n 1 (∆f)= freq 2sin (4.11) Ldth 12 f f ∆f 2 dth dth 58 Despite of the 1/s filtering effect, ∆Σ Modulators should be carefully designed in order to make sure shaped quantization noise do not raise the far-away noise floor [63].

DCO Fine Tuning Bank Resolution

wmin =120nm

n p

wmin +∆min =125nm c

Mini. Bank Basic Unit

Figure 4.9: Fine tuning arrangement

Another method to get a ﬁne tuning resolution is to use the arrangement as shown in Figure 4.9, which is presented in our included paper 6 [45] and paper 7 [88]. There are two devices with a small diﬀerence in size used. One is the minimum size (120nm in a 90nm process) allowed in processes. The other is the minimum size plus the minimum increment (5nm in a 90nm process). By doing in this way, the capacitance step is the delta capacitance (30 aF) of these two switched varactors. This method has no noise penalty as ∆Σ Modulators but attention should be paid in the layout stage to avoid mismatch.

59 t Amcos(ωmt) Aocos( KDCO Amcos(ωmt)dt+ωot) ∫0

KDCO

(a)

∆dB

ωoωm ωo ωo+ωm Spectrum

(b)

Figure 4.10: Measurement of the ﬁne tuning step

It is not easy to measure the small tuning step ( around 200 Hz) when DCOs are free-running, since the carrier frequency is drifting due to electronic noise or environmental changes. The drifted frequency can be larger than this small frequency tuning step. To address the difficulty, the narrow band modulation theory is explored. The tuning control of the DCO is modulated by a sinusoidal waveform 1 (Amcos(ωmt)) as shown in Figure 4.10(a). In the spectrum there are two sidebands around the main carrier as indicated in Figure 4.10(b). The power difference (∆dB) between the sidebands and the carrier is related to the tuning step KDCO of the DCO as ∆ dB 10 20 2fm KDCO = (4.12) Am The detailed information about ADPLL fine tuning design and measurements can be found in the included paper 6 [45] and paper 7 [88].

1The peak value of the sinusoidal wave is chosen to be smaller enough so that only the ﬁne tuning bank is active.

Chapter 5

Direct Digital-RF Polar Transmitter

Q a a

θ θ a·cos(ωot+θ) x 0 I PA PLL Polar Coordinate (a)

Suppress Harmonics I

o 90 + LPF a·cos(ωot+θ)

Q PA

PLL

(b)

Figure 5.1: (a) The polar transmitter and (b) the quadrature (IQ)transmitter

For RF transmitters polar architecture (Figure 5.1(a)) [31, 45, 88, 108–112] is

63 an effective solution in terms of the number of components (die area) and power efficiency, compared to quadrature (IQ) transmitters (Figure5.1(b)). No mixer is needed since frequency up-conversion is accomplished by PLLs, eliminating the harmonics caused by mixers. Switching mode power amplifiers (PAs) can be used instead of linear mode PAs, which are able to achieve higher efficiency. Especially in the contemporary wireless protocols with orthogonal frequency-division multiplexing (OFDM) schemes the high peak-to-average power ratio (PAPR) lowers the efficiency of the linear PAs considerably. The LO pulling issue can also be relaxed in polar transmitters since LOs and PAs demonstrate the same frequency modulation. The I/Q mismatch problem is also eliminated. However, challenges lie in AM/PM path delay mismatch [113] and baseband spectral expansion [114, 115]. In this chapter, we introduce briefly an all-digital polar transmitter based on an ADPLL and an phase sychronized ∆Σ modulator, which was published in our included paper 6 [45] and paper 7 [88]. All modulation is completed in the digital domain illustrating digital waveforms. The only analog signals appear at the interface to die pads where a band-pass analog filter suppresses shaped quantization noise and acts as both a matching network and differential-to-single-ended conversion.

5.1 Contemporary Transmitters: more digital GSM 1800 GSM 1900 Bluetooth GSM800 GSM900 UMTS GPRS EDGE HSPA CM 850 WCDMA CDMA2000 TD-SCDMA CDMA 800 CDMA CDMA P L2 GPS L1 GPS WiMax WiFi LTE 1 2

Freq 700 1200 1700 2200 2700 3200 3500 (MHz)

WCDMA 850, UMTS 850

Figure 5.2: Mobile standards

Several mobile communication standards exist nowadays in the frequency range from 700 MHz to 3500 MHz, as shown in Figure 5.2. The need of covering multiple standards from the market leads to the transmitters with high programmability or ﬂexibility in frequency selection (from 700 MHz to 3500 MHz), modulation scheme

64 (GMSK, QPSK, QAM and so on) and output power level (more than 10 dB back off). Those programmabilities are relatively easy to fulfill in the digital domain or digitally-intensive transmitters. On the other hand, CMOS process down-scaling brings several difficulties to tranditional analog designs such as reduced voltage head room and high leakage current. Hence long redesign time is needed to move analog designs toward an advanced process. However, digital circuits can benefit from the scaling in terms of speed, matching, power consumption and integration level. As far as process scaling is concerned, more digital circuits1 or digital signal processing should be adopted in RF transmitters to replace analog circuits [31]. So the technology direction for RF transmitters is to move digital signal processings closer to antennas.

Band Pass RF Baseband Σ∆ MOD

4fo (a)

Low Pass Baseband Σ∆ MOD AND RF

fo (b)

Baseband RFDAC RF

fo (c)

Figure 5.3: The frequency up-conversion in digital transmitters

In the literature several digitally intensive transmitters have been proposed, based on polar architecture [30, 31, 45, 88, 109, 112] or IQ [114, 116–119] architecture. Low-pass or band-pass ∆Σ modulators are widely used in digitally intensive transmitters to push quantization noise away interesting bands. The frequency up- conversion function of mixer can be achieved by band-pass ∆Σ modulators (Figure 5.3(a)), however the modulator should operate at higher frequency than the carrier frequency usually four times higher [112, 116]. For the architecture with low-pass

1Digital circuits here means both standard cells or analog circuits with the digital interface.

65 ∆Σ modulators the frequency up-conversion is fulﬁlled by mixers that can be simple AND gates (Figure 5.3(b)) [88, 112] or multiplexers [116]. Other researchers combine the functions of analog mixers and digital-to-analog converters (DACs), yielding the RF-DAC (Figure 5.3(c)) solution [120–122]. All the up-conversion methods in Figure 5.3 take baseband signals directly without the need of DACs. For the architecture with ∆Σ modulators, switching mode PAs can be used to achieve high power eﬃciency.

5.2 The Proposed All-digital Polar Transmitter

For RF transmitter design there are several aspects needed to be taken into account such as LO pulling, spectral purity and power eﬃciency.

LO Pulling The LO pulling is caused by PAs with large power transmission and certain modulation. It pulls LOs away the nominal frequency. One solution is to operate LOs at a frequency far away from PAs frequency [39]. For polar transmitters the LO pulling issue is mitigated since the LO is also modulated as PAs instead of providing a ﬁxed frequency carrier.

Spectral Purity The spectral purity means the output spectrum should be conﬁned within certain range. The impact to adjacent channels due to harmonics, spurious tones 2 and noise ﬂoor should be minimized. Adjacent-channel power rejection (ACPR) is used too evaluate the spectral purity [123]. As far as PAs are concerned, the linearity performance should be optimized to increase spectral purity or reduce spectral regrowth[124].

Power Efficiency The power efficiency is one of the most important parameters for PA designs. For constant envelop modulation applications, linear PAs are used. The efficiency of linear PAs is reduced considerably when the envelop is varying and hence switching mode PAs are preferred in this case.

Proposed All-digital Polar Transmitter The proposed all-digital polar transmitter is shown in Figure5.4. The spectral purity performance is improved by the combination of an one-bit ∆Σ modulator

2Harmonics are generated by modulators and PAs while spurious tones are from mixers, oscillators, parasitic resonator and nonlinearity in PAs [39].

66 Digital Base Phase Amplitude Band Modulation Modulation P Envelope ρ MatchingFilter&

Digital DCO Phase dθ CKV Low Pass SD PLL Vdiff θ dt Σ∆ MOD Loop

N ADPLL

CKVD ∆t CKVD

Trim. Pulse ClassD Delay Shaper PA

Figure 5.4: The proposed all-digital polar transmitter

and an switching mode class-D PA. The switching mode PA can be regarded as a linear stage for digital signals [125]. Hence the linearity of the transmitter is determined by the ∆Σ modulator. A well-designed one-bit ∆Σ modulation is linear [126] which assures the linearity property of the proposed transmitter and hence the spectral purity. As to the power efficiency, the switching mode PA demonstrates better efficiency compared to its linear counterparts. The operation principle of the proposed transmitter in Figure 5.4 is explained as follows. Phase information θ modulates the carrier frequency directly through the ADPLL. The output of the ADPLL CKV is a phase modulated clock. The ∆Σ modulator performs amplitude modulation by taking CKV as an oversampling clock so that the output SD is phase synchronized to CKV except a fixed delay tPD caused by the propagation delay of the ∆Σ modulator as shown in the waveforms of CKV and SD in Figure 5.5(a). SD contains both phase and amplitude information. However the power around the carrier frequency fs or fCKV is still quite low while most of the power is located at the baseband as shown in Figure 5.5(b). To increase the power at fs, a pulse shaper (AND gate) is used acting as mixers to upconvert the baseband power to fs. The delay tPD between the transition edges of SD and CKV should be compensated before the pulse shaper, otherwise power efficiency would be lowered and more harmonics would be produced. This is accomplished by the delay block (Trim. Delay in Figure 5.4). As seen in Figure 5.5(c), the power around fs is raised after the use of the pulse shaper. The H-bridge arrangement or the differential style further increase the power around fs by 3 dB in the ideal case and suppress the power at DC and other odd harmonics as shown in Figure 5.5(d).

67 tPD

CKV SD

CKVD CKVD

P = CKVD & SD N = CKVD & SD

Vdiff = P - N

Vout BPF (a)

signal sinc q. noise alias

Freq. 0 fs=fCKV 2fs (b) The spectrum of SD

Freq. 0 fs=fCKV 2fs (c) The spectrum of P and N

On-chip filter

Freq. 0 fs=fCKV 2fs

(d) The sepctrum of Vdiff

Figure 5.5: The operation of the proposed all-digital polar transmitter

As the last stage, the band-pass ﬁlter removes shaped quantization noise and the harmonics, generating the ﬁnal analog output Vout as shown in Figure 5.5(a).

68 5.3 Phase Modulation: ADPLL with two-point modulation

y[k]

+ FCW + Σ + α ∆f[i]

TDC & Σ BW

(a)

y[k]

+ FCW Σ + α + ∆f[i]

TDC & Σ BW

(b)

y[k] Two point Modulation 1 NG BW BW + + FCW + Σ + α + ∆f[i]

TDC & Σ BW

(c)

Figure 5.6: The two point modulation scheme of the ADPLL

As mentioned before, phase or frequency modulation is accomplished by the ADPLL. The modulating data is added to FCW (Figure 5.6(a)), resulting in the frequency modulation of the ADPLL. Based on the z-domain model [62, 89] the transfer function of the path from y[k] to ∆f[i] is illustrated as αK /(z 1) H(z)= DCO − (5.1) 1+ αK /f 1/(z 1) DCO R − where α is the scale factor, KDCO is the gain of the DCO. As shown in Figure 5.6(a), the transfer function shows a low-pass response in the frequency domain,

69 meaning it cannot modulate wideband baseband signals. The two point modulation scheme [30] can be adopted to overcome this limitation. The ADPLL with the two point modulation is illutrated in Figure 5.6(c). The z-domian transfer function of the additional path from y1[k] to ∆f[i] is K H(z)= DCO (5.2) 1+ αK /f 1/(z 1) DCO R − The frequency reponse of the additional path (Figure 5.6(b)) demonstrate a high pass feature shown in Figure 5.6(b). As long as the cut-oﬀ frequency of these two paths can be matched, an all-pass frequency response can be achieved as plotted in Figure 5.6(c). The z-domain total transfer function is K /NG (z 1+ α NG) H(z)= DCO − (5.3) z 1+ αK /f − DCO R The extra modulation path will introduce a zero which cancels the pole resulting a all-pass transfer function when K NG = DCO (5.4) fR Hence, besides phase noise the modulation accuracy is impacted by the estimation of the KDCO. Several techniques have proposed in the literature to accurately estimate KDCO such as the LMS method [127].

5.4 Amplitude Modulation: low-pass ∆Σ modulator

E(z)

+ 1 U(z) + V(z) Z - 1 + -

Figure 5.7: The linear z-domain model of the ﬁrst-order low-pass ∆Σ modulator

Amplitude modulation is performed using a low-pass ﬁrst-order one-bit ∆Σ Modulator. The z-domain model of the ∆Σ Modulator is shown in Figure 5.7. The signal transfer function (STF) from U(z) to V (z) is written as

V (z)= U(z) z−1 (5.5) 70 which shows one clock delay. The noise transfer function (NTF) of quantization noise E(z) in the Figure 5.7 can be expressed as Q(z)= E(z) (1 z−1) (5.6) − As expected it demonstrates a high-pass frequency response. Low frequency noise is pushed out of interesting bands and then suppressed by ﬁlters. After replacing z with ej2πfT , the PSD of quantization noise ouput can be expressed

S (f)=(2 sin(πfT ))2 S (f) (5.7) Q E

Noise Transfer Function Transfer Noise 2

0 0 0.2 0.4 0.6 Normalized Frequency (f/fs)

Figure 5.8: The noise shaping function of the ∆Σ modulators with diﬀerent orders.

The order of ∆Σ Modulators impacts the noise shaping property, causing different in-band and out-of-band behaviors as shown in Figure 5.8. In this case, a ﬁrst-order modulator is chosen since it has simple implementation and meets requirements. As mentioned, the combination of the ∆Σ Modulator with the switching mode PA illustrates a linear operation, since the switching PA is linear for digital inputs and the ideal implementation of the ∆Σ Modulator assures the linearity. How- ever, in a real design the linearity can be degraded by device mismatch and other imperfection [128, 129].

71 5.5 H-bridge Class-D PA Stages and on-chip Matching Filter

P Vout k PAD

Vdiff N

H-bridge Class-D PA Filter & Matching

Figure 5.9: H-bridge Class-D PA Stages and on-chip Matching Filter

The H-bridge or differential style class-D PA stage is adopted as shown in Figure 5.9. The differential style can increase the power at the fundamental tone by 3 dB ideal (compared to the single-ended method [112]). At the same time the differential style suppresses the DC power and the second-order harmonic, alleviating the on- chip filter requirement. The device size of the class-D PA is optimized for power efficiency. The on-chip filter filters out shaped quantization noise and other unwanted harmonics, lessening the contamination to adjacent channels. Digital waveforms are now converted to analog, therefore this filter is the interface between the digital domain and the analog domain. It also acts as the matching network between off- chip loads and the transmitter, diminishing the impact of package parasitics. The differential signal is transformed to the single-ended one by this filter.

Chapter 6

Summary and Future Work

6.1 Summary

In this thesis, we first study the RF CMOS oscillator phase noise performance optimization through core device sizing and topology improvement. Then the ADPLL with a fine frequency tuning is proposed and the noise analysis is discussed. Fi- nally it presents an all-digital polar transmitter showing a improved architecture. A number of design techniques have been proposed and verified in three oscillator and one transmitter implementations. The basics of phase noise and jitter are introduced, and the relation between phase noise and jitter , how phase noise propagates in the system and how to derive the phase noise specification are described. A fast phase noise measurement method for free running oscillators is proposed. This method is accurate for most RF integrated oscillators with only the need of a single spectrum analyzer without other assistant circuits such as phase detectors, delay lines or mixers. Phase noise of LC-tank oscillators is optimized through core device sizing. Closed-form expressions are derived based on the linear time-variant (LTV) ISF [11] theory and verified in both SepctreRF simulations and real implementation in 0.18-µm CMOS process. It is concluded that the minimum size of core device (the switch pair devices) is preferable for both 1/f 2 and 1/f 3 phase noise reduction purpose. A modified topology (PW-VCO or class-C) is proposed. The bias noise is decou- pled by tail capacitors. The phase noise contribution due to core devices is reduced as the drain current is shaped into a pulse wave. The PW-VCO demonstrates a theoretic reduction of 3.9 dB in phase noise at 1-MHz offset compared to LC-tank oscillators without considering the reduction of bias noise. Measurements of the design in a 0.18 µm CMOS process illustrates that phase noise can be reduced in the range of 5-10 dB at 1-MHz offset from different carrier frequency. The ADPLL with a small frequency tuning step and wideband two-point FM is designed in a 90-nm CMOS process. The small frequency tuning step is achieved

75 by making use of the capacitance difference of two transistors with slightly different width (5 nm in 90-nm CMOS process). By doing so the achieved capacitance step is 30 aF. The small frequency step (around 200 Hz) of the free-running oscillator is measured based on the narrow-band frequency modulation theory in order to conquer the frequency drift problem. An improved transmitter architecture is proposed based on the designed AD- PLL and a phase synchronized ∆Σ modulator. It is a polar transmitter with the differential H-bridge class-D PA stages. The ADPLL with high programmability is adopted to accomplish the phase noise modulation due to the low noise and low spurious output. The amplitude modulation is done by using a first-order low-pass ∆Σ modulator since it is inherently linear, relaxing the need of a complex calibration. The differential H-bridge class-D PA stages increases the power of the fundamental tone and suppresses the power at DC and even harmonics. The on-chip filter filters the quantization noise, converts the differential-end to the single-end and also pro- vides a matching to the antenna. Measurements of the design fabricated in a 90nm CMOS process illustrates this improved architecture achieve good power efficiency, small area with decent modulation accuracy.

6.2 Future Work

One technology direction is digitally-intensive RF design. To go towards it, oscillators will be purely digital code controlled instead of analog voltage controlled, becoming a DCO. Phase noise reduction is still a future attempt never ending. Other efforts will be paid on how to achieve a fine frequency tuning step with a wide frequency tuning range and how to achieve a linear DCO gain. For ADPLL design the techniques to reduce different types of spurs and increase the design automation as well as the high resolution TDC deserves to the further investigation. The wideband all-digital transmitter is definitely a very interesting topic since several challenges are still existing. For example how to achieve a wideband modulation with reasonable modulation accuracy if the polar architecture is adopted, how to keep the efficiency and linearity for PAs driven by high PAPR signals and how to remove the shaped quantization noise if several standard signals exist simultaneously.

Appendix A

Phase spectral density and voltage spectral density

At moderate oﬀset frequencies the normalized PSD can well approximate the real phase noise spectrum if the phase variation is small, ϕ(t) << 1 rad. With the | | condition of a small phase variation, the equation vo(t) = cos[ωot + ϕ(t)] can be approximated:

vo(t)= cos(ωot)cos[ϕ(t)] sin(ωot)sin[ϕ(t)] − (A.1) cos(ω t) ϕ(t)sin(ω t) ≈ o − o where the amplitude noise is ignored and ωo is the carrier frequency. Now let’s consider the situation when ϕ(t) is a single tone, ϕ(t)= ϕp sin(ωmt) where ϕ << 1. Substitution of ϕ(t) into equation (A.1) gives | p|

vo(t) cos(ωot) ϕpsin(ωmt)sin(ωot) ϕ ≈ − (A.2) cos(ω t) p cos[(ω + ω )t] cos[(ω ω )t] ≈ o − 2 { o m − o − m } i.e. the output signal have two side-bands at the frequency of ωo + ωm and ωo ωm 2 − respectively with a power of ϕp/8. Then the normalized phase noise at the frequency ωo + ωm caused by the single tone ϕ(t) is calculated according to the deﬁnition - noise power density normalized to the carrier power as:

ϕ2/8 ϕ2 (∆ω)= p = p (A.3) L 1/2 4

As ϕ(t) is a single tone (ϕ(t)= ϕ sin(ω t)), the PSD is p m ϕ2 S (∆ω)= p . (A.4) ϕ 2

79 Together with equation (A.3) and equation (A.4), we obtain the following relation: S (∆ω) (∆ω)= ϕ . (A.5) L 2 The approximation in equation (A.5) is accurate as long as the phase deviation is small and the oﬀset frequency ∆ω is moderate.

80 Appendix B

Jitter and phase noise

In this appendix, we are going to discuss the relation among jitter, the noise ﬂoor (frequency independent) and 1/f 2 phase noise of oscillators.

B.1 Synchronouse jitter and noise ﬂoor

∆t[1] ∆t[2] Time Error Distribution

Actual timestamp 0 tjs [1]=To+∆t[1] tjs [2]=2To+∆t[2]

Ideal timestamp 0 To 2To

Figure B.1: Synchronous jitter.

The noise ﬂoor is related the synchronous jitter [38, 63] in the time domain. The synchronous jitter occurs in driven systems where the output is the response of the input. As seen in Figure B.1, the current time error ∆t[i] has nothing to do with other time errors and the current timestamp tjs[i] equals

tjs[i]= iTo + ∆t[i] (B.1) where To is the period of the ideal input signal. It is assumed the time error is caused by thermal noise or white Gaussian stationary or T-cyclo-stationary noise process [38]. Given the double-side noise ﬂoor of phase noise curve and the sample frequency f (f = 1/T is the frequency of L o o o 81 the input), the power of the time error can be expressed as

T 2 σ2 = f o (B.2) js L o 2π where the term To/2π converts a phase error to a time error. Based on the statistics theory, the RMS value is identical to the standard deviation for white Gaussian noise and hence the RMS synchronous jitter is

T σ = f o (B.3) js L o 2π p B.2 Accumulating jitter and 1/f 2 phase noise

∆t[1] ∆t[2] Time Error Distribution To

Actual timestamp 0 tja [1]=To+∆t[1] tja [2] = tja [1]+To+∆t[2]

Ideal timestamp 0 To 2To

Figure B.2: Accumulating jitter.

The 1/f 2 phase noise region is related to the accumulating jitter [38, 63]. The accumulating jitter happens in autonomous systems such as oscillators. From its name it can be seen that the eﬀect is accumulating along time so the current timestamp tja[i] is based on the previous one tja[i 1] as demonstrated in Figure B.2: − j=i t [i]= t [i 1] + T + ∆t[i]= i T + ∆t[j] (B.4) ja ja − o o j=1 X The 1/f 2 phase error can also be expressed in terms of the accumulating jitter ja as j (t) ϕ(t) = 2π a (B.5) To where j=i

ja(i)= ∆t[j] (B.6) j=1 X 82 The value of the accumulating jitter ja(t) is the integration of synchronous jitters ∆t[i] i.e. like the case of random walk. Assume that the synchronous jitters ∆t[i] is a white Gaussian stationary or T- cyclo-stationary noise process (this excludes ﬂicker noise). Then its single-sided power spectral density (PSD) is

S (f) = 2 c (B.7) js where c is constant in the frequency of interest. Phase noise is the PSD of phase error (B.5). With (B.6) and (B.7), the 1/f 2 phase noise equals 1 (f)= (2πf )2S (f) L 2 o ja (B.8) 1 1 f 2 = (2πf )2 S (f)= c o . 2 o (2πf)2 js f 2 where Sja(f) is the PSD of the accumulating jitter (B.6).

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