Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter JIAN CHEN Doctoral Thesis in Electronic and Computer Systems Stockholm, Sweden 2012 TRITA-ICT/ECS AVH 13:03 KTH School of Information and ISSN 1653-6363 Communication Technology ISRN KTH/ICT/ECS/AVH-13/03-SE SE-164 40 Kista, Stockholm ISBN 978-91-7501-643-6 Sweden Akademisk avhandling som med tillst˚and av Kungl Tekniska h¨ogskolan framl¨agges till offentlig granskning f¨or avl¨aggande av teknologie doktorsexamen i Elektronik och Datorsystem onsdag den 13 mars 2013 klockan 9.00 i Sal D, Forum 120, Kungl Tekniska h¨ogskolan, Kista 164 40, Stockholma. c Jian Chen, September 2012 Tryck: Universitetsservice US AB iii Abstract In recent years all-digital or digitally-intensive RF transmitters (TX) have attracted great attention in both literature and industry. The motivation is to implement RF circuits in a manner suiting advanced nanometer CMOS processes. To achieve that, information is encoded in the time-domain rather than voltage amplitude. This enables RF design to also benefit from CMOS process scaling. In this thesis an improved architecture of a digitally-intensive transmitter is proposed and validated experimentally. The techniques to lower oscillator phase noise and all-digital phase-locked loop (ADPLL) quantization noise are discussed and proved by both simulation and measurements. The impact of device sizing on 1/f 2 noise is analyzed and validated by measurements. Seven oscillators in 180-nm CMOS with the same LC-tank, operation frequency and power consumption but different core device width are compared. The conclusion clarifies the different suggestions on device sizing in the literature. It is illustrated that tail noise contribution is strongly positive dependent to core device sizing, while the contribution of core devices themselves is weakly dependent. Measurements demonstrate that there is a 14-dB phase noise increase when sizing core devices from 40 µm to 280 µm in the case of noisy tail current. If tail current is clean, the increase is only 4 dB. For 1/f 3 phase noise, the investigation reveals that the capacitance modulation is the dominant factor accounting for the 1/f or flick noise up- conversion, which is proved by measurements of 180-nm CMOS designs. A class-C oscillator with ensured start-up and constant amplitude is pre- sented. It achieves a 3.9-dB phase noise reduction in theory and 5-dB reduc- tion in measurements, compared to a conventional LC-tank oscillator operat- ing at the same frequency and power. With the help of a digital bias voltage and bias current control loop, a 191 Figure-of-Merit (FoM) is achieved, show- ing the ability for low power and noise application. The previous oscillator optimization techniques have been applied in de- signing a digital controlled oscillator (DCO) for an ADPLL. A fine tuning varactor is proposed to reduce quantization noise, achieving a frequency step of only several hundreds Hz. In order to measure this small frequency step when the DCO is free-running, a method based on the narrow-band frequency modulation (FM) theory is proposed. The ADPLL wide-band FM is fulfilled by using a digital two-point modulation so that the modulation bandwidth is not limited by the ADPLL loop dynamic. Finally an all-digital polar TX is proposed based on an improved archi- tecture. The ADPLL is used for FM while a one-bit low-pass Σ∆ modulator using the phase modulated ADPLL output as the clock accomplishes ampli- tude modulation. A simple AND gate is adopted to increase the fundamental power as mixers. A class-D power amplifier stages deliver 6.8-dBm power to antenna through a on-chip band-pass pre-filter. The filter also acts as single-ended to differential-end conversion and matching network. keywords: all-digital, digitally-intensive, frequency modualtion, phase modulation, amplitude modulation, polar, transmitter, oscillator, digital con- troled oscillator, DCO, VCO, voltage controled oscillator, class-C oscillator, class-D PA, ADPLL, phase noise, RF, CMOS. Acknowledgement It is a long but exciting journey (since 2006) to reach the destination of a PhD study. I would like to take this opportunity to appreciate sincerely all the people helping me during the road, although I might forget their names due to my bad memory. First I would like to thank my supervisors Prof. Li-Rong Zheng, Prof. Hannu Tenhunen and Prof. Dian Zhou for giving the opportunity to study at KTH, sup- porting me along the way and sharing with me their knowledge. Special thanks go to my technology supervisor Dr. Fredrik Jonsson, who opens the door of RF analog circuits for me, inspires me to progress by his deep insights and intuitive understanding on this field, and walks beside me during the way. The PhD journey would not be of such great fun if without his knowledge and advice. I wish to thank Dr. Qiang Chen for sharing his experience and suggestions for both work and life. I would like to thank Prof. Axel Jantsch, Agneta Herling, Alina Munteanu and Robin Gehrke for their support and assistance, and Prof. H˚akan Olsson for interesting discussion. I also want to thank all colleagues at KTH for their help who have made the PhD more enjoyable by complaining together and entertaining talks during lunch time: Geng Yang, Botao Shao, Dr. Huimin She, Qiansu Wan, Liang Rong, Jue Shen, Jie Gao, Yi Feng, Li Xie, Zhiying Liu, Jian Liu, Zhi Zhang, Peng Wang, Ning Ma, David S. Mendoza, Ana L´opez Cabezas, Dr. Zuo Zhou, Qin Zhou, Jia Mao, Zhai Chuanying, Xueqian Zhao, Pei Liu, Ming Liu, Yasar Amin, Zhibo Pan, Shaoteng Liu, Yajie Qin, Xiaolong Yuan, Dr. Jinliang Huang, Dr.Jinfeng Du, Dr. Majid Baghaei Neijad, Dr. Saul Rodriguez Duenas, Dr. Roshan Weerasekera and Assoc. Prof. Zhonghai Lu. I also would like to express my sincere gratitude to Assoc. Prof. Svante Signell for reviewing the thesis, Prof. Georges Gielen from Katholieke Universiteit Leuven as my opponent, as well as Dr. Sven Mattisson from Ericsson, Assoc. Prof. Robert Bogdan Staszewski from TU Delft, Prof. Peter H¨andel and Prof. Mark Smith for serving as my committee members. I performed this PhD project together with Catena Wireless Electronics AB, Kista and after 2010 I fully worked there since I finished the PhD study except the defense. I sincerely thank my industry supervisors: Mats Carlsson and Dr. Char- lotta Heden¨as for their invaluable discussion. Also special thanks to Jan Rapp, Kav´eKianush and Rien Geurtsen for their support during writing the thesis and v vi impressive talks, Paul Stephansson for cooperating an ADPLL project, Fredrik Pusa and Andreas Drejfert for the fun time together, Magnus Bohman and Giti Amozandeh for reviewing design, Rob Visser and Marcel van de Gevel at Delft for reviewing a manuscript, and all other colleagues for your help during that period. Since 2012, I work at Ericsson, Kista where I would like to thank all my colleagues and my manager Ali Ladjemi for helping me to involve into the new place, answer- ing my questions regarding to both work and life, encouraging me to pursue new technology, and sharing the fun time during work and Friday Fika. Finally I would like to thank my family, my wife, my parents, and my brother for your unconditional love and support, and for always encouraging me. I also want to thank my mother in-law for helping us to take care of my small son. You are always my motivation to move forward. Abbreviations ACPR adjacent channel power ratio ADC analog to digital converter ADPLL all digital phase locked AM amplitudemodulation ASIC application specific integrated circuit ASK amplitude shift keying AWGN additive white Gaussian noise BER biterrorrate BW bandwidth CKR sampled reference clock CKV digitally-controlled oscillator clock CMOS complementary-metal-oxide semiconductor CNR carriertonoiseratio DAC digital-to-analog converter DCO digitally-controlled oscillator DSP digital signal processing ECG electrocardiography EEG electroencephalography FCW frequency control word FM frequencymodulation FoM figure of merit FPAA field-programmable analog array FPGA field-programmable gate array FSM finitestatemachine GMSK Gaussian filtered mnimum shift keying IC integratedcircuit IoT Internet-of-things ISF impulse sensitivity function IQ inphasequadrature KTH Royal Institute of Technology KDCO digitally-controlled oscillator gain LC-VCO LC-tank voltage-controlled oscillator LMS least-meansquare vii viii LNA lownoiseamplifier LTE long-term evolution LTI linear time-invariant LTV linear time-variant LO localoscillator MEMS micro-electro-mechanical systems NTF noise transfer function NMF noise modulation function OFDM orthogonal frequency division multiplexing PA power amplifier PAPR peak to average power ratio PM phasemodulation PLL phaselockedloop PSD powerspectraldensity PVT process voltage temperature PW-VCO pulse-wave voltage-controlled oscillator QoS qualityofservice REF referenceclock RF radiofrequency RF-DAC radio frequency digital-to-analog converter RFID radio frequency identification RX receiver SDR software-defined radio SoC system-on-chip SSB singlesideband TDC time-to-digital converter TX transmitter VPA variable phase accumulator VCO voltage-controled oscillator WCDMA wideband code division multiple access WIMAX worldwide interoperability for microwave access WLAN wireless local area network Contents Contents ix List of Figures xi 1 Introduction 5 1.1 Digitally-intensiveRFDesign . 7 1.2 ThesisInvestigationScope. 8 1.3 ThesisOrganization ........................... 11 1.4 IncludedPapersandContribution . 12 2 Phase Noise and Jitter 17 2.1 DefinitionandMetrics . 17 2.2 PhaseNoisePropagationinSystems . 20 2.3 PhaseNoiseRequirementofOscillators . 22 2.4 FastOscillatorPhaseNoiseMeasurement . 25 3 PhaseNoiseOptimizationforCMOSLCOscillators 29 3.1 LargeSignalAnalysis .......................... 29 3.2 Phase Noise Sources and Conversion Mechanisms . 33 3.3 Device Sizing for 1/f 2 PhaseNoise................... 38 3.4 Sizing for 1/f 3 PhaseNoise ....................... 39 3.5 Pulse-waveorClass-COscillator . 41 3.6 HandCalculationsforaStartPoint . 44 4 QuantizationNoiseandSpursinADPLL 49 4.1 Introduction...............................