Xilinx Smpte 2022 Video Over Ip Innovations: Hardware, Tools, Ip, and Reference Design Accelerate Development
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BROADCAST SMPTE 2022 VIDEO OVER IP FLEXIBLE, HIGH-CAPACITY SDI-TO-ETHERNET BRIDGE FOR COST-EFFECTIVE CONVERGENCE OF BROADCAST VIDEO AND LAN/WAN NETWORKS XILINX SMPTE 2022 VIDEO OVER IP INNOVATIONS: HARDWARE, TOOLS, IP, AND REFERENCE DESIGN ACCELERATE DEVELOPMENT Broadcast Market Challenges Establishing live feeds from in-field cameras to the studio and out to audiences no longer requires complex, video-only connections and networks. High-capacity local area and wide • Economic and market conditions put high area networks have created the opportunity to packetize and carry video using Internet priority on reducing CAPEX and OPEX Protocol. Xilinx FPGAs are accelerating this convergence of data and video worlds by uniquely • Converging SDI with existing Internet enabling high-performance, high-capacity bridging between SDI and Ethernet. Protocol (IP) networks introduces Equipment manufacturers are taking advantage of the Xilinx SMPTE 2022 standard-based interoperability issues innovations and development platform to shorten time to market for next-generation, highly interoperable video over IP equipment. The resulting designs offer superior density, with the • Standards for transporting video over IP ability to carry multiple channels of video over a single link or cost-effectively carrying data are changing rapidly (moving target) along with video. The high IO capabilities of Xilinx FPGAs support more video devices, 3D • Manufacturers need to deploy quickly, to content, and higher resolutions for Super Hi Vision and 4K2K. speed convergence of video and data SMPTE 2022 Video over IP Standards To enable the transport of compressed and uncompressed video over 1Gbps and 10Gbps Xilinx Solution Ethernet networks, Xilinx is focused on: • Performance and power of programmability • SMPTE 2022-1 “Forward Error Correction for Real-Time Video/Audio Transport Over IP let FPGAs uniquely bridge between SDI Networks” and Ethernet worlds • SMPTE 2022-2 “Unidirectional Transport of Constant Bit Rate MPEG-2 Transport Streams on IP Networks” • High-channel bandwidth and capacity drive • SMPTE 2022-5 “Forward Error Correction for High Bit Rate Media Transport over IP Networks” up density for support of 3D, Ultra HD and higher aggregation solutions • SMPTE 2022-6 “High Bit Rate Media Transport over IP Networks” • Support for emerging industry standards Note: The SMPTE 2022-5 and SMPTE 2022-6 draft standards have yet to be ratified by SMPTE, and are (SMPTE 2022-1,2,5,6) maximizes therefore subject to change. interoperability • Development platform (hardware, tools, IP, reference designs) dramatically shortens equipment design time BROADCAST SMPTE 2022 VIDEO OVER IP XILINX FPGA-BASED SMPTE 2022-5/-6 SYSTEM SD/HG/3G CH 1 RX SD/HG/3G CH N RX SD/HG/3G CH 1 TX SD/HG/3G CH N TX Triple-Rate Deserialize Triple-Rate Deserialize Triple-Rate Triple-Rate Format Det Format Det Serializer Serializer SD/HD/3G RX Cores SD/HD/3G TX Cores FEC TX TX Buffer RX Buffer Time Recovery Engine Controller Controller Rate Gen VCXOs SMPTE 2022-5/-6 RX LogiCORE SMPTE 2022-5/-6 Timestamp and FEC RX RTP TX LogiCORE RTP Framer Engine Parser DDR3 AXI Memory 10G MAC AXI4 AXI4 Memory Controller AXI4 LogiCORE Microblaze Soft Processor/ Xilinx FPGA Embedded Hard Processor Xilinx SMPTE 2022 Video over IP System • Supports multiple channels of SD/HD/3G-SDI (up to 8 today) • Handles Internet packet drops and out-of-order packet handling for • SMPTE 2022-6-2009 packetization and de-packetization support IP reception – Automatic recognition of SDI format to be packetized • Timestamp generation and extraction • SMPTE 2022-5-2009 FEC support with block aligned and non-block • Memory controller using Xilinx AXI-4 Memory Controller aligned matrices – Rx with FEC requires approximately 40 Gbps memory bandwidth • IP firewall and handshaking of standard Ethernet protocols – Tx with FEC requires approximately 20 Gbps memory bandwidth • Handles SD/HD/3G outages during IP transmission • Stream monitoring and selection of FEC matrix parameters on a stream by stream basis Accelerated Productivity Developers can get started today and shorten time to market with the Xilinx Broadcast Connectivity Kit, Xilinx ISE Design Suite tools, and Xilinx broadcast intellectual property (IP). A reference design is available, to integrate the hardware and IP with a memory subsystem. For more information, please contact [email protected]. Available System Components • Virtex-6 FPGA Broadcast Connectivity Kit • Triple-Rate SDI LogiCORE IP • SMPTE2022-5/6 LogiCORE IP • MicroBlaze Soft Processor Core • 10 Gigabit Ethernet MAC LogiCORE IP • AXI External Memory Controller LogiCORE IP • 10 Gigabit Attachment Unit Interface (XAUI) LogiCORE IP Take the NEXT STEP To request a demo, please contact [email protected]. For more information about broadcast resources, please visit www.xilinx.com/broadcast. Corporate Headquarters Europe Japan Asia Pacific Pte. Ltd. Xilinx, Inc. Xilinx Europe Xilinx K.K. Xilinx, Asia Pacific 2100 Logic Drive One Logic Drive Art Village Osaki Central Tower 4F 5 Changi Business Park San Jose, CA 95124 Citywest Business Campus 1-2-2 Osaki, Shinagawa-ku Singapore 486040 USA Saggart, County Dublin Tokyo 141-0032 Japan Tel: +65-6407-3000 Tel: 408-559-7778 Ireland Tel: +81-3-6744-7777 www.xilinx.com www.xilinx.com Tel: +353-1-464-0311 japan.xilinx.com www.xilinx.com © Copyright 2012 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Printed in the U.S.A. PN 2504.