MSC8157/MSC8157E Broadband Wireless Access DSP Advanced 45 Nm, Six-Core DSP for 3G-LTE (FDD and TDD), HSPA+, LTE Advanced and Wimax Base Station
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Digital Signal Processors MSC8157/MSC8157E Broadband Wireless Access DSP Advanced 45 nm, six-core DSP for 3G-LTE (FDD and TDD), HSPA+, LTE Advanced and WiMAX base station Overview The MSC8157/MSC8157E DSP delivers a The MSC8157/MSC8157E embeds 6 MB The MSC8157/MSC8157E is a six-core DSP high level of performance and integration, of internal memory and supports a variety based on Freescale’s new SC3850 StarCore combining six fully programmable new of advanced, high-speed interface types, ® technology and designed to advance the and enhanced SC3850 DSP cores, each including two Serial RapidIO interfaces, capabilities of wireless broadband equipment. running at up to 1 GHz with an architecture two Gigabit Ethernet interfaces for network ® It delivers industry-leading performance and highly optimized for wireless infrastructure communications, a PCI Express controller, power savings, leveraging 45 nm process applications. Developed by Freescale and one DDR controller for high-speed, industry technology in a highly integrated DSP to integrated on chip, the second-generation standard memory interface and six common provide performance equivalent to 6 GHz MAPLE-B2 baseband accelerator supports public radio interfaces (CPRI). of a single-core device. The MSC8157/ hardware acceleration for Turbo and Viterbi MSC8157E will help equipment manufacturers channel decoding, Turbo encoding and and carriers create solutions and services that rate matching, MIMO MMSE, IRC and ML enable near-term, mainstream adoption of equalization schemes, matrix inversion, CRC next-generation wireless standards such as insertion and check, DFT/iDFT and FFT/iFFT 3G-LTE (FDD and TDD), HSPA+ LTE Advanced calculations and chip rate acceleration. The and WiMAX. The device is designed to lower optional security engine core (SEC) in the system costs by integrating functionality into a MSC8157E accelerates data plane encryption/ single device that previously required multiple decryption and code protection with minimal discrete parts. DSP core intervention. MSC8157 and MSC8157E Block Diagram DDR Interface 64/32-bit 1333 MHz Data Rate JTAG IEEE® 1149.6 I/O Interrupt DDR M3 Shared Memory Concentrator Controller 3072 KB UART Clocks CLASS Non Blocking Switching Fabric Timers Reset DMA 32-ch. Semaphores Two CPRI MAPLE-B2 SEC QUICC SGMII High-Speed data Engine Serial Baseband Virtual StarCore SC3850 Interrupts DSP Core Subsystem Interface Accelerators 32 KB 32 KB Boot ROM L1 L1 ICache DCache Only for the I2C MSC8157E 512 KB L2 Cache/M2 Memory Other Modules x10 Six DSP Cores at 1 GHz Two RGMII Two Serial RapidIO® x1/x2/x4 up to 5 Gbaud SPI Six Lanes CPRI v4.1 up to 6.144 Gbaud PCI Express® x1/x2/x4 up to 5 Gbaud Note: The arrow direction indicates master or slave. Two SGMII Features and Benefits • High-speed, high-bandwidth CLASS fabric • JTAG test access port (TAP) and boundary • Six StarCore DSP SC3850 core subsystems arbitrates between the DSP cores and scan architecture designed to comply ® operating at up to 1 GHz per core and up other CLASS masters to M2 memory, M3 with IEEE standard. 1149.6 profiling and to 48000 MMACS per device memory, DDR controller, MAPLE-B2 and performance monitoring support the configuration registers • Total of 6 MB on internal memory • Reduced power dissipation with wait, • One DDR controller with up to 667 MHz stop and power down low-power • Second-generation multi-accelerator clock (1333 MHz data) rate and 32/64- standby modes platform engine for baseband (MAPLE-B2) bit DDR2/3 SDRAM data bus. Supports • Optimized power management circuitry Highly flexible, programmable Turbo and SODIMMs and up to 2 GB Viterbi decoder supports configurable • Technology: CMOS 45 nm SOI technology • 32-channel DMA controller decoding parameters. It can perform in 29 mm, 29 mm, 783 ball, FC-PBGA up to 440 Mbps of Turbo decoding for • Dual RISC core QUICC Engine subsystem package 3GLTE. Viterbi decoding at up to operating at up to 500 MHz provides parallel packet processing independent of 200 Mbps. Development Support the DSP cores Turbo information bits encoding includes Freescale supplies a complete set of Supports: rate matching up to 1.8 Gbps for 3GLTE CodeWarrior DSP development tools for Two Gigabit Ethernet controllers and WiMAX and up to 900 Mbps for the MSC8157/MSC8157E device. The tools supporting RGMII or SGMII universal mobile telecommunications provide easier and more robust ways for systems (UMTS) Serial peripheral interface designers to develop optimized DSP systems. FFT/iFFT processing up to 1500 million • HSSI that supports ten SerDes lanes, Whether the application targets a 3G-LTE, samples per second including: WCDMA, or WiMAX system, the development DFT/iDFT support up to 900 million Two Serial RapidIO controllers supporting environment gives designers everything they samples per second x1/x2/x4 operation up to 5 Gbaud need to exploit the advanced capabilities of the MSC8157/MSC8157E architecture. CRC check and insertion supporting up One PCI Express controller that supports to 10 Gbps x1/x2/x4 operation • Library of selected, yet fully optimized software kernels for 3G-LTE MMSE/IRC MiMO equalization and Multiplexing capability for RapidIO®, PCI Express®, CPRI, SGMII signals matrix inversion accelerators Support tools include: through the ten SerDes lanes UMTS downlink spreading, scrambling, • Eclipse-based integrated development • SPI, UART and I2C interfaces gain and combining up to 512 physical environment (IDE) channels, including MIMO, STTD, TSTD • Eight software watchdog timers • C and C++ compiler with in-line assembly and closed loop mode 1 operation • 16 16-bit timers and eight 32-bit timers • Librarian per channel. Chip rate despreading/ • Two 32-bit general purpose timers per core • Multicore debugger spreading descrambling/scrambling up to for RTOS support 360 R99 users • Royalty-free RTOS • I/O interrupt concentrator and virtual UMTS uplink batch interpolation, interrupt support • Software simulator despreading, descrambling, combining • Eight hardware semaphores • Profiler and frequency correlation for up to 384 • High-speed run control physical channels with up to 2144 total • 32 GPIO ports multiplexed with interface • Host platform support fingers from up to 24 antenna streams signals and IRQ inputs with max 512 chips delay spread • Optional SEC (MSC8157E) optimized to • MSC8157 application development system (MSC8157ADS) UMTS uplink low latency DCPCCH and process all the encryption/decryption algorithms associated with IPsec, IKE, E-DPCCH interpolation, despreading Contact your local sales office or WTLS/WAP, SSL/TLS, AES, DES, and descrambling of up to 400 physical representative for availability. channels with up to 3200 EOL total RC-4, SNOW-3G and Kasumi for fingers from up to 24 antenna streams 3G-LTE and 3GPP 2 UMTS path searcher and RACH • Boot options: Ethernet, Serial RapidIO, I C correlations in frequency domain and SPI UMTS frequency domain equalization • Three input clocks and six PLLs acceleration Learn More: For current information about Freescale products and documentation, please visit freescale.com/DSP. Freescale, the Freescale logo, StarCore and CodeWarrior technologies are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine is the trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. Document Number: MSC8157FS REV 0.