The Floating-Point Unit of the Jaguar X86 Core
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The Floating-Point Unit of the Jaguar x86 Core Jeff Rupley, John King, Eric Quinnell, Frank Galloway, Ken Patton, Peter-Michael Seidel, James Dinh, Hai Bui, Anasua Bhowmik AMD Austin and Bangalore Abstract—The AMD Jaguar x86 core uses a fully-synthesized, process, capable of executing in a variety of voltage ranges 128-bit native floating-point unit (FPU) built as a co-processor and frequencies of up to and beyond 2GHz. model. The Jaguar FPU supports several x86 ISA extensions, including x87, MMX, SSE1 through SSE4.2, AES, CLMUL, II. ARCHITECTURE AVX, and F16C instruction sets. The front end of the unit decodes two complex operations per cycle and uses a dedicated The Jaguar FPU is first and foremost a “co-processor” renamer (RN), free list (FL), and retire queue (RQ) for in- architectural model – meaning that the FPU contains a order dispatch and retire. The FPU issues to the execution dedicated decode, rename, out-of-order scheduler, and in- units with a dedicated out-of-order, dual-issue scheduler. order retire units. The FPU accepts up to two micro- Execution units source operands from a synthesized physical instructions per cycle from the dispatch unit in the main register file (PRF) and bypass network. The back end of the processor and is able to retire up to two micro-instructions unit has two execution pipes: the first pipe contains a vector per cycle. Figure 1 shows a block diagram of the Jaguar integer ALU, a vector integer MUL unit, and a floating-point FPU architecture. adder (FPA); the second pipe contains a vector integer ALU, a store-convert unit, and a floating-point iterative multiplier (FPM). The implementation of the unit focused on low-power design and on vectorized single-precision (SP) performance optimizations. The verification of the unit required complex FP Opcode Decode pseudo-random and formal verification techniques. The Jaguar FPU is built in a 28nm CMOS process. F Rename Retire Keywords; AMD Jaguar; floating-point unit; x87; SSE; L [ARF/FF] 44 entry Queue AVX; MMX; AES; CLMUL; F16C; industry implementation [RQ/SRF] I. INTRODUCTION Sched Queue 18 entry The AMD Jaguar x86 core [1][2][3] is a fully- synthesized, two-wide, out-of-order superscalar core FP PRF 72x148b implemented in a 28nm CMOS process, targeted at low- (4R, 3W) 72 entry power, low-cost form factors. Jaguar is the next-generation architecture of the AMD Bobcat x86 core [4], supporting many x86 ISA extensions, including the floating-point VALU0 VALU1 Int Cluster specific sets x87, MMX, SSE1 through SSE4.2, AES, 128 bit load L CLMUL, AVX and F16C. D This paper describes the microarchitecture of the Jaguar C VIMUL St Conv Stc Cluster 128-bit native FPU in detail. The architecture section 128 bit store describes the Jaguar FPU co-processor model, the ISA 64+6 int+flag bus register file formats required, new register rename FPA FPM Flt Cluster optimizations, the optimized, fully-synthesized 4-read, 3- write PRF, and the execution units. The vector integer Figure 1. Jaguar FPU Block Diagram execution units include two vector ALUs and a vector The FPU front-end contains a dual micro-instruction integer multiplier, all on a shared bypass network. The decoder and renamer that drives an 18-entry scheduler floating-point execution units include a store-convert unit queue (SQ) and a 44-entry retire queue (RQ)/status register (STC) that drives results to the main-core data cache, a file (SRF). Operand data is stored into a pointer-renamed floating-point adder (FPA) that shares roots with the AMD floating-point physical register file (PRF) that has 72 K7 [5][6] FPA, and a floating-point iterative multiplier physical entries of 148-bits each (bits in excess of 128-bits derived from the Bobcat FPM design [7] and K7 are for internal bookkeeping and classification). The PRF divide/square-root algorithms [6]. drives four 128-bit read ports to feed two execution pipes The verification section describes a high-level summary and has three 128-bit write ports: two write ports for results of the many verification models used by our team, as well as from the two execution pipes and one dedicated write port the industry tools for formal verification works. Finally, the for incoming data from the main processor data cache. results section describes the IPC uplifts of the Jaguar core The two execution pipes contain three major execution FPU over the Bobcat core FPU on various binaries (such as units each: Pipe0 contains a vector integer arithmetic logic SPECFP 2006). The Jaguar FPU is built in a 28nm CMOS unit (VALU0), a vector integer multiplier (VIMUL), and a floating-point adder (FPA); Pipe1 contains a vector integer excluding 256-bit AVX, the Jaguar PRF implements each arithmetic logic unit (VALU1), a floating-point store and format as a 128-bit renamed microarchitectural register. For convert unit (STC), and a floating-point multiplier (FPM). AVX 256-bit ymm registers, the renamer allocates two The Pipe1 STC drives a 128-bit data bus to the main microarchitectural registers – one for the lower 128-bits and processor data cache, while Pipe0 drives a 64-bit integer one for the upper 128-bits. data and 6-bit flag bus (EFLAGS) to the main processor Register renaming is done using an indirect, physical integer unit. The execution pipes have three separate bypass register scheme and a map table which maps networks, organized into integer, store/convert, and float microarchitectural registers to physical register numbers. clusters. Two tables are used: a speculative table used for renaming of incoming instructions, and a retire-time checkpoint table A. Decode, Schedule and Retire which holds the non-speculative architectural rename state. The front-end control and instruction flow of the FPU 80‐bits b byte begins with the instruction dispatch interface to the FPU = EP w = word from the main processor. This dispatch interface uses a dw double‐word X87 = 16 64‐bits qw quad‐word token system to track machine resources that each = b b b b b b b b w w w w instruction will need, such as queue entries and registers, 1 8 23 dw dw SP s e signif with optimizations for early freeing of tokens in cases where = qw the resources were not needed. Once dispatched, 111 52‐bits MMX 128‐bits DP s e significand instructions proceed to the dual micro-instruction decoders. = b b b b b b b b b b b b b b b b w w w w w w w w These decoders translate micro-instructions into internal FP 115 64‐bits dw dw dw dw EP s e significand operations (ops). The FPU renamer renames two ops per = qw qw cycle and writes into the retire queue and the out-of-order SP SP SP SP DP DP scheduler. SSE The scheduler is a single, unified, dual-pipe, out-of- 128‐bits 128‐bits 0 SP SP SP SP order scheduler. It tracks dependencies and issues ops to the 0 DP DP execution units as execution sources become ready, with AVX.128 256‐bits appropriate control signals used to read operands from the SP SP SP SP SP SP SP SP PRF or the bypass network. The non-shifting scheduler uses DP DP DP DP an age matrix scheme for picking the oldest-ready ops for AVX.256 each pipe [8]. Some ops, such as floating-point adds and Figure 2 Supported PRF ISA formats multiplies, can only issue in one pipe based on execution AVX 128-bit instructions define the upper 128-bits of a resources. Other ops, such as those executed on vector ymm 256-bit result to be zeroed out. Since the Jaguar FPU integer ALUs, can issue in either pipe. Ops are statically renaming is done at a 128-bit granularity, a direct bound to a single pipe before being written into the implementation would require holding a dedicated scheduler queue using a counter-based pipe-balancing microarchitectural register of all zeros. The Jaguar FPU algorithm. The scheduler can issue up to two ops per cycle – optimization of these static-zero cases uses an additional one op to each execution pipe. The scheduler pre-reserves renamer bit, one per microarchitectural renamed register result bus cycles on each pipe using each op’s pre-assigned called a “zero-bit” (ZBit), to track “all-zero” registers. This latency to avoid result bus contention. bit allows for the architectural state to be correctly The retire unit can retire up to two FPU ops per cycle represented without allocating an entire PRF entry full of and coordinates architectural register file updates, status zeros. word updates, and exception processing with the retire unit When the ZBit is set by an instruction, the renamer does in the main processor. not allocate a new physical register to map to the zeroed out architectural register. When the zeroing instruction retires, B. PRF, Rename, and ZBits the physical register that had been previously backing that The Jaguar FPU supports x87/MMX, SSE, and AVX same architectural register is freed as usual. However, no register sets via a unified rename unit and unified physical new register will be mapped, and instead only the ZBit will register file. The PRF size was a key design consideration; be set in the architectural map table. This scheme allows for the goals of high performance, low power, and ISA support more physical registers to be available for other in-flight were in tension, so multiple techniques were used to keep instructions, ultimately allowing the FPU to keep the the PRF size manageable while still allowing for high number of PRF entries low.