CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c/su05 Review CS61C : Machine Structures • Benchmarks Lecture #29: Intel & Summary • Attempt to predict performance • Updated every few years • Measure everything from simulation of desktop graphics programs to battery life • Megahertz Myth • MHz ≠ performance, it’s just one factor 2005-08-10 Andy Carle CS 61C L29 Intel & Review (1) A Carle, Summer 2005 © UCB CS 61C L29 Intel & Review (2) A Carle, Summer 2005 © UCB MIPS is example of RISC MIPS vs. 80386 • RISC = Reduced Instruction Set Computer • Address: 32-bit • 32-bit • Term coined at Berkeley, ideas pioneered • Page size: 4KB • 4KB by IBM, Berkeley, Stanford • Data aligned • Data unaligned • RISC characteristics: • Destination reg: Left • Right • Load-store architecture •add $rd,$rs1,$rs2 •add %rs1,%rs2,%rd • Fixed-length instructions (typically 32 bits) • Regs: $0, $1, ..., $31 • %r0, %r1, ..., %r7 • Three-address architecture • Reg = 0: $0 • (n.a.) • RISC examples: MIPS, SPARC, • Return address: $31 • (n.a.) IBM/Motorola PowerPC, Compaq Alpha, ARM, SH4, HP-PA, ... CS 61C L29 Intel & Review (3) A Carle, Summer 2005 © UCB CS 61C L29 Intel & Review (4) A Carle, Summer 2005 © UCB MIPS vs. Intel 80x86 MIPS vs. Intel 80x86 • MIPS: “load-store architecture” • MIPS: “Three-address architecture” • Only Load/Store access memory; rest • Arithmetic-logic specify all 3 operands operations register-register; e.g., add $s0,$s1,$s2 # s0=s1+s2 lw $t0, 12($gp) add $s0,$s0,$t0 # s0=s0+Mem[12+gp] • Benefit: fewer instructions ⇒ performance • Benefit: simpler hardware ⇒ easier
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